1 2 3 4 5 6 7 8

Programming Logic
USB1 F1 +5V
VUSB
1
R17 22R D_N
2 6V 500mA R18
R19 22R D_P
3 1k
4 D3
GND R20 D5
5 RSB6.8S
A 10k 1N5819 A
G Boot Mode Configuration

1
Header 5
U6 R4 10K
S1 3.3V
D3 2S 2 3 Auto-Reset
IN OUT 3.3V
Q4 EN
1 GND
GND GND AO3401 GND Boot Mode Configuration RESET C

S9013
C58 C59 Pin Default Boot Download C53 B R5 10K DTR
P-CH: G < S ON HT7333-1 10uF 1uF 4.7uF T1
C60 GPIO0 1 1 0 E
1uF U0TXD 1 1 x
GPIO2 0 x 0
GPIO4 0 x x
GND MTDO 1 x x
GND GND GND
GPIO5 1 1 x
U7 JP4

S9013
E
If U0TXD, GPIO2, GPIO5 are floating, R6 10K R7 10K RTS
4 3 VBAT S2 3.3V B
+5V VCC BAT 1 GPIO0 determines boot mode T2 C
C61 R21 2 2 0
GND GND
10uF 330R C63 If DTR is LOW, toggling RTS from HIGH to LOW resets to run mode. BTN-0
5 1 Header 2
PROG CHRG 220nF If RTS is HIGH, toggling DTR from LOW to HIGH resets to bootloader.
R22 TP4054
GND 2K
D4 GND GND GND
LED1

GND

B B

Power Supply

Wireless Shell module & 2.54 Headers USB - UART Bridge

U8 Wireless_Shell

+5V
JP2 JP3
C 1 44 37 32 +5V C
Vext Vext GND 20 20 R2
2 43 38 DIO1
Vext GND 19 19 U1 4.7K
39 DIO2 C1 1uF
18 18
3 42 EN 33 7 9
3.3V 3V3 GND 17 17 REGIN !RST
4 41 36 25 GND C2 0.1uF 8
3V3 GND 16 16 VBUS
21 DIO0 12
15 15 SUSPEND
LoRa_Reset 5 40 MOSI U0TXD 12 C3 1uF 6 11
LoRa_RST MOSI 14 14 VDD !SUSPEND
11 6 39 10 GND U0RXD 13 GND
GPIO11 GPIO10 13 13
6 7 38 9 22 15 D_P 4 2
GPIO6 GPIO9 12 12 D+ RI
7 8 37 17 MISO 2 1
GPIO7 GPIO17 11 11 DCD
8 9 36 16 23 0 D_N 5 28 DTR
GPIO8 GPIO16 10 10 D- DTR
SCK 10 35 4 CS 4 27
SCK GPIO4 9 9 DSR
CS 11 34 0 SCK 16 26 U0RXD
CS GPIO0 8 8 TXD
23 12 33 2 8 17 25 U0TXD
GPIO23 GPIO2 7 7 RXD
MISO 13 32 15 7 9 0 24 RTS
MISO GPIO15 6 6 GND@EXP RTS
22 14 31 13 6 10 3 23
GPIO22 GPIO13 D2 5 5 GND CTS
U0RXD 15 30 12 11 MOSI
RXD GPIO12 4 4
U0TXD 16 29 DIO0 LoRa_Reset GND CP2102
TXD DIO0 R9 3 3
21 17 28 25 GND GND
GPIO21 GPIO25 GND 2 2
36 18 27 33 10K
GPI 36 GPIO33 1 1
LED1
GPIO32

Header 20 Vext GND Header 20 +5V 3.3V GND

GPI 37
GPI 38
GPI 39

DIO2
DIO1
ANT

EN
19
20
21
22
23
24
25
26
DIO2
DIO1
ANT

D D
EN
37
38
39

32

Title
Heltec Automation
Size Number Revision
E2 Wireless Shell Reference Hardware Design
A3
U.FL Antenna
Date: 2019/6/2 www.heltec.org
Sheet of
File: E:\DreamSpark\..\客户用原理图(基于V2).SchDoc
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