Unit 2

Shri Vile Parle Kelavani Mandal’s Institute of Technology, Dhule
Unit 2
Memory interfacing
Course Instructor
Dr. Vishal Moyal
Department of Electrical Engineering

Contents
• Unit 2: Memory interfacing 7 Hours

Types of main memories, Compatibility between memory and system
BUS, Address space, Partitioning of address space, Special chips for
address decoding, ROM and RAM interfacing, i/o interfacing: memory
map i/o, i/o map i/o scheme. Programmable peripheral interface. Data
transfer techniques and their implementation: Programmed data
transfer, DMA mode of transfer, I/O port, Device polling in interrupt
driven mode of data transfer, DMA controller and data transfer in
DMA mode, Serial mode of data transfer

Course Outcome & TLO

CO502.2:
TLO CO TLO Description

What is an Interface?
• An interface is a concept that refers to a point of interaction between

components, and is applicable at the level of both hardware and
software.
• This allows a component, (such as a graphics card or an Internet
browser), to function independently while using interfaces to
communicate with other components via an input/output system and
an associated protocol.

Example Block Diagram
AddressLines
8085 Data Lines Memory
Control Lines
Interface
8085 Interfacing Pins
Higher AddressBus A15 –A8
Lower Address/Data Bus AD7–AD0

8085 ALE
IO/M
RD
WR
READY

Buses of 8085
• Address Bus
– Used to address memory & I/Odevices
– 8085 has a 16-bit address bus
Higher-orderAddress Lower-orderAddress
A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
• Data Bus
– Used to transfer instructions and data
– 8085 has a 8-bit data bus
Higher Order Address Bus
• The higher order address bus is a unidirectional bus.

• It carries most significant 8-bits of a 16-bit address of memory or I/O
device.
• Address remains on lines as long operation is not completed.

Lower Order Address/Data Bus
• This bus is bidirectional and works on time division multiplexing

between address and data.
• During first clock cycle, it serves as a least significant 8-bits of
memory/ IO address.
• For second and third clock cycles it acts as data bus and carries data.

Demultiplexing Address/Data Lines
• 8085 identifies a memory location with its 16 address lines, (AD0 to

AD7) & (A8 to A15) 8085 performs data transfer using its data lines,
AD0 to AD7
• Lower order address bus & Data bus are multiplexed on same lines
i.e. AD0 to AD7.
• Demultiplexing refers to separating Address & Data signals for
read/write operations.

Demultiplexing of address and data lines

Generating Control Signals

IO/M =0 1
1 Memory Read
RD=0
1
0 Memory Write
WR=1
0 IO Read
1
0 IOWrite
0
Generating Control Signals …

IO/M =0 1
0 Memory Read
RD=1
1
1 Memory Write
WR=0
0 IO Read
0
0 IOWrite
1

IO/M =0 0
1 Memory Read
RD=0
0
0 Memory Write
WR=1
1 IO Read
1
1 IOWrite
0

IO/M =1 0
0 Memory Read
RD=1
0
1 Memory Write
WR=0
1 IO Read
0
1 IOWrite
1
Types of Memory
• Read Only Memory (ROM)

• Random Access Memory (RAM)

ROM
• ROM is a read only memory.

• It retains the information even if power is turned off.
• It contains permanently stored instructions that help in
staring up of a computer e.g. BIOS or Basic Input
Output System.
• These are of following three basic types
• PROM, EPROM, EEPROM

PROM
• The Programmable Read Only Memory can be

programmed only once in its lifetime.
• Information once stored can not be erased.
• Requires special hardware circuit to program it.

EPROM
• Stands for Erasable Programmable Read Only

Memory.
• These ROMs can be erased and programmed again
and again.
• Can be erased with UV light or electricity.
• Main disadvantage is that it takes 15 to 20 minutes to
erase it.

EEPROM
• Stands for Electrically Erasable Programmable Read

Only Memory.
• Information can be erased electrically at register level
rather than erasing entire information.
• It requires lesser erasing time.

The Design and Operation of Memory

• Memory in a microprocessor system is where information (data and
instructions) is kept.
• It can be classified into two main types:
• Main memory (RAM and ROM)
• Storage memory (Disks , CD ROMs, etc.)
• The simple view of RAM is that it is made up of registers that are
made up of flip-flops (or memory elements).
• The number of flip-flops in a memory register determines the size of
the memory word.
• ROM on the other hand uses diodes instead of the flip-flops to
permanently hold the information.
Basic RAM Cell
• RAM is a type of computer memory that can be accessed randomly

i.e. any location can be accessed any time within chip.
• It is most common type of memory found in computers, printers etc.
• It is basically of two types:
• SRAM
• DRAM

SRAM
• SRAM stands for Static Random Access Memory.

• This memory is made up of flip-flops and stores the
bit as a voltage.
• Each cell requires 6 transistors hence chip has low
density but high speed.
• More expensive and consumes more power.
• Often known as cache memory in high speed PCs.

Basic SRAM Cell

DRAM
• DRAM stands for Dynamic Random Access Memory.

• This memory is made up of MOS transistor gates and
it stores the bit as charge.
• High density, low power consumption, cheap as
compared to SRAM.
• Due to leakage of charge requires frequent refreshing
and hence extra circuitry.

Basic DRAM

Accessing Information in Memory
• For the microprocessor to access (Read or Write) information in

memory (RAM or ROM), it needs to do the following:
• Select the right memory chip (using part of the address bus).
• Identify the memory location (using the rest of the address bus).
• Access the data (using the data bus).

Tri-State Buffers
• An important circuit element that is used extensively in memory.

• This buffer is a logic circuit that has three states:
• Logic 0, logic1, and high impedance.
• When this circuit is in high impedance mode it looks as if it is
disconnected from the output completely.
The Output is Low The Output is High High Impedance

The Tri-State Buffer
• This circuit has two inputs and one output.

• The first input behaves like the normal input for the circuit.
• The second input is an enable.
• If it is set high, the output follows the proper circuit behavior.
• If it is set low, the output looks like a wire connected to nothing.
Input Output OR Input Output
Enable Enable

The Basic Memory Element
• The basic memory element is similar to a D latch.

• This latch has an input where the data comes in. It has an enable input
and an output on which data comes out.
Dat a Input Data Output

D Q
Enable
EN

The Basic Memory Element …
• However, this is not safe.

• Data is always present on the input and the output is always set to the
contents of the latch.
• To avoid this, tri-state buffers are added at the input and output of the
latch.
Data Input Data Output

D Q
WR RD
Enable
EN

The Basic Memory Element
• The WR signal controls the input buffer.

• The bar over WR means that this is an active low signal.
• So, if WR is 0 the input data reaches the latch input.
• If WR is 1 the input of the latch looks like a wire connected to
nothing.
• The RD signal controls the output in a similar manner.

A Memory Register
• If we take four of these latches and connect them together, we would

have a 4-bit memory register
D D D D
Q Q Q Q
EN EN EN EN
EN
RD O0 O1 O2 O3

A group of memory registers
• Expanding on this scheme to add more memory registers we get the

WR
D0
o o
D1
o
D2
o
D3
diagram to the right. DQ DQ DQ DQ
EN EN EN EN
DQ DQ DQ DQ
EN EN EN EN
DQ DQ DQ DQ
EN EN EN EN
DQ DQ DQ DQ
EN EN EN EN
o o o o
RD
Department of Electrical Engineering 9

Externally Initiated Operations
• External devices can initiate (start) one of the 4 following operations:

• Reset
• All operations are stopped and the program counter is reset to 0000.
• Interrupt
• The microprocessor’s operations are interrupted and the
microprocessor executes what is called a “service routine”.
• This routine “handles” the interrupt, (perform the necessary
operations). Then the microprocessor returns to its previous
operations and continues.

A group of Memory Registers

• If we represent each memory location (Register) as a block we get the
following
I0 I1 I2 I3
WR Input Buffers
EN0 Memory Reg. 0
EN1 Memory Reg. 1
EN2 Memory Reg. 2
EN3 Memory Reg. 3
Output Buffers
RD
O0 O1 O2 O3

The Design of a Memory Chip
• Using the RD and WR controls we can determine the direction of flow

either into or out of memory.
• Then using the appropriate Enable input we enable an individual
memory register.
• What we have just designed is a memory with 4 locations and each
location has 4 elements (bits).
• This memory would be called 4 X 4 [Number of location X number
of bits per location].

The Enable Inputs
• How do we produce these enable line?

• Since we can never have more than one of these enables active at the
same time, we can have them encoded to reduce the number of lines
coming into the chip.
• These encoded lines are the address lines for memory.

• So, the previous diagram would now look like the as following
I0 I1 I2 I3
WR Input Buffers
A D Memory Reg. 0
d e
A1 d c Memory Reg. 1
r o
e d Memory Reg. 2
A0
s e Memory Reg. 3
s r
RD Output Buffers
O0 O1 O2 O3

• Since we have tri-state buffers on both the inputs and outputs of the
flip flops, we can actually use
WR ne set of pins only.

Input Buffers
The
A D chipMemory
d e
would Reg. 0 now D0
A1
look
d c li
r o
Memory Reg. 1 D1 A1 D1
e d Memory Reg. 2 D2 D2
A0 A0
s e Memory Reg. 3
s r D3 D3
RD Output Buffers
RD WR

The steps of writing into Memory
• What happens when the programmer issues the STA instruction?

• The microprocessor would turn on the WR control (WR = 0) and turn
off the RD control (RD = 1).
• The address is applied to the address decoder which generates a single
Enable signal to turn on only one of the memory registers.
• The data is then applied on the data lines and it is stored into the
enabled register.

Dimensions of Memory
• Memory is usually measured by two numbers: its length and its width
(Length X Width).
• The length is the total number of locations.
• The width is the number of bits in each location.
• The length (total number of locations) is a function of the number of
address lines.
• # of memory locations = 2( # of address lines)
• So, a memory chip with 10 address lines would have
• 210 = 1024 locations (1K)
• Looking at it from the other side, a memory chip with 4K locations would
need
• Log2 4096=12 address lines
The 8085 and Memory
• The 8085 has 16 address lines.

• That means it can address 216 = 64K memory locations.
• Then it will need 1 memory chip with 64 k locations, or 2 chips with
32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc.
• how would we use these address lines to control the multiple chips?

Chip Select
• Usually, each memory chip has a CS (Chip Select) input.

• The chip will only work if an active signal is applied on that input.
• To allow the use of multiple chips in the make up of memory, we need
to use a number of the address lines for the purpose of “chip
selection”.
• These address lines are decoded to generate the 2n necessary CS
inputs for the memory chips to be used.

Chip Selection Example
• Assume that we need to build a memory system made up of 4 of the 4

X 4 memory chips we designed earlier.
• We will need to use 2 inputs and a decoder to identify which chip will
be used at what time.
• The resulting design would now look like the one on the following
slide.

Chip Selection Example

RD
WR
D0
D1
RD WR RD WR RD WR RD WR
A0 A0 A0 A0
A1 A1 A1 A1
CS CS CS CS
A0
A1
A2 2 X4
A3 Decoder

Memory Map and Addresses
• The memory map is a picture representation of the address range and

shows where the different memory chips are located within the
address range.
EPROM Address Range of EPROM Chip

3FFF
4400
RAM 1 Address Range of 1st RAM Chip
5FFF
6000
Address Range
RAM 2 Address Range of 2nd RAM Chip

8FFF
9000
RAM 3 Address Range of 3rd RAM Chip
A3FF
A400
RAM 4 Address Range of 4th RAM Chip
F7FF
FFFF

Address Range of a Memory Chip
• The address range of a particular chip is the list of all addresses that
are mapped to the chip.
• An example for the address range and its relationship to the memory
chips would be the Post Office Boxes in the post office.
• Each box has its unique number that is assigned sequentially (memory
locations).
• The boxes are grouped into groups (memory chips).
• The first box in a group has the number immediately after the last box
in the previous group.

Address Range of a Memory Chip

• The above example can be modified slightly to make it closer to our
discussion on memory.
• Let’s say that this post office has only 1000 boxes.
• Let’s also say that these are grouped into 10 groups of 100 boxes each.
• Boxes 0000 to 0099 are in group 0, boxes 0100 to 0199 are in group 1
and so on.
• We can look at the box number as if it is made up of two pieces:
• The group number and the box’s index within the group.
• So, box number 436 is the 36th box in the 4th group.
• The upper digit of the box number identifies the group and the
lower two digits identify the box within the group.
The 8085 and Address Ranges
• The 8085 has 16 address lines. So, it can address a total of 64K
memory locations.
• If we use memory chips with 1K locations each, then we will need 64
such chips.
• The 1K memory chip needs 10 address lines to uniquely identify the
1K locations. (log21024 = 10)
• That leaves 6 address lines which is the exact number needed for
selecting between the 64 different chips (log2 64 = 6).

The 8085 and Address Ranges
• Now, we can break up the 16-bit address of the 8085 into two pieces:
Chip Selection Location Selection within the Chip

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Depending on the combination on the address lines A15 - A10 ,

the address range of the specified chip is determined.

Chip Select Example
• A chip that uses the combination A15 - A10 = 001000 would

have addresses that range from 2000H to 23FFH.
• Keep in mind that the 10 address lines on the chip gives a range of 00
0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips.
• The memory chip in this example would require the following circuit
on its chip select input:
A10
A11
A12 CS
A13
A14
A15

Chip Select Example
• If we change the above combination to the following:

A 10
A 11
A 12 CS
A 13
A 14
A 15
• Now the chip would have addresses ranging from: 2400 to 27FF.
• Changing the combination of the address bits connected to the chip
select changes the address range for the memory chip.
Chip Select Example

• To illustrate this with a picture:
• In the first case, the memory chip occupies the piece of the memory
map identified as before.
• In the second case, it occupies the piece identified as
Before After
0000 0000
2000
23FF 2400
27FF
FFFF FFFF

High-Order vs. Low-Order Address Lines
• The address lines from a microprocessor can be classified into two

types:
• High-Order
• Used for memory chip selection
• Low-Order
• Used for location selection within a memory chip.
• This classification is highly dependent on the memory system design.

Data Lines
• All of the above discussion has been regarding memory length.
• Lets look at memory width.
• We said that the width is the number of bits in each memory word.
• We have been assuming so far that our memory chips have the right width.
• What if they don’t?
• It is very common to find memory chips that have only 4 bits per
location. How would you design a byte wide memory system using
these chips?
• We use two chips for the same address range. One chip will supply 4 of
the data bits per address and the other chip supply the other 4 data bits
for the same address.
Data Lines
CS
A0
…
A9
CS CS
D0
…
D3
D4
…
D7

Address decoders
2 to 4decoder
O0 CS Memory 1
A12 S1 O1 CS Memory 2
A11 S0 O2 CS Memory 3
O3 CS Memory 4
E
A13
A10 - A0

The Overall Picture

Chip Selection
A15-A 10 Circuit
8085
A15-A8 CS
ALE
A9-A0 1K Byte
AD7-AD0 Latch Memory
A7-A0 Chip
WR RD IO/M D7-D0
RD WR

Types of Address Decoding
• There are two types of address decoding techniques

• Absolute / Exhaustive / Full Decoding
• Partial / Linear Select Decoding

Absolute Decoding
• In this type of scheme all the 16 bits of the 8085 address bus are used
to select a particular location in memory chip.
• Advantages:
• Complete Address Utilization
• Ease in Future Expansion
• No Bus Contention, as all addresses are unique.
• Disadvantages
• Increased hardware and cost.
• Speed is less due to increased delay.

Partial Decoding
• In this scheme minimum number of address lines are used as required

to select a memory location in chip.
• Advantages:
• Simple, Cheap and Fast.
• Disadvantages:
• Unutilized space & fold back (multiple mapping).
• Bus Contention.
• Difficult future expansion.

Interfacing I/O Devices
• Using I/O devices data can be transferred between the

microprocessor and the outside world.
• This can be done in groups of 8 bits using the entire
data bus.
• This is called parallel I/O.
• The other method is serial I/O where one bit is
transferred at a time using the SID and SOD pins on
the Microprocessor.
Types of Parallel Interface
• There are two ways to interface 8085 with I/O devices in parallel data
transfer mode:
• Memory Mapped I/O
• I/O Mapped I/O

Memory Mapped I/O
• It considers them like any other memory location.

• They are assigned a 16-bit address within the address
range of the 8085.
• The exchange of data with these devices follows the
transfer of data with memory.
• The user uses the same instructions used for memory.

I/O Mapped I/O
• It treats them separately from memory.

• I/O devices are assigned a “port number” within the 8-bit address
range of 00H to FFH.
• The user in this case would access these devices using the IN and
OUT instructions only.

I/O mapped I/O v/s Memory Mapped I/O

Memory Mapped I/O I/O Mapped I/O
I/O is treated as memory. I/O is treated I/O.
16-bit addressing. 8- bit addressing.
More Decoder Hardware. Less Decoder Hardware.
Can address 216=64k devices. Can address 28=256 devices.
Whole memory address space is
Less memory is available.
available.
Memory related instructions such Special instructions are used
MOV, STA are used like IN, OUT.
I/O mapped I/O v/s Memory Mapped I/O

Memory Mapped I/O I/O Mapped I/O
Control signals used are Control signals used are
MEMR , MEMW IOR , IOW
Arithmetic and logic Arithmetic and logic
operations can be operations cannot be
performed on data. performed on data.
Data transfer between Data transfer between
register and I/O. Accumulator and I/O.

The interfacing of output devices
• Output devices are usually slow.

• Also, the output is usually expected to continue appearing
on the output device for a long period of time.
• Given that the data will only be present on the data lines for
a very short period (microseconds), it has to be latched
externally.
• To do this the external latch should be enabled when the
port’s address is present on the address bus, the IO/M’
signal is set high and WR is set low.
The interfacing of output devices …
• The resulting signal would be active when the output

device is being accessed by the microprocessor.
• Decoding the address bus (for memory-mapped
devices) follows the same techniques discussed in
interfacing memory.




Interfacing of Input Devices
• The basic concepts are similar to interfacing of output devices.

• The address lines are decoded to generate a signal that is active when
the particular port is being accessed.
• An IORD’ signal is generated by combining the IO/M’ and the RD’
signals from the microprocessor.
• A tri-state buffer is used to connect the input device to the data bus.
• The control (Enable) for these buffers is connected to the result of
combining the address signal and the signal IORD’.

Interfacing of Input Devices …



The interfacing of I/O devices using decoder

The interfacing of I/O devices using decoder

Absolute Decoding

Partial Decoding

7 segment LED Display

7 segment LED Display as an output device

7 segment LED Display as an output device

DIP switches as input device

DIP switches as input device …

Memory Mapped I/O

Memory Mapped I/O …
1. Decode the address bus to generated the device address pulse.

2. AND the control signal with the device address pulse to generate the
device select (I/O Select) pulse.
3. Use the device select pulse to enable the I/O port.



• Output port and its address


• Input port and its address


• Instructions

Example 1
• Identify the scheme of
interfacing.
• Determine the port address

if all the unconnected lines
are assumed to be
connected to ‘0’

Example 2
• Identify the scheme of
interfacing.
• Determine the port address

if all the unconnected lines
are assumed to be connected
to ‘0’.

8255 : Programmable Peripheral Interface
• Programmable Peripheral Interface (PPI).

• It interfaces i/o device to the CPU.
• It is used for handshake and non-handshake applications with i/o
devices.
• It is a parallel port device.
• With the help of Control Word Register (CWR) ports can be
programmed as input or output.

8255 Functional Description

• 24 input/output lines
• Port A (8-bit input/output port, Bidirectional)
• Port B (8-bit input/output port)
• Port C (8-bit input/output port, 2 4-bit ports, to produce handshake signals
for Port A and B)
• 8 data lines write data bytes/control word to port or read data bytes/status
word from port
• Reset
• Initialize control register to 9Bh and all port as input port.
• Address inputs (A0, A1)
• Allows to access one of the 3 ports or the control word register.
• Port A: 00, Port B: 01, Port C: 10, Control Register: 11.
8255 Pin Diagram

8255 Internal Architecture

8255 Control Word Register (I/O Mode)

8255 Control Word Register (BSR Mode)

Data Transfer Techniques
• Need of Data Transfer Techniques

• In all process content applications, 𝜇p would like to communicate
with different I/O devices for data transfers, i.e., transfer of data
between circuitry external to the microprocessor and the processor
itself.
• This transfer of data is in addition to transfers between the
microprocessor and memory and is referred to as input/output or
I/O.
• Data transfer may take place between microprocessor and memory,
microprocessor and I/O devices and memory & I/O devices.

Data Transfer Techniques
• Need of Data Transfer Techniques

• Not much of the problems arise for the data communication
between microprocessor and memory as same technology is used
in the manufacturing of memory and microprocessor however
problems arise due to mismatch of the speed of the I/O devices and
the speed of microprocessor or memory.
• To overcome this problem of speed mismatch between the
microprocessor and I/O devices we introduce data transfer schemes
of 8085 microprocessor

Data transfer Techniques …

Parallel Transmission
• In Parallel Transmission, various bits are sent together simultaneously with
a single clock pulse.
• It is a fast way to transmit as it uses many input/output lines for transferring
the data.
• The basic difference between a parallel and a serial communication channel
is the number of electrical conductors used at the physical layer to convey
bits.
• Parallel communication implies more than one such conductor.
• For example, an 8-bit parallel channel will convey eight bits (or a byte)
simultaneously, whereas a serial channel would convey those same bits
sequentially, one at a time. If both channels operated at the same clock
speed, the parallel channel would be eight times faster.
Parallel Transmission …
• In order to transmit n bits, n wires or
lines are used. Thus each bit has its
own line.
• All n bits of one group are transmitted
with each clock pulse from one device
to another i.e. multiple bits are sent
with each clock pulse.
• Parallel transmission is used for short
distance communication.

Programmed I/O Mode of Data Transfer
• Programmable I/O is the most simple type of I/O technique for the
exchanges of data or any types of communication between the
processor and the external devices.
• The processor executes a program that gives it direct control of the I/O
operation, including sensing device status, sending a read or write
command, and transferring the data.
• When the processor issues a command to the I/O module, it must wait
until the I/O operation is complete.
• If the processor is faster than the I/O module, this is wasteful of
processor time.

Steps in Programmed I/O
• The processor is executing a program and encounters an instruction

relating to I/O operation.
• The processor then executes that instruction by issuing a command to
the appropriate I/O module.
• The I/O module will perform the requested action based on the I/O
command issued by the processor (READ/WRITE) and set the
appropriate bits in the I/O status register.
• The processor will periodically check the status of the I/O module until
it find that the operation is complete.

Programmed I/O Mode Data Transfer

Synchronous Mode
• Synchronous means “at the same time” i.e. the device which sends the
data and the device which receives the data are synchronized with the
same clock speed.
• This technique of data transfer can be employed when the speed of I/O
devices and the speed of CPU are compatible.
• This technique can also be used when the speed characteristic of the
I/O devices are known, so we can delay the data transfer for a fixed
time.
• When the device is ready with the data it can indicate to 8085 on the
READY pin.

Asynchronous Mode
• Asynchronous means “at regular interval”.

• In this method data transfer is not based on the predetermined timing
pattern.
• This technique is suitable when timing characteristics of I/O devices
doesn’t match with the speed of microprocessor and are not known.
• In this mode the status of I/O devices i.e. whether the device is ready
or not, is checked by the microprocessor before the data are
transferred.

Asynchronous Mode …
• The microprocessor initiates the I/O device to get ready by sending a

REQUEST signal to the I/O device and then continuously checks the
status of the I/O device till the I/O device become ready to transfer
data.
• When the I/O device becomes ready it send the ACKNOWLEDGE
signal to processor and then the processor executes the I/O
instructions.
• This method of data transfer is also known as Handshaking mode of
data transfer because some signals are exchanged between
microprocessor and the I/O device before the actual transfer occurs.

Asynchronous Mode

Interrupt Driven Data Transfer
• In the asynchronous mode of transfer, microprocessor is busy all the

time in checking for the availability of data from the slower I/O
devices.
• And it also busy in checking if I/O device is ready for the data transfer
or not.
• In other words in this data transfer scheme, some of the
microprocessor time is wasted in waiting while an I/O device is getting
ready.
• To overcome this problem interrupt driven I/O data transfer
introduced.

Interrupt Driven Data Transfer ..
• In this interrupt driven I/O data transfer method the I/O device informs
the microprocessor for the data transfer whenever the I/O device is
ready.
• This is achieved by interrupting the microprocessor by using the
interrupt pins of microprocessor.

• In the beginning the microprocessor initiates data transfer by

requesting the I/O device ‘to get ready’ and then continue executing
its original program rather wasting its time by checking the status of
I/O device.
• Whenever the device is ready to accept or supply data, it informs the
processor through a control signal.
• This control signal known as interrupt (INTR) signal.
• In response to this interrupt signal, the microprocessor sends back an
interrupt acknowledge signal to the I/O device

• Interrupts driven data transfer is better from asynchronous mode but it

is still not very effective technique when data needs to be transferred
in large amounts because it requires an interrupt for every character
read or written.
• This leads us to an another approach called direct memory
access(DMA) mode.

DMA Mode of Data Transfer
• Direct memory access (DMA) is a method that allows an input/output

(I/O) device to send or receive data directly to or from the main
memory, bypassing the CPU to speed up memory operations.
• The process is managed by a chip known as a DMA controller
(DMAC)
• DMA channels are used to communicate data between the peripheral
device and the system memory. A DMA channel enables a device to
transfer data without exposing the CPU to a work overload.

DMA Mode of Data Transfer …
• Without the DMA channels, the CPU copies every piece of data using
the peripheral bus from the I/O device which does not allow the
microprocessor to perform other work until the operation is completed.
• With DMA, the CPU can process other tasks while data transfer is
being performed.
• The transfer of data is first initiated by the CPU. During the transfer of
data between the DMA channel and I/O device, the CPU performs
other tasks.
• When the data transfer is complete, the CPU receives an interrupt
request from the DMA controller.

DMA Mode of Data Transfer …

• For the data transfer using DMA process, a request to the
microprocessor in form of HOLD signal, by the I/O device is sent.
• When microprocessor receipt of such request, the microprocessor
relinquishes the address and data buses and informs the I/O devices of
the situation by sending Acknowledge signal HLDA after completing
the current machine cycle.
• The DMA controller then takes over the control of the buses of
microprocessor and controls the data transfer between RAM and I/O
device.
• When the data transfer is complete, DMA controller returns the
control over the buses to the microprocessor by disabling the HOLD
signal.
Modes of DMA Transfer
• The different DMA transfer modes are as follows:

• Burst or block transfer DMA
• Cycle steal or single byte transfer DMA.
• Transparent or hidden DMA.

Burst or block transfer DMA
• It is the fastest DMA mode. In this two or more data bytes are
transferred continuously i.e. entire block of data is transferred in one
contiguous sequence.
• Processor is disconnected from system bus during DMA transfer.
• N number of machine cycles are adopted into the machine cycles of
the processor where N is the number of bytes to be transferred.
• So once the DMA controller is granted access to the system bus by the
CPU, it transfer all bytes of data in the data block before releasing
control of the system buses back to the CPU.

Burst or block transfer DMA …
• After receiving HLDA signal, DMA gains control of system bus and
transfers one byte.
• After transferring one byte, it increments memory address, decrements
counter and transfers next byte.
• In this way, it transfer all data bytes between memory and I/O devices.
• After transferring all data bytes, the DMA controller disables HOLD
signal & enters into slave mode.

Cycle steal or single byte transfer DMA
• In this mode only one byte is transferred at a time.

• This is slower than burst DMA.
• In cycle stealing mode, after one byte of data transfer, the control of
the system bus gives back to the CPU so after transfer one byte, it
disables HOLD signal and enters into slave mode.
• Processor gains control of system bus and executes next machine
cycle.

Cycle steal or single byte transfer DMA …
• If count is not zero and data is available then the DMA controller
again sends HOLD signal to the processor and transfer next byte of
data block.
• By continually obtaining and releasing the control of the system bus,
the DMA controller essentially interleaves instructions and data
transfers.

Transparent or Hidden DMA transfer
• Processor executes some states during which is floats the address

and data buses.
• During this process, processor is isolated from the system bus.
• DMA transfers data between memory and I/O devices during
these states.
• This operation is transparent to the processor.
• This is slowest DMA transfer.
• In this mode, the instruction execution speed of processor is not
reduced.
• But, the transparent DMA requires logic to detect the states when
Serial Communication
• Serial communication transmits data one bit at a time, sequentially

over a single communication link to a receiver where each bit has its
clock pulse rate..
• This method is used when data transfer rate is slow and data have to
transmit over a long distances and also where the cost of cable and
synchronization difficulties makes parallel communication
impractical.
• Since the microprocessors process data in bit-parallel mode, the
transmitter performs parallel-to-serial conversion, while the receiver
performs serial-to- parallel conversion.

Serial Communication …

Key Differences Between Serial And Parallel

Transmission
• Serial transmission requires a single line to communicate and transfer data
• Serial transmission used for long distance communication whereas, the
parallel
• Error and noise are least in serial as compared to parallel transmission.
Since one bit follows another in Serial Transmission whereas, in Parallel
Transmission multiple bits are sent together.
• Parallel transmission is faster as the data is transmitted using multiples lines
• Serial transmission cables are thinner, longer and economical in comparison
• Serial Transmission is reliable and straightforward whereas, Parallel
Transmission is unreliable and complicated.

Unit 2

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Unit 2

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Shri Vile Parle Kelavani Mandal’s Institute of Technology, Dhule

Department of Electrical Engineering

• Unit 2: Memory interfacing 7 Hours

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Course Outcome & TLO

TLO CO TLO Description

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• An interface is a concept that refers to a point of interaction between

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Example Block Diagram

8085 Data Lines Memory

8085 Interfacing Pins

Higher AddressBus A15 –A8

Lower Address/Data Bus AD7–AD0

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Higher Order Address Bus

• The higher order address bus is a unidirectional bus.

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Lower Order Address/Data Bus

• This bus is bidirectional and works on time division multiplexing

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Demultiplexing Address/Data Lines

• 8085 identifies a memory location with its 16 address lines, (AD0 to

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Demultiplexing of address and data lines

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Generating Control Signals

Generating Control Signals …

Generating Control Signals …

Generating Control Signals …

• Read Only Memory (ROM)

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• ROM is a read only memory.

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• The Programmable Read Only Memory can be

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• Stands for Erasable Programmable Read Only

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• Stands for Electrically Erasable Programmable Read

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The Design and Operation of Memory

Basic RAM Cell

• RAM is a type of computer memory that can be accessed randomly

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• SRAM stands for Static Random Access Memory.

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Basic SRAM Cell

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• DRAM stands for Dynamic Random Access Memory.

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Accessing Information in Memory

• For the microprocessor to access (Read or Write) information in

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• An important circuit element that is used extensively in memory.

The Output is Low The Output is High High Impedance

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The Tri-State Buffer

• This circuit has two inputs and one output.

Input Output OR Input Output

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The Basic Memory Element

• The basic memory element is similar to a D latch.