Unit 1

MPU(Micro Processor Unit) Organization

 Unit 1: MPU Organization
MPU Organization:
 Instruction set Architectures, Harvard & Von-Neuman Architectures, Micro programmed &
Hardwired Control unit, Floating Point & Fixed-Point Processor, Endianness.
 Intel’s 8086 architecture, Pin groups, Functioning, Segmentation, Address generation,
Stack, Interrupts.

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Block diagram of a
computer system

MP
IC

 Bus: Collection of wires

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Source: T.L Floyd, “Digital Fundamentals”, 9e Bus
 Block diagram of a computer
 All computer systems consists of basic functional blocks that include a CPU,
memory and input/output ports.
 These blocks are connected together with three internal buses: Address bus,
Control bus, Data bus collectively called as system bus.
 A port is a physical interface on a computer through which data are passed to and
from peripherals.
 The memory includes program memory(ROM) to store instructions to be executed
to solve a specific problem and data memory to store data during executing
instructions.

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 Processor
 A processor unit is that part of a computer system or digital system
that implements the operations in the system.
 A Processor IC interfaced with many other components to realize
computer system.
 The user is expected to give instructions to the processor by writing a
program in assembly or high level language.

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Functional units
of a Microprocessor

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Source: T.L Floyd, “Digital Fundamentals”, 9e
 CPU: Block diagram

Processor
Control Unit
Logic Unit

 Processor logic unit is a digital circuit capable of performing different

operations, which are controlled by control unit by generating control
signals.

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Processor Logic Unit(PLU)
 In most of the processors, the different operations are implemented by
means of arithmetic & logical operations.
 Processor logic unit consists of circuits to implement Arithmetic &
Logic operations. These circuits are called as Arithmetic & Logic
Unit(ALU).
 The ALU receives the information(operands) from the registers and
performs a given operation as specified by control unit.

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Simple PLU:
Bus Organization

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Bus Organization
 Different units are connected by buses: Bus organization
 Each register is connected to two multiplexers( MUX) to form
input buses A & B.
 The input buses A & B are applied to a ALU.
 The function selected in the ALU determines the particular
operation that is to be performed.
 The result of the operation goes through the output bus S into the
inputs of all registers.
 The shift operation is implemented in the shifter.

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 Bus Organization: An Example
 Operands:
- MUX A selector: One among 4 registers is to be connected to input bus A
& B , hence at least two select line(bits) are required.

MUX –A MUX-B
Select lines Register
Select lines Register
A1 A0 Selected
B1 B0 Selected
0 0 R0
00 R0
0 1 R1
01 R1
1 0 R2
10 R2
1 1 R3
11 R3

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Number of multiplexers
 One MUX is required to connect a bit of register to ALU, the number MUXs required is
equal number of bits(size of ALU).
E.g: Size of ALU=4 bits => Register Size=4 bits

0 0 0 0

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 Bus Organization: An Example
ALU
 Assume ALU performs 8 different operations.
 Hence, requires at least 3 bits of input to differentiate the operation.
 The ALU performs different operations according to table shown below.

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 Bus Organization: An Example
Shifter
 Assume if Shift select=1, shift the data,
shift select=0, no shift
Decoder
 Decoder select a register to store data after operation.
 Assume decoder generate load signal to different register according to table shown
below. Destination Register
select Selected
D1 D0
00 R0
01 R1
10 R2
11 R3
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 So the control unit is …..

Operation and
Operands

Control Signals
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 Example:
 Assume: Operation to be performed is addition (by user).
R1 R1+R2
 Operation is called as an instruction.
 R2 is source operand & R1 is source as well as destination.

Different Control signals

 MUX A select: 01 to select R1
 MUX B select:10 to select R2
 Function select: 000 for addition
 Shift select:0 no shift
 Destination select: 01 to load data to R1

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 Example contd…
 The macro operation(operation/Instruction) addition involves
many micro operations.
 Micro operations
- Place contents of R1 onto bus A
- Place contents of R2 onto bus B
- Perform Addition in ALU
- No shifting of data(transfer data)
- Select Destination register

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 Example contd…
 So, for the operation assumed, the control signals to be generated are,

 The processor(Control unit & PLU) understands instructions in binary format called
as Machine(Processor) level language.
 It is not possible for the user to give instructions in binary format.
 Hence, we have assembly language & high level language.

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 So,
how to write
instructions?

Mnemonics

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Machine Independent High level languages

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Source: T.L Floyd, “Digital Fundamentals”, 9e
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 Example contd…
 Compiler & assembler generates machine codes, based on instruction format of the
processor.
 Instruction format or control word of the PLU considered:

 Function select is also called as Opcode(Operation Code)

 Machine code of the operation considered:
32H (H-Hexadecimal)

 So, this is one byte(8 bits) instruction.

 Assembly instructions are called instruction set of processor.

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 Timing Sequence
 Each micro operation assumed takes some time for completion.
 The control signals are expected to generate in a sequence starting from source operand
selection.
 Assume, different successive times instants during which control signals generated to
complete the operation.
 T0 is time instant during which control signals for register selection are generated.
T0: Register selection (MUX A Sel=01, MUX B Sel= 10)
T1: Addition (Opcode=000)
T2: Shift( Shift Select=0)
T3: Destination Selection(Decoder input=01)
 To complete all micro operations, at least 4 time instants are required.
 The sequence of time instants form timing sequence.
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 Timing sequence…
 To generate timing sequence, a counter can be used by control unit.
 It is required to generate 4 time instants, a counter with at least 4 states is
required.
 A Simple 2 bit up counter with outputs Q1Q0 with AND gate decoding according
to table shown below.

2-bit counter
Q1
Q0 T3

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Control unit modified

Operation and
Operands

Clock

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 Questions?
 What is instruction code?
 What is micro and macro instruction?
 What is control signal?
 What is mnemonics?
 What is an ALU size?
 What is bus?

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 Control Unit(CU) Basics
 CU generates different control signals needed to perform different operations in data path.
 2 ways to implement: Hardwired & Micro programmed
E.g: Consider a assembly program as follows for the PLU Considered.(Note: Instructions & Mnemonics assumed are
arbitrary.)
Begin
SUB R2,R1
CPL R3
Assembler Directives
AND R2,R3
OR R2,R3
end Instructions

 Assembler directives are used to give information to assembler only, no machine codes are generated, hence called
as pseudo instructions in the program.
(Assembler directives are similar to pre processor directives of high level languages).

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 Assembly Program with machine codes

 If the sequence of machine codes to be generated are known, then a digital circuit can
be designed to generate the machine codes => “Hardwired” Control Unit
 So, hardwired control unit is predesigned hardware capable of generating one
sequence of machine codes.

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 Control unit: Micro programmed

 The sequence of control signals(micro program) necessary to execute

the different instructions are stored in ROM called control ROM( Micro
program memory/Program memory).
 To execute instructions, the control signals stored in the ROM can be
accessed.
 The control signals read from the ROM are used to control the micro
operations associated with different instructions to be executed at any
time.

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 Micro programmed Control unit: Stored Program Concept

Execute

Decode
Fetch

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 Questions
1. Mention different functional units of a computer.
2. What is a processor?
3. What is Processor unit & Control unit ?
4. What is address bus, data bus, control bus?
5. What is address space of the processor?
6. What is the size of the memory supported by processor?

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 Questions
1. What is required in a processor to support memory?
2. What is data memory?
3. What is program memory?
4. What is chip select signal?
5. How many memory chips of size 4k x 4 are required to realize 8k x 8 memory?

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 Instruction Set Architectures(ISAs)
 An instruction set or instruction set architecture (ISA), is the part of the
processor architecture related to programming.
 All processors are supported by instruction set /instructions (Assembly
instructions) which are dependent on organization of different components in PLU.
 Depending upon the way of supporting different instructions, the ISA is majorly
divided into:
-Reduced Instruction Set Computer(RISC)
-Complex Instruction Set Computer(CISC)
 Other types of ISAs:
-Very Long Instruction Word(VLIW), etc….

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 CISC & RISC Design Philosophy: CISC Vs RISC
CISC
 More number of instructions
 Instructions are complex to
understand.
• Hardware support for many
instructions (More silicon Usage)
A programmer can achieve the desired
functionality with a single instruction
which in turn provides the effect of using
more simpler single instructions in RISC.
• Clock cycles per instruction(CPI) is
more.
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RISC
 Lesser no. of instructions.
 Instructions are Easier to
understand.
• Software support for many
instructions/operations.
(Less silicon usage)
Programmer needs to write more code
to execute a task since the instructions
are simpler ones.
 Clock cycles per instruction(CPI)
is less.
CISC & RISC Design Philosophy: CISC Vs RISC
CISC
 Code density is more.
 Less number of registers.
 Memory to memory operations are
supported.
Load & store operations in an instruction
• More number of addressing
modes.
• Variable length instructions.
• Design of Pipelining is Complex.
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RISC
 Code density is less.
 More number of registers.
 No memory to memory operations
are supported.
Load & store operations not in a
instruction (So called as, load-store
architecture)
• Less number of addressing modes.
• Fixed length instructions.
• Design of Pipelining is easier.
 CISC & RISC Design Philosophy: CISC Vs RISC

CISC RISC
 Non Orthogonal Instruction Set  Orthogonal Instruction Set
All instructions are not allowed to operate Allows each instruction to operate on any
on any register and use any addressing register and use any addressing mode.
mode. It is instruction specific. • Examples: ARM, MSP 430, PIC MCUs,
• Examples: 8086
POWERPC

NOTE: The fact is, the designers are not worried about the
architecture(CISC/RISC). So, the features from both the architectures are mixed up
to increase the performance(Increase speed & reduce memory consumption).
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 Questions
 What is code density?
 What is an orthogonal instruction set?
 Why CPI is less in RISC architecture?
 Which is the preferable control unit to support complex operations ?
 What is the advantage/disadvantage of fixed length instructions?
 What is hardware support for an instructions?

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 Von Neumann & Harvard Architecture
 This classification is based on processor architecture design to support
memory.
 Address Space:
- No. of locations a processor/controller can address.
E.g: 8086: Address bus=20 bits, so address space is 1 Mb
(00000H-FFFFFH)
8051: Address bus=16 bits, so address space is 64 Kb
(0000h-FFFFh)

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Von Neumann/Princeton Architecture
 In this architecture, address space is shared between program memory & data memory.
 E.g: 8086
-Total Address space is 1Mb
- The address space is segmented(shared) in to code segment(Program memory) and
data segment (data memory).
 Common memory for program & data.
 Single shared bus(Address, data & control: System bus) for Instruction and Data fetching.
Pgm /data
memory

 The speed of execution is less because sharing of bus.

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complexity of design of processor is less because single bus.
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 Harvard Architecture
 In this architecture, address space is not shared between program memory & data
memory.
 E.g:8051
- Total address space for program memory is 64KB & for data memory is 64KB.
- Program memory & data memory locations are separate.
 Separate memory for program & data.
 Separate buses for Instruction and Data fetching.

 The speed of execution is more because separate buses.

 The processor design is complex.

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Von Neumann & Harvard Architecture
 What is the meaning of common memory for program & data?
- Is it possible to use RAM as program memory(Basic need: Permanent storage)?
- Is it possible to use ROM as data memory?(Basic need:
Read/write during program execution)

Case 1: Microcontrollers
-The flash (EEPROM) is used as a program memory & RAM(SRAM) is used as a data
memory(Integrated into chip).
- Usually based on Harvard architecture.
So, the question is invalid!
(Note: Some microcontrollers are based on Von Neumann also)

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Von Neumann & Harvard Architecture
Case 2: Microprocessor
-The block diagram shows 8086 MPU connected to memory.

 Separate memory! Why it is called as Von Neumann?

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 Von Neumann & Harvard Architecture
Case 3: Modern Microprocessors/ Computers
- The block diagram shows MPU connected to memory

 Common memory! Architecture is Von Neumann

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Von Neumann & Harvard Architecture
Case 4: Modern Microprocessors/ Computers

 Architecture is Von Neumann.

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Von Neumann & Harvard Architecture
Case 5: Modern Microprocessors/ Computers
- The block diagram shows MPU connected to memory

 What does this architecture called?

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Von Neumann/Princeton Architecture

Note: The separate bus for program memory & data memory is applicable
only to on chip memory.

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 Questions
 What is an address space?
 Why execution is faster in a processor based on Harvard architecture?
 What is a cache?

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 Fixed point and Floating point Processors
 Processing can be separated into two categories: fixed point and
floating point.
 These designations refer to the format used to store and manipulate
numeric representations of float data.
 Fixed-point CPUs are designed to represent and manipulate rational
numbers using integer notation.
 Floating-point CPUs represent and manipulate rational numbers in a
manner similar to scientific notation IEEE 754 (Sign, mantissa and an
exponent).
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  The term ‘fixed point’ refers to a fixed number of digits after the
decimal point.
E.g. 123.45, 1234.56, 12345.67(two digits after decimal point)
 With ‘floating-point’ representation, the placement of the decimal
point can ‘float’ relative to the significant digits of the number.
E.g.1.234567,123456.7,0.00001234567, 1234567000000000
 The floating-point computation assures a much larger dynamic range -
the largest and smallest numbers that can be represented.
 Floating-point processing yields much greater precision(accuracy)
than fixed-point processing.
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Question
 The following declarations are appeared in a C program to be executed on floating
point and fixed-point processors.
char cIvalue= ‘a’; unsigned char ucMyvalue= 234;
int iTemp=0x1234; float fSample=0.0004
float fBalance=123.456 double ldTemp=1234.0000678
The floating-point processor is supported with single precision and double precision
accuracy. Similarly, the fixed-point processor is supported with precision of 2
decimal digits after point. Identify the format used to represent the declared
variables by the compiler to execute on fixed point and floating-point processors.

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 Endianness
• Endianness refers to the sequential order in which bytes are arranged into larger
numerical values when stored in memory.
-Wiki
• Little-endian Operation

• E.g. x86 Intel Processors

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 Endianness…
 Big-endian Operation

E.g. Motorola 68000

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 8086 Features
 16 bit micro processor (ALU is designed to work with 16 bit data).
 16 bit data bus.
 20 bit address bus, so it can access 220 or 1048576(1 MB) memory
locations of byte wide each. Therefore, a sixteen bit words are stored
in two consecutive memory locations (Von Neumann).
 Support memory segmentation
 The 8086 has time multiplexed address and data bus which reduces
number of pins required.

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 8086 Features…
 The 8086 requires clock with a 33% duty cycle.(no on chip oscillator,
requires clock generator 8284).
 clock speed: 5 MHz- 8086
8 MHz - 8086-2
10 MHz – 8086-1
 Two modes of operation:
Minimum Mode: CPU is connected to memory and I/O devices.
Maximum Mode: CPU is connected to another processor
(Multiprocessor Mode) in addition to memory and
I/O devices.
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 8086 Features …
 The 8086 can generate 16 bit I/O addresses.
 The 8086 provides fourteen 16 bit registers (SFR+ GPR)
 Micro-programmed control unit.
 16-Bit flag register (Control + Status)
 6 bytes instruction queue(Pipelining)
 Interrupts
- NMI & INTR (Hardware)
- INT instruction(Software)

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 8086 Internal Configuration

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 Architecture of 8086
 The 8086 CPU is divided into independent functional parts:
-Bus Interface Unit(BIU)
- Execution Unit(EU)
 BIU sends out addresses, fetches instructions from memory,
reads data from ports and memory and writes data to ports and
memory.

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 Architecture of 8086…

 The EU tells the BIU where to fetch instructions and data from, decodes
instructions and executes instructions.
 Dividing work between these two units, speeds up the execution.

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8086 Internal Diagram

Bus Interface Unit

(B I U)

Execution Unit (EU)

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Bus Interface Unit(BIU)
Instruction Queue
 While the EU is decoding an instruction or executing an instruction which
does not require use of the system buses, the BIU fetches up to six bytes
for the following instructions and stores in FIFO queue.
 The size of queue is 6 bytes.
 When EU is ready for next instruction execution, it simply reads
instruction byte(s) from the queue.
 Fetching next instruction while the current instruction executes is called
pipelining.

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 BIU-Instruction Queue…

 This speeds up program execution(Except for JMP and CALL instruction).

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 BIU…

Segment Registers
The BIU sends out the 20-bit address, so it can address any location of 1048576
bytes(1 MB).
Memory Segmentation
-At any time, 8086 works with only four segments of 64KB with in 1 MB.
-The 4 segment registers of 16 bits wide in the BIU are used to hold 16 bits
of the starting address of 4 segments.

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 BIU...
 Four segment registers:
-Code segment (CS) register for code segment:
Used for program storage(Instruction codes)
- Data Segment (DS) register for data segment:
Used for data storage
- Extra Segment (ES)register for extra segment:
Used for data storage
- Stack Segment (SS) register for stack segment:
Used to store address & data while subprogram executes

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 Memory Segmentation

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Generation of 20 bit address
 The index registers or pointer registers contain displacement or offset, used to
point to a particular location is called offset or effective address.
 Index registers/ Pointer registers
IP (Instruction Pointer) for Code segment
SI(source Index) for Data segment(default)
16
DI(Destination Index) for Data Segment (ES for string instruction)
bit
SP(Stack Pointer) for stack segment
BX register for DS(default), CS,ES,SS(Alternate)
BP(Base Pointer) for SS(default), CS,ES,DS(Alternate)

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 20 bit address…
 The address put on address bus called as physical address must contain 20 bits.
 The physical address is calculated as follows:

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Advantages of memory segmentation
1. Allow the memory capacity of 1 MB even though index
registers & pointer registers used to access memory are 16 bits
wide.
2. Allow the instruction or data of a program to be more than 64K
bytes long using more than one code and data segment.
3. Facilitate the use of separate memory areas for a program, its
data and the stack.

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 Questions
1. If CS=1000H, IP= 1234H what is effective address & physical address?
2. What is the operation of following instruction? MOV AL,[BP]
3. What is the operation of following instruction? MOV CX, [BX]
4. What is the operation of following instruction? MOV DS:[BP], AL
5. What is synchronous & Asynchronous interrupt?
6. If BX=0adech ,DS= 2000h and SI= 55h, find the effective address and physical
address of the instruction MOV AL,[BX][SI].
7. What is the IO capability of 8086 in IO mapped IO method?

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 Execution Unit(EU)
 The EU tells the BIU where to fetch instructions and data from, decodes
instructions & executes instructions.
 It contains,
- Control Circuitry
- Instruction decoder
- ALU
-Flags
- General Purpose registers
-Pointers & index registers

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 The STATUS register(Flag register)
 Indication/Status Bits
 only for status: Bits are set or cleared based on the result
of any Arithmetic or Logic operation.

 Control Bits
 Used for control: Bits may be affected indirectly (by the execution of an
instruction) or directly by an instruction designed to access the status word

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

x x x x OF DF IF TF SF ZF x AF x PF x CF

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 The STATUS register(Flag register)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

x x x x OF DF IF TF SF ZF x AF x PF x CF

 Carry flag(CF): This flag is set if there is carry out of MSB in

addition. It is set when borrow is needed in Subtraction.
 Parity flag(PF): It is set to 1 when result of byte operation or lower
byte of the word operation contain even number of ones.

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  Auxiliary Carry Flag(AF): This is set when there is an carry out from lower nibble
to higher nibble (D3 to D4).(used in BCD operations)
 Zero Flag(ZF): This flag is set if the result of ALU operation is zero.
 Sign Flag(SF): After ALU operation, if the MSB of the result is 1, sign bit is set.
 Overflow Flag(OF): If result is out of range.
This bit is set if there is a carry into MSB and no carry out of it or vice versa for
addition.
Subtraction: set to 1 when MSB needs borrow & no borrow from the MSB.

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 Question
 Give the contents of flag register after execution of following addition.
65D1H+2359H = 892A H
0110 0101 1101 0001
0010 0011 0101 1001
1000 1001 0010 1010

SF=1,ZF=0,PF=0, CF=0,AF=0,OF=1

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 Control Bits
 Trap Flag (TF): Trap flag is used for single stepping.
A system will stop after it executes each instruction and performs
trap interrupt.
 Interrupt Flag(IF): If set, maskable interrupts are enabled.
 Direction Flag(DF): It used to auto increment/decrement pointers
(DI & SI) made to point to string.
DF=0 =>Increment
DF=1=>Decrement

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 Questions
 Differentiate between control bits & status bits of flag register.
 What is the importance of overflow flag?
 What for segment registers are used?
 How 20 bit physical address is generated?
 Differentiate between maximum mode & minimum mode.
 What is the use .model small directive?
 Give an example for an instruction which supports memory to memory
operation.

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 8086 Pin diagram

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 8086 Pin Description

 The 8086 pins can be categorized into 3 groups:

 Pins having common functions in minimum and maximum modes.
 Pins having special functions in minimum mode.
 Pins having special functions in maximum mode.

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 Common Pins
 GND: Ground(2 pins)
 Vcc : Supply voltage of 5 V with ± 10%
 AD15-AD0 : Bidirectional in nature, during first part of the bus cycle, processor
outputs address and during later part of the bus cycle, processor reads (input) or
write (output) data.
 NMI: Non Maskable Interrupt request pin. It is positive edge triggered.
 INTR : Maskable interrupt request. If INTR pin is held active high when IF=1,
8086 enters into interrupt acknowledge cycle(INTA becomes active) after the
current instruction execution completion.

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 Common pins…
 CLK : Input Clock frequency
The 8284 clock generator is used to obtain the clock.
- The crystal is connected to 8284 chip, which divides crystal frequency by
three internally.
- Maximum CPU operation
8086 :5 MHz( Crystal frequency:15 MHz)
8086-2 :8 MHz(Crystal Frequency:24 MHz)
8086-1 : 10 MHz (Crystal Frequency: 30 MHz)
 RESET: Active high signal, when maintained for atleast 4 clock cycle, reset is
initiated.
- Reset clears PSW(Flag register), IP,DS, SS,ES and instruction queue.
- The CS register set to FFFFh.
- Processing begins at FFFF0H.
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 Common pins…

 Ready : The 8086 bus cycle consists of 4 clock cycles (T states).

- The ready pin is checked at the end of T2 of every bus cycle.

- If ready pin is low, it inserts wait state betweenT2 and T3.
- If the READY pin is still low after wait state, one more wait state is
inserted.
- The 8086 enters to T3 state only when READY pin high at the end of
wait state.
- Used to match the speed of slower peripherals.
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 Common pins…

Tw T3
 One wait state

 2 wait states Tw T3

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 Common pins…

 Test: A wait instruction causes CPU to idle (except for interrupt

processing) until low signal applied to this pin.
 RD : whenever this signal is low it indicates memory or I/O
read operation is to be performed.
 MN/MX :When tied to Vcc, 8086 is in minimum mode,
when grounded 8086 will be in maximum mode.

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 Common pins…
 BHE /S7: Byte High Enable, Active low signal
- Used to enable most significant data bus bits (D15- D8) during read or
write operation.
- Generated during first part of the machine cycle(bus cycle).

524KB 524KB

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  BHE & A0 pin together indicate various data transfer as indicated below.

Operation A0 Data Pins used

BHE
Write/Read a word 0 0 AD15-AD0
at Even Address
Write/Read a byte 1 0 AD7-AD0
at even address
Write/ Read a byte 0 1 AD15-AD0
at an odd address
Write/Read a word 0 1 AD15-AD0
at odd Address Read least
significant byte
1 0 AD7-AD0
Read Most
significant byte

86 S7 Carries no meaning, always high.

 MGRJ,ECE,RVCE
 Common pins…
 A19/S6-A16/S3 : During First part of the bus cycle(T1) the most significant 4 bits
of the address.
- Later part of the bus cycle status is output.
-S6 always zero, carries no meaning
- S5 gives the current setting of IF (interrupt Flag)
- S4 & S3 show which segment is accessed during the current bus cycle.

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 Minimum Mode pins
 INTA: Acknowledgement given by CPU to interrupt request.
 ALE(Address Latch Enable):This shows that the 8086 address/data bus contain
address information.
- The address can be memory address or I/O port address.
 DT/R: Data Transmit/Receive signal shows that microprocessor data bus
is transmitting(DT/R=1) or receiving(DT/R=0).
- This signal is used to control direction of data bus buffers.
- This is output signal issued by microprocessor.
 WR: Whenever this signal is low it indicates memory or I/O write operation
is to be performed.
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  DEN: The data bus enable is an output signal given by µP, during later part of the
cycle to inform the transceivers that CPU is ready to send or receive data.
 M/IO : This pin selects memory or I/O.
 HOLD, HLDA
➢when HOLD line goes High – it indicates the processor that another
master(DMA: Direct Memory access) is requesting the bus access.
➢In-turn the processor
➢issues acknowledge on HLDA pin, in the middle of the next clock cycle after
completing the current bus cycle.
➢Processor enters into hold state(releases bus/ not executing) until hold
release signal.
➢ Asynchronous input
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Maximum mode pins
 S2, S1, S0
 Indicates the type of operation carried out by the processor.
 Becomes active in the previous T4 and remains till T1,T2 of current cycle.
 Return to 'Passive State' during T3 – so that they may again become active for the next cycle
during T4.
 These output signals are used by 8288 bus controller to generate all memory & IO access
control signals
S2’ S1’ S0’ Indication
0 0 0 Interrupt Acknowledgement
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive (Inactive)
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  LOCK
 Prevents the other system bus master from gaining the system bus.
 Activated by the 'LOCK' prefix instruction and remains active until the completion
of the next instruction.
 QS1, QS0
 Queue status – informs the status of the code-pre fetch queue
QS1 QS0 Indication
0 0 No operation
0 1 1st byte of opcode from the queue
1 0 Empty queue
1 1 Subsequent byte of the opcode

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  RQ/GT0, RQ/GT1 (Request/grant)
➢Used by other local bus masters – to force the processor to release the
local bus at the end of the processor's current bus cycle.
➢RQ/GT0 has the highest priority than RQ/GT1
➢These lines are bidirectional and are used to both request and grant a
DMA operation.

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 Questions

 What is a bus cycle?

 What is a T-state?
 How to synchronize a slower peripheral with microprocessor?
 Why DMA is required?
 What is the use of LOCK prefix?
 What is the advantage of storing data at even address?

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