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    EE6104 Embedded Mid

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    prathima1704g7
    This 3 question, 30 point midterm exam covers embedded computing systems. The exam tests students on: 1) Deriving a single rate data flow graph with minimum edges and nodes from a multirate circuit. 2) Determining the critical path and iteration bound of a filter using the Minimum Cycle Mean method. 3) Finding the sampling frequency of a digital filter, pipelining it using feed forward cut-set method to increase the frequency to 1MHz assuming a 3MHz clock.

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    EE6104 Embedded Mid

    Uploaded by

    prathima1704g7
    4 views1 page
    This 3 question, 30 point midterm exam covers embedded computing systems. The exam tests students on: 1) Deriving a single rate data flow graph with minimum edges and nodes from a multirate circuit. 2) Determining the critical path and iteration bound of a filter using the Minimum Cycle Mean method. 3) Finding the sampling frequency of a digital filter, pipelining it using feed forward cut-set method to increase the frequency to 1MHz assuming a 3MHz clock.

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    This 3 question, 30 point midterm exam covers embedded computing systems. The exam tests students on: 1) Deriving a single rate data flow graph with minimum edges and nodes from a multirate circuit. 2) Determining the critical path and iteration bound of a filter using the Minimum Cycle Mean method. 3) Finding the sampling frequency of a digital filter, pipelining it using feed forward cut-set method to increase the frequency to 1MHz assuming a 3MHz clock.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    4 views1 page

    EE6104 Embedded Mid

    Uploaded by

    prathima1704g7
    This 3 question, 30 point midterm exam covers embedded computing systems. The exam tests students on: 1) Deriving a single rate data flow graph with minimum edges and nodes from a multirate circuit. 2) Determining the critical path and iteration bound of a filter using the Minimum Cycle Mean method. 3) Finding the sampling frequency of a digital filter, pipelining it using feed forward cut-set method to increase the frequency to 1MHz assuming a 3MHz clock.

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    © All Rights Reserved
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    of 1

    NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA

    Department of Electrical Engineering


    Mid-Semester Examination, 2022 - 2023 (Spring)
    M.Tech. Regular 2nd Semester

    Subject Name: Embedded Computing System


    Subject Code: EE6104

    Number of Pages: 1 Full Marks: 30 Duration: 2 Hours

    Figures at the right hand margin indicate marks.


    All symbols carry usual meaning. Assume standard value for any missing data.
    Answers should be brief and to the point.

    Q1. Derive the Single Rate Data Flow Graph (DFG) with minimum edge and nodes for the following DFG of a 10
    circuit operating at multirate.

    Q2. Determine the critical path and iteration bound of the following filter using Minimum Cycle Mean method. 10
    Assume the computation time for adder and multiplier as 2 u.t. and 4 u.t. respectively.

    Q3. Find the possible sampling frequency of the following digital filter. Pipeline the circuit using feed forward 10
    cut-set method to increase the sampling frequency to 1 MHz. Assume the clock frequency as 3MHz.

    END OF QUESTION PAPER. ALL THE BEST.

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