inst.eecs.berkeley.

edu/~cs61c
CS61C : Machine Structures
Lecture 7 – Introduction to RISC-V
Assembly language : lw, sw, decisions
Instructors
Dan Garcia and Bora Nikolic
2018-09-07
Fun video game
teaches assembly code!
The game “human resource
machine” takes players
through very simple
challenges through sorting
of zero-terminated strings!
My 9 & 12-year-old kids
loved it!
tomorrowcorporation.com/humanresourcemachine
 Review
• In RISC-V Assembly Language:
– Registers replace C variables
– One instruction (simple operation) per line
– Simpler is Better, Smaller is Faster
• In RV32, words are 32b
• Instructions:
– add, addi, sub
• Registers:
– 32 registers, referred to as x0 – x31
– Zero: x0
 Data Transfer:
Load from and Store to memory
Processor Memory Input
Enable?
Read/Write
Control
Program
Datapath Address Much larger place
PC
Write Data = Bytes To hold values, but
Registers Store to slower than registers!
memory
Arithmetic & Logic Unit Read Data = Data
(ALU) Output
Load from
memory
Fast but limited place
To hold values Processor-Memory Interface I/O-Memory Interfaces
3
 Memory Addresses are in Bytes
• Data typically smaller than 32 bits, but rarely smaller than 8 bits
(e.g., char type)–works fine if everything is a multiple of 8 bits
• 8 bit chunk is called a byte Least-significant byte in a word
(1 word = 4 bytes)
… … … … …
• Memory addresses are really 15 143 13 12
in bytes, not words 11 102 9 8
• Word addresses are 4 bytes apart 7 61 5 4
– Word address is same as address of 3 20 1 0
rightmost byte – least-significant byte 31 24 23 16 15 8 7 0
Least-significant byte
(i.e. Little-endian convention)
gets the smallest address
4
 en.wikipedia.org/wiki/Big_endian
Big Endian vs. Little Endian
Big-endian and little-endian derive from Jonathan Swift's Gulliver's Travels in which the Big Endians were
a political faction that broke their eggs at the large end ("the primitive way") and rebelled against the
Lilliputian King who required his subjects (the Little Endians) to break their eggs at the small end.
• The order in which BYTES are stored in memory
• Bits always stored as usual. (E.g., 0xC2=0b 1100 0010)
Consider the number 1025 as we normally write it:
BYTE3 BYTE2 BYTE1 BYTE0
00000000 00000000 00000100 00000001

Big Endian Little Endian

ADDR3 ADDR2 ADDR1 ADDR0 ADDR3 ADDR2 ADDR1 ADDR0
BYTE0 BYTE1 BYTE2 BYTE3 BYTE3 BYTE2 BYTE1 BYTE0
00000001 00000100 00000000 00000000 00000000 00000000 00000100 00000001

Examples
Names in China (e.g., Garcia Dan)
Java Packages: (e.g., org.mypackage.HelloWorld)
Dates done correctly ISO 8601 YYYY-MM-DD (e.g., 2018-09-07)
Eating Pizza crust first
Unix file structure (e.g., /usr/local/bin/python)
Examples
Names in the US (e.g., Dan Garcia)
Internet names (e.g., www.cs.berkeley.edu)
Dates written in England DD/MM/YYYY (e.g., 07/09/2018)
Eating Pizza skinny part first (the normal way)
Great Idea #3: Principle of Locality /
Memory Hierarchy
 Speed of Registers vs. Memory
• Given that
– Registers: 32 words (128 Bytes)
– Memory (DRAM): Billions of bytes (2 GB to 64 GB on laptop)
• and physics dictates…
– Smaller is faster
• How much faster are registers than DRAM??
– About 100-500 times faster! (in terms of latency of one access)

7
 Jim Gray’s Storage Latency Analogy:
How Far Away is the Data?
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 Load from Memory to Register
• C code
int A[100];
g = h + A[3];

Data flow

• Using Load Word (lw) in RISC-V:

lw x10,12(x15) # Reg x10 gets A[3]
add x11,x12,x10 # g = h + A[3]

Note: x15 – base register (pointer to A[0])

12 – offset in bytes
Offset must be a constant known at assembly time
9
 Store from Register to Memory
• C code
int A[100];
A[10] = h + A[3];

• Using Store Word (sw) in RISC-V:

lw x10,12(x15) # Temp reg x10 gets A[3]
add x10,x12,x10 # Temp reg x10 gets h + A[3]
sw x10,40(x15) # A[10] = h + A[3]

Data flow

Note: x15 – base register (pointer)

12,40 – offsets in bytes
x15+12 and x15+40 must be multiples of 4
10
 Loading and Storing Bytes
• In addition to word data transfers
(lw, sw), RISC-V has byte data transfers: n s i gn e d
o h a s “ u ro
– load byte: lb a l s c h ze
RISC-V s ( l b u ) w h i
no
– store byte: sb l o a d W hy
byte” f i l l re g i st e r.
• Same format as lw, sw te n d s to b u ?
ex o r e b y t e s
g n e d st
• E.g., lb x10,3(x11) unsi
– contents of memory location with address = sum of “3” + contents of
register x11 is copied to the low byte position of register x10.
xxxx xxxx xxxx xxxx xxxx xxxx xzzz zzzz
x10 byte
…is copied to “sign-extend”
: This bit
loaded
11
 Your turn. What’s in x12?
addi x11,x0,0x3F5 0x0
sw x11,0(x5) 0x3
lb x12,1(x5) 0x5
0xF
0xFFFFFFFF

12
 Computer Decision Making
• Based on computation, do something different
• In programming languages: if-statement

• RISC-V: if-statement instruction is

beq register1,register2,L1
means: go to statement labeled L1
if (value in register1) == (value in register2)
….otherwise, go to next statement
• beq stands for branch if equal
• Other instruction: bne for branch if not equal

13
 Types of Branches
• Branch – change of control flow

• Conditional Branch – change control flow depending on

outcome of comparison
– branch if equal (beq) or branch if not equal (bne)
– Also branch if less than (blt) and branch if greater than or equal
(bge)

• Unconditional Branch – always branch

– a RISC-V instruction for this: jump (j), as in j label

14
 Example if Statement
• Assuming translations below, compile if block
f → x10 g → x11 h → x12
i → x13 j → x14

if (i == j) bne x13,x14,Exit
f = g + h; add x10,x11,x12
Exit:
• May need to negate branch condition
15
 Example if-else Statement
• Assuming translations below, compile
f → x10 g → x11 h → x12
i → x13 j → x14
if (i == j) bne x13,x14,Else
f = g + h; add x10,x11,x12
else j Exit
f = g – h; Else: sub x10,x11,x12
Exit:
16
Magnitude Compares in RISC-
V
• Until now, we’ve only tested equalities (== and != in C);
General programs need to test < and > as well.
• RISC-V magnitude-compare branches:
“Branch on Less Than”
Syntax: blt reg1,reg2, label
Meaning: if (reg1 < reg2) // treat registers as signed integers
goto label;
• “Branch on Less Than Unsigned”
Syntax: bltu reg1,reg2, label
Meaning: if (reg1 < reg2) // treat registers as unsigned integers
goto label;

17
 C Loop Mapped to RISC-V Assembly
int A[20]; add x9, x8, x0 # x9=&A[0]
int sum = 0; add x10, x0, x0 # sum=0
for (int i=0; i < 20; i++) add x11, x0, x0 # i=0
sum += A[i]; addi x13,x0, 20 # x13=20
Loop:
bge x11,x13,Done
lw x12, 0(x9) # x12=A[i]
add x10,x10,x12 # sum+=
addi x9, x9,4 # &A[i+1]
addi x11,x11,1 # i++
j Loop
Done:
18
 Peer Instruction
We want to translate *x = *y into RISC-V 1
x, y ptrs stored in: x3 x5 2
3
1: add x3, x5, zero 4
2: add x5, x3, zero 5® 6
3: lw x3, 0(x5) 6® 5
4: lw x5, 0(x3)
5: lw x8, 0(x5) 7® 8
6: sw x8, 0(x3)
7: lw x5, 0(x8)
8: sw x3, 0(x8)

19
 “And in Conclusion…”
• Memory is byte-addressable, but lw and sw access one word at a time.
• A pointer (used by lw and sw) is just a memory address, we can add to it
or subtract from it (using offset).
• A Decision allows us to decide what to execute at run-time rather than
compile-time.
• C Decisions are made using conditional statements within if, while,
do while, for.
• RISC-V Decision making instructions are the conditional branches: beq
and bne.
• New Instructions:
lw, sw, lb, sb, lbu, beq, bne, blt, bltu, bge, j