ECE301 VLSI System Design

Digital System Design to Verilog Hardware

Description Language

FALL 2010

1
 Hardware Description Language

‰ Currently, almost all integrated circuits are designed with

using HDL

‰ Two widelyy used hardware description

p languages
g g
— VHDL
— Verilog

‰ HDL languages can describe circuits from two perspectives

— function
f ti
— structure

2
 A simple Verilog Example

‰ Verilog Code ‰ Circuit

// A simple example a
comment line c
b
module and2 (a, b ,c); module name
port list
input
p a,, b;;
port declarations
output c;

assign c = a & b; body

Many materials in this lecture
are taken from ALDEC Verilog
endmodule end module tutorial (www.aldec.com)

3
 Module definition

‰ Modules are the basic building blocks in Verilog. A module

d fi iti starts
definition t t with
ith the
th keyword
k d module
d l endsd with
ith the
th
keyword endmodule

‰ Elements in a module module name (port_list)

(port list)

port declarations
— Interface: consisting of port and parameter declarations
parameter declarations
`include directives
— optional add-ons
variable declarations
— body: specification of internal assignments
i t
part of the module low-level module instantiation
initial and always blocks
task and function

endmodule 4
 Port declaration

‰ Verilog Code ‰ Circuit

module MAT (enable, data, all_zero, result, status);
input enable; // scalar input
all_zero
input [3:0] data; // vector input enable
MAT result[2:0]
output all_zero; // scalar output
data[3:0] status[1:0]
output [3:0] result; // vector output
Inout [1:0] status // bi-directional port
…… LSB
MSB
endmodule

‰ To make code easy to read, use self-explanatory port names

‰ For the purpose of conciseness, use short port names
‰ In vector port declaration
declaration, MSB can be smaller index.
index
e.g. output [0:3] result (result[0] is the MSB)
5
 Available signal values

‰ Four signal values

—1 True
T
—0 False
—X Unknown
—Z High impedance

‰ Logic operations on four-value signals

Truth table
AND 1 0 X Z
a
b c 1 1 0 X X
0 0 0 0 0
X X 0 X X
Z X 0 X X
6
 Signal Classification

‰ Each signal in Verilog belongs to either a net or a register

‰ A net represents a physical wire. Its signal value is

determined by its driver. If it is not driven by any driver,
its value is high impedance (Z).
(Z)

‰ A register is like a variable in programming languages.

It keeps its value until a new value is assigned to it.
it

‰ Unlike registers, nets do not have storage capacity.

7
 Net declaration
‰ A net declaration starts with keyword wire
…… addr
wire r_w; // scalar signal

Proceessor

Mem
wire [7:0] data; // vector signal data

mory
wire [9:0] addr; // vector signal
r_w
……

— Selecting a single bit or a portion of vector signals

¾ data[2] single bit
¾ data [5:3] 3 bits

‰ Other keywords that can be used to declare nets are:

tri, wand, triand, wor, trior, supply0, supply1, tri0,
tri1, trireg
8
 Nets v.s. Ports

‰ Nets are internal signals that cannot be accessed by outside environment

‰ Ports are external signals to interface with outside environment

— input ports can be read but cannot be written

— output ports can be written but cannot be read
— inout ports can be read and written
pc
module pc (clk, rst, status, i_o);
i t clk,
input lk rst;
t clk
output [3:0] status; addr[9:0]
inout [7:0] i_o; rst

Proccessor

Meemory
wire r_w;
_ data[7:0]
[ ]
wire [7:0] data; status[3:0]
wire [9:0] addr; r_w
…… i_o[7:0]
endmodule

9
 Register declaration
‰ A register declaration starts with keyword reg
……
reg done; // scalar signal
reg [7:0] count; // vector signal
……
‰ Registers can be used to describe the behavior of sequential circuits

‰ Registers can also be used to implemented registered output ports

module pc (clk, rst, status, i_o);

input clk, rst;
output
t t [3:0]
[3 0] status;
t t
reg [3:0] status;
inout [7:0] i_o;
……

10
 Defining memory
‰ A memory component can be defined using reg variables
‰ Example:
……
reg [7:0] myMem [3:0]; // It defines a memory with 4 locations and each
// location contains an 8-bit data

Bit 7 6 5 4 3 2 1 0
myMem[0]
myMem[1]
myMem[2]

myMem[3]

11
 Using parameters
‰ The use of parameters make code easy to read and modify
‰ Example:
……
parameter bussize = 8;
reg [bussize-1 : 0] databus1;
reg [bussize-1 : 0] databus2;
……

12
 Predefined gate primitives
‰ Verilog offers predefined gate primitives
— Multiple-input
p p ggates: and,, nand,, or,, xor,, xor,, xnor
e.g. a
b d
and (d, a, b, c)
c

— Multiple-output gates: buf, not

e.g.
buf (a, b) b a

e.g.
a
not (a, b, c) c
b

13
 Predefined gate primitives
— tri-state gates: bufif1, bufif0, notif1, notif0

e.g. c
bufif1 (a, b, c) b a

c
e.g.
notif0 (a, b, c) a
b

— Verilog also offers two other gates (pull gates)

14
 Example of structural Verilog code
‰ Example of using predefined gate primitives

(from ALDEC tutorial)

15
 User defined primitives
‰ Verilog allows users to defined their own primitive
components, referred to as User defined primitives (UDPs)

— A UDP is always defined by truth table

— It can have multiple inputs but only one output
— None of its inputs and output can be a vector
— UDPs for combinational and sequential circuits are represented
and instantiated differently
— ? represents any value of 1, 0, X
— b represents any value of 1 or 0
—Value Z is not allowed in UDPs

16
 Combinational UDPs
‰ Example: 2-to-1 multiplexer

(from ALDEC tutorial)

— Combinational UDPs don’t need initialization

— The first signal in the port list is always output. However, in the truth table
the output signal value is at the end (after a colon).
— Input order in the truth table must follow the order given in the port list.
— Output for unspecified combination is always X.
17
 Sequential UDPs
‰ Example: D-Latch

(from ALDEC tutorial)

— Output Q is initialized by initial block.

— In the truth table Q is the current state, Q* is the next state.
— Symbol – indicates the next state is the same as the current state.
state

18
 Sequential UDPs
‰ Example: D Flip-Flop

(from ALDEC tutorial)

— r for rising edge, same as (01)

— f for falling edge, same as (10)
— p for positive edge, same as (01), (0X), (X1)
— n for negative edge, same as (10), (1X), (X0)
— * for any change, same as (??)
19
 Using UDPs
‰ Example: 4-bit synchronous counter

‰ Defining UDPs

— Cannot be defined
within modules.
modules
— Can be defined after
or before the module in
the same file.
— Can be defined
in a separate file
and use include
directive to include
to the code.

(from ALDEC tutorial)

20
 Module instantiation

‰ Module instantiation leads to hierarchy design

‰ Port connecting rules

input net or reg

inout net

output net

(from ALDEC tutorial)

21
 Module instantiation

‰ Signal assignment following port list order

(from ALDEC tutorial)

22
 Module instantiation
‰ Signal assignment by port names

(from ALDEC tutorial)

— The two methods cannot be mixed!

23
 Module instantiation
‰ Unconnected ports

by port list order

by name

(from ALDEC tutorial) 24

 Functional Verilog code

‰ So far, you learned how to write structural Verilog code

Self evaluation:
Can you translate any schematic into Verilog code?

‰ Sometimes, it is more convenient to use functional

Verilog code. This is what are going to be discussed next.

25
 Integer constants
‰ Un-sized integer example
— 12 // decimal number 12
— `h12 // hex number 12 (18 decimal number)
—`o12 // octal number 12 (10 decimal number)
—`b1001
b1001 // binary number 1001 (9 decimal number)

‰ Sized integer example

—88`d12
d12 // decimal number 12 taking 8 bits
— 8`h12 // hex number 12 taking 8 bits
—8`b10010011 //
—8`b1
8 b1 // binary number 00000001
Note Verilog uses left padding

26
 Integer constants
‰ Negative numbers
— Negative
N i numbers
b are represented
d iin 2’s
2’ complement
l form
f
— - 8`d12 // stored as 11110100

‰ Use of ?, X, Z, _ characters
— 8`h1? // 0001ZZZZ
— 2`b1? // 1Z
— 4`b10XX // 10XX
— 4`b100Z // 100Z
— 8`b1010_0011 // 10100011

27
 Arithmetic operators
‰ Available operators: +, -, *, /, % (modulo)

‰ Arithmetic operators treat register operands as unsigned values

— Example:

integer A; reg [7:0] A;

A = -12; A = -12;
A/4 -3 A/4 61

28
 Relation and equality operators
‰ Available relational operators: <, <=, >, >=
— If any bit off an operandd is
i X or Z,
Z the
th result
lt will
ill be
b X

‰ Available equality operators: ===, !==, ==, !=

— ===, !== : case equality (inequality). X and Z values are considered
in comparison
— ==, != : logic equality (inequality). If any bit of an operand is
X or Z
Z, the
th result
lt will
ill be
b X

Example
Left Op.
Op Right Op.
Op === !== == !=
0110 0110 1 0 1 0
0110 0XX0 0 1 X X
0XX0 0XX0 1 0 X X

29
 Logic operators
‰ Logic operators:
— && (logic and), || (logic or), ! (logic not)
Operand A Operand B A&B A|B !A !B
1010 00 0 1 0 1
1010 011 1 1 0 0

‰ Bit-wise logic operators:

— & (and), | (or), ~ (not), ^ (xor), ~^ (xnor)
Operand A Operand B A&B A|B ~A A^B A~^B
1010 0011 0010 1011 0101 1001 0110

‰ Reducation
R d ti operators:
t
— & (and), ~& (nand), | (or), ~| (nor), ^ (xor), ~^ (xnor)
Operand A &A ~&A |A ~|A ^A ~^A
1010 0 1 1 0 0 1
30
 Shifter operators
‰ << : shift left
reg [3:0]
[3 0] A
A;
1 1 0 1 A << 2 0 1 0 0

— zeros are moved in from the right end

‰ >> : shift right

g

reg [3:0] A;
1 1 0 1 A >> 2 0 0 1 1

31
 Concatenation operators
‰ Example
reg [7:0] A, B, Data;
reg c;
……
A = 10101101
10101101; BB= 00110011
00110011;
c = 0;
Data = {A[3:0], B[7:6], c, c}; // Data = 11010000

Data 1 1 0 1 0 0 0 0

c c
A[3:0] B[7:6]

32
 Continuous assignment
‰ Continuous assignment starts with keyword assign.

‰ The left hand side of a continuous assignment command must be

a net-type signal.
‰ Example
p
a x
b AND

OR o
c

module cir1 (o, a, b, c); module cir1 (o, a, b, c);

output o; output o;
input a, b, c; input a, b, c;
wire x; OR wire x = a & b;
assign x = a & b; assign o = x | c;
assign o = x | c; endmodule
endmodule 33
 Conditional assignment
‰ A conditional assignment has three signals at the right hand side.
— The first signal
g is the control signalg
— If the control signal is true, the second signal is assigned to
the left hand side (LHS) signal ; otherwise, the third signal
is assigned to LHS signal.

(from ALDEC tutorial)

34
 Adding
g delay
y to continuous assignment
g
‰ Delay is added by # t after keyword assign, t is the number
of delayed
y time unit.
‰Time unit is defined by `timescale
‰ Example
E l
`timescale 10ns/1ns // <ref_time_unit>/<time_precision>
module buf1 (o,
(o i);
output o;
input i;

assign
i #3 o = 1;
1 // delay
d l for
f 3 time
i unit
i

endmodule

35
 Behavioral blocks
‰ In additional to assignment, other functional description codes are
included in two-type behavioral blocks:
initial blocks and always blocks
‰ A module can have multiple blocks, but blocks cannot be nested.
‰ When a block has multiple statements, they must be grouped using
begin and end (for sequential statements) or fork and join (for
concurrent statements)
statements).

‰ An initial block is executed at the beginning of simulation. It is

executed only once.
‰ Always blocks are repeated executed until simulation is stoped.

36
 Procedural assignment
‰ Procedural assignment is used to assign value to variables.

‰ A variable can be a signal defined by reg or a name defined by integer

(another form of register-type signal). A variable cannot be a net type signal.

‰ Variable assignments must be in behavioral blocks.

‰ Difference between continuous assignment and procedural assignment

— In continuous assignment changes the value of the target net whenever
the right-hand-side operands change value.
— Procedural assignment changes the target register only when the assignment
is executed according to the sequence of operations

37
 Procedural assignment examples

‰ Signal initialization ‰ generating clock

Note how to specify delay

(from ALDEC tutorial)
in procedural assignment

38
 Delay in procedural assignments
‰ Delay specified in front of procedural assignment statements
((e.g.
g #3 a = b&c;)
;) delayy the execution of the entire statement.

Module delayTest;
integer a, b, c;
initial begin
a = 2; b = 3; Change a from 2 to 4
end after 3 time unit
initial #3 a = 4;
initial #5 c = a+b; Execution order:
endmodule 1. delayy
2. evaluation
3. assignment

Result: cc=77

39
 Delay in procedural assignments
‰ Delay specified right after = in procedural assignment statements
(e.g. a = #3 b&c;) just delay the assignment operation. The evaluation
off the
h right
i h hand
h d side
id expression
i isi executedd without
ih delay.
d l

Module delayTest;
integer a,
a b,
b c;
initial begin
a = 2; b = 3; Change a from 2 to 4
end after 3 time unit
initial #3 a = 4;
initial c = #5 a+b; Execution order:
endmodule 1 evaluation
1. l ti
2. delay
3. assignment

Result: c=5
40
 Blocking assignments v.s. Non-blocking assignments
‰ Blocking assignments use = as assignment symbol (previously discussed
procedural assignments). Assignments are performed sequentially.
initial begin
a = #1 1; // assignment at time 1
b = #3 0; // assignment at time 4 (3+1)
c = #6 1; // assignment at time 10 (6+3+1)
end

‰ Non-blocking
Non blocking assignments use <= as assignment symbol
symbol. Non
Non-blocking
blocking
assignments are performed concurrently.
initial begin
#1 a < = 1;1 // assignment
i t att time
ti 1
#3 b <= 0; // assignment at time 3
#6 c <= 1; // assignment at time 6
end

41
 Parallel blocks
‰ Parallel block is a more flexible method to write concurrent statements.
It uses fork and join, instead of begin and end, in block description.

Sequential block with Sequential block with

blocking assignments Non-blocking assignments

Parallel
ll l block
bl k

(from ALDEC tutorial)

42
 Event control statements
‰ An event occurs when a net or register changes it value. The event can be
further specified
p as a rising
g edge
g ((by
ypposedge)
g ) or fallingg edge
g (by
( y negedge)
g g )
of a signal.
‰ An event control statement always starts with symbol @

@ (clk) Q = D; // assignment will be performed whenever

signal clk changes to its value

@ (posedge
( d clk)
lk) Q = D;
D // assignment will be performed whenever
signal clk has a rising edge (0Æ1, 0ÆX,
0ÆZ, XÆ1, ZÆ1)

@ (negedge clk) Q = D; // assignment will be performed whenever

signal clk has a falling edge (1Æ0, 1ÆX,
1ÆZ, XÆ0, ZÆ0)

43
 Sensitivity list
‰ Sensitivity list specifies events on which signals activating always blocks

(from ALDEC tutorial)

44
 Wait statements
‰ Wait statements allow designers to more specifically control when to
execute statements.
‰ A wait statement starts with keyword wait followed by:
— A logic condition that determines when to execute the statements.
The condition is specified in brackets.
brackets
— Statements that will be executed
module testWait;
g a, b, c;
integer
reg en;
initial a = 0;
initial #3 a = 3;
intial #6 a = 7;
wait (a==7) b = 1; // assign 1 to b when a=7
wait (en) c = 2; // assign 2 to c when en is true (en is like enable signal)
endmodule
45
 Conditional statements
‰ Conditional statement is another method to control when statements are
executed
If (condition) true_statements;
else false_statements;

46
(from ALDEC tutorial)
 Multiple choice statements
‰ Multiple choice statement starts with keyword case. It offers a more
readable alternative to nested if-else statements.

(from ALDEC tutorial) 47

 Loop statements
‰ Loop statements include forever, repeat, while, and for

(from ALDEC tutorial)

48
 A simple combinational circuit example
‰ A 2-to-4 decoder

(from ALDEC tutorial)

Circuit schematic

Data flow code

Structural code
49
 A simple combinational circuit example
‰ A 2-to-4 decoder behavioral Verilog code

(from ALDEC tutorial)

50
 An FSM example
read_1_zero
‰ Moor-type machine 0
0 1 read_2_zero 0
0
1
start_state 0 1 0
1 0

1
0 1 read_2_one 1
read_1_one
module moore_explicit
moore explicit (clock,
(clock reset,
reset in_bit,
in bit out_bit);
out bit);
input clock, reset, in_bit;
output out_bit;
reg [2:0] state_reg, next_state;

parameter start_state = 3'b000;

parameter read_1_zero = 3'b001;
parameter read 1 one = 33'b010;
read_1_one b010;
parameter read_2_zero = 3'b011;
parameter read_2_one = 3'b100; 51
 An FSM example
always @ (posedge clock or posedge reset)
if ((reset == 1)) state_regg <= start_state;; else state_regg <= next_state;;

always @ (state_reg or in_bit)

case (state_reg)
start state:
start_state:
if (in_bit == 0) next_state <= read_1_zero; else
if (in_bit == 1) next_state <= read_1_one;

read_1_zero:
if (in_bit == 0) next_state <= read_2_zero; else
if (in_bit == 1) next_state <= read_1_one;

read_2_zero:
if (in_bit == 0) next_state <= read_2_zero; else
if (in_bit == 1) next_state <= read_1_one;

52
 An FSM example

read_1_one:
if (in_bit == 0) next_state <= read_1_zero; else
if (in_bit == 1) next_state <= read_2_one;

read_2_one:
read 2 one:
if (in_bit == 0) next_state <= read_1_zero; else
if (in_bit == 1) next_state <= read_2_one;

default: next_state <= start_state;

endcase

assign out
out_bit
bit =((state
((state_reg
reg == read_2_zero)
read 2 zero) || (state
(state_reg
reg ==read
read_2_one))
2 one)) ? 1 : 0;
endmodule

53
 Synthesizing registers
‰ Assignment inside a clocked always block will be synthesized as DFFs.

(from ALDEC tutorial)

54
 Avoiding unwanted latches
‰ Incomplete system specifications (if-else, or case) lead to unwanted latches

— Latch-prone
L t h code
d — Latch-free code

(from ALDEC tutorial)

55
 Other synthesis tips
‰ Nested if-else leads to lengthy mux-chain, which is normally slow. Using
case instead. However,, case results in mux with multiple
p inputs,
p , which
makes routing more difficult.

‰ Using instantiated module to implement arithmetic operators, instead

of directl
directly using
sing arithmetic operators.
operators

‰ Good partition leads to better results.

‰ Assign values to all outputs in all cases (to avoid unwanted latches).

56
 Verilog subroutines

‰ Subroutines lead to more readable code and make code-reuse easy .

‰ Types of subroutines are: task and function.

‰ Subroutines can be used only in behavioral blocks and contain behavioral

statements.
t t t

‰ Subroutines are declared with modules.

‰ Verilog
V il offers
ff a large
l set off system built-in
b il i tasks
k andd functions.
f i

57
 Task example
‰ Task declaration
task name
argument declaration

local variable

task body

(from ALDEC tutorial)

‰ Task
T k invocation
i i
reg [31:0] result;
reg [3:0] data;
……
factorial (result, data);
58
 Function example
‰ Function declaration

function name
input declaration
local variable

assign return value

(from ALDEC tutorial)

‰ Function call

reg [31:0]
[31 0] result;
lt
reg [3:0] data;
……
result = Factorial (data);

59
 Creating testbench
‰ Testbench is used to verify the designed circuit.

(from ALDEC tutorial)

60
 Testbench example

‰ Testbench ‰ Unit under test

‰ Simulation result

(from ALDEC tutorial)

61