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Unit I: FET and MOSFET

JFET: Basic operation, Drain and Transfer Characteristics (Shockley’s Equation).
Configurations, biasing arrangements for JFET.
MOSFET: Basic operation, Drain and Transfer Characteristics. Non ideal voltage-current
characteristics viz. Finite output resistance, body effect, sub threshold conduction, breakdown
effects and temperature effects. MOSFET biasing. N-MOS, P-MOS and CMOS devices.
Handling precautions for CMOS devices, Comparison of BJT, FET and MOSFET.

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JFET (Junction Field Effect Transistor)

1. Introduction:
 Transistor was invented by W.H. Brattain, John Bardeen and William Shockley in 1947.
 The word transistor was derived from transfer resistor, as they transfer signals from low
resistance to high resistance
 It is a three-layer semiconductor device in which an n-type semiconductor is sandwiched
between two p-type layers or a p-type semiconductor is sandwiched between two n-type
layers
 It is extensively used in amplifiers, digital switches and oscillator circuits
 In the previous course, we have studied BJTs and now in this course, we will study the
second major type of transistor i.e. FETs – Field Effect Transistor.
 There are two general categories of FETs - Junction Field Effect Transistor (JFET) and
Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
 The detail tree structure of transistor family is as in Figure 1. It consist a FET and their
classifications.
 Figure1: The transistor family tree

2. JFET Construction and working:

 FETs are voltage operated devices. There are major two categories of FETs- Junction
FETs and Insulation gate FETs or MOSFET (Metal Oxide Semiconductor FET)
 Junction field effect transistor popularly is known as J field effect where JFET is the
abbreviated form of Junction field effect transistor
 There are two types: 1. n- channel JFET 2. p- channel JFET
 Figure 2 shows the structure of n-channel junction field effect transistor. It consists of an
N-type substrate (bar or channel) of moderately doped in which two heavily doped P-
regions are diffused.
 One end of the N type substrate is called as source and other end is called as drain.
 The two heavily doped P-regions are connected to a third terminal called as gate.
 Whereas in the construction of P channel JFET, p-type material is forming channel
between 2 n-type materials.
 Figure 2: Structure of n-JFET
 By applying a reverse bias voltage to a gate terminal, the channel is pinched off, so that
the electric current is switched off completely. A JFET is usually on when there is no
potential difference between its gate and source terminals
 If a potential difference of the proper polarity is applied between its gate and source
terminals, the JFET will become more resistive to current flow, which means that less
current will flow in the channel between the source and drain terminals.
 The working of n- channel JFET can be divided different parts as shown in Figure 3.
1. VGS = 0 V and VDS > 0 V
2. VGS < 0 V and VDS > 0 V
3. Large negative VGS is applied
4. VGS = 0 V and 0< VDS< |Vp|
 Figure 3: Working Principle of n-JFET
1. VGS = 0 V and VDS > 0 V
• The potential of the gate terminal is same as the potential of the source terminal, thus the
potential difference between gate and source is equal to zero volts. So we have connected
the gate terminal with the source terminal as shown in figure 4.
• VGS is equal to zero volts thus, we will connect the ground to the source the potential of
ground is equal to zero volts.
• VDS is greater than zero it is positive and let's say VDS is equal to some positive voltage
VDD.
• Thus a voltage source is connected between the drain and source whose magnitude is
equal to VDD.
• The positive of VDD is connected to the drain and the source is connected to the negative
terminal.
• Thus, when the gate terminal is not connected and a potential is applied between the drain
and source terminals, free electronics moves from source to drain and conventional
current flows from drain to source known as I D.
• The drain current at this point where, VGS = 0 V, is referred as drain to source saturation
current (IDSS)
• IDSS corresponds to the maximum drain current as the channel width is maximum.
 Figure 4: VGS = 0 V and VDS > 0 V

2. VGS < 0 V and VDS > 0 V

 When the gate terminal is biased negative w.r.to source and the drain is operated at a
positive potential with respect to the source, there exist space charge region (depletion
region) on either side of junction as shown in figure 5.
 The width of depletion region is increased and effective width of channel is decreases.
Hence, amount free electronics moves from source to drain decreases and ID reduces.
 When the negative bias voltage is further increased, the depletion regions meets to each
other at the centre and ID is cut off completely
 The value of VGS that makes the drain current ID ≈ equal to 0 is called as cut off voltage
VGS(off)

Figure 5: VGS < 0 V and VDS > 0 V

3. Large negative VGS is applied

 As the negative potential voltage VGS is increased as shown in figure 6, the depletion
regions are widened, the channel resistance is increased and the drain current is reduced.
 At a certain value of VGS the depletion regions seem to touch each other, at this point, the
channel width is zero and the drain current is 0 Amp. This gate to source voltage at which
the drain current is 0 is called as VGS (cut- off).
 Thus for a fixed drain to source voltage, it becomes possible to control the drain current
by varying the reverse bias voltage across the gate junction.

Figure 6: Large negative VGS is applied

4. VGS = 0 V and 0<VDS<|Vp|

 When VGS = 0 and VDS is increased, ID increases. Therefore, ID is proportional to VDS (for
small values of VDS).
 With further small increase in VDS, the drain current increase is nearly linear and the
channel behaves as a resistance of almost constant value.
 For larger value of VDS, as VDS increases, the depletion layer become wider, causing
increase in the resistance of channel and smaller increase in I D.
 Because of the rapid increase in channel resistance at this stage, a saturation level of I D is
reached, where further increase in VDS, produces only a slight increase in ID (almost
constant ID) as shown in figure 7.
 Figure 7: Characteristics of n-JFET when VGS = 0 V

 When drain current saturation level is reached, the shape of the depletion regions is such
that they appear to pinch off the channel
 The drain to source voltage at which ID levels off is called pinch-off voltage (Vp)
 The region in the characteristics where I D is fairly constant is referred as pinch off region
 The value of VDS beyond which the drain current becomes constant is called as pinch off
voltage VP
 The region of characteristic between VDS = 0 V and VDS = VP is termed as the channel
ohmic region as the channel here is behaving as a resistance.
 With continue increase in VDS, voltage will be reached at which, the gate channel
junction breaks downs.
 At this point the drain current increases very rapidly and the device may be destroyed
producing an avalanche effect

3. JFET characteristics:
The JFET characteristics are described in two modes as drain characteristics and transfer
characteristics.
3.1 Drain Characteristics:
 Drain characteristics is a plot of drain to source voltage V DS versus drain current ID and,
at different constant values of gate to source voltage VGS.
 It is observed that as the negative gate bias voltage is increased; the maximum saturation
drain current becomes smaller because the conducting channel now becomes narrower.
 Pinch-off voltage is reached at a lower value of drain current ID as compared with
VGS = 0

Figure 8: Drain Characteristics of n-channel JFET

 Thus the maximum value of VDS can be applied to a JFET is the lowest voltage which
causes avalanche breakdown. It is also observed in the figure 8 that with VGS = 0, ID
saturates at IDSS and the characteristic shows VP = 4 V
 Hence for working of JFET in the pinch-off or saturation region, it is necessary that the
following conditions must be fulfilled:
VP < VDS < VDS (max)
VGS (OFF) < VGS < 0
 Mainly the JFET operates three regions such as ohmic, saturation, cut-off. It can operate
in break-down regions for in extreme increase in V DS.
  Ohmic Region: If VGS = 0 then the depletion region of the channel is very small. The
drain current ID varies with variation in drain to source voltage VDS. In this region
the JFET acts as a voltage controlled resistor or Variable Voltage Resistance
(VVR). This region is valid for VGS is less than magnitude of Vp.
 Saturation Region: In this region ID remains constant as VDS increases. JFET acts as
an amplifier in this region for V GS is not equal to zero (some - ve value). In this
region JFET can work as close switch at VGS = 0V.
 Pinched-off (cut-off) Region: This is also called as cut-off region. The JFET enters
into this region when the gate voltage is large negative, then the channel closes i.e.no
current flows through the channel. In this region the JFET acts as an open circuit
switch.
 Breakdown Region: If the drain to source voltage (VDS) is high enough, then the
channel of the JFET breaks down and in this region uncontrolled maximum current
passes through the device.

3.2 Transfer Characteristics:

 Transfer characteristics is a plot of output current I D versus the input controlling quantity
VGS for constant value of VDS. The figure 9 shows the transfer and drain characterises of
JFET.
 The transfer characteristics represents the how effectively the input voltage is transferred
as output voltage.
 For the BJT transistor the output current I C and input controlling current IB were related
by beta, which was considered constant for the analysis to be performed.
 Figure 9: Drain Characteristics ofnJFET

 In equation form, shows a linear relationship exists between IC and IB

(1)
 This linear relationship does not exist between the output and input quantities of a JFET.
The relationship between ID and VGS is defined by Shockley’s equation.

(2)

where,
IDSS = maximum drain to source saturation current
VP = Pinch off voltage
3.3 JFET Parameters:
During purchasing a JFET for a particular application we need to check the specifications of the
device. Important Parameters of JFET are as follows:
a. Transconductance (gm)
b. Dynamic Output Resistance(AC) (rd)
c. Amplification Factor (μ)
d. Input resistance

a. Transconductance (gm):
 Transconductance is the ratio of change in drain current (δI D) to change in the
gate to source voltage (δVGS) at a constant drain to source voltage
(VDS = Constant).

Figure 10: Transfer Characteristics of n-JFET

The transconductance factor is obtained from the slope of the characteristics as shown in
figure 10.

An equation for gm can be derived as follows:

 where,
gmo is the value of gm at VGS = 0 V.
Further gm is written as:

b. Dynamic (AC) Output Resistance (rd):

 It is defines as the ratio of change in the drain to source voltage to the corresponding
change in drain current, at a constant value of gate to source voltage. Figure 11 elaborates
more detail to calculate the rd.

where,
yos is the output admittance, with the units of μS
 Figure 11: To calculate rd from characteristics of n-JFET

 As, the slope of the characteristics is very small, the value of rd is large. It is usually in
the range of 50KΩ to few hundred KΩ .

c. Amplification Factor (μ):

 The amplification factor is defined as the ratio of change of drain voltage (δV DS) to
change of gate voltage (δVGS) at a constant drain current (ID = Constant).

 There is a relation between transconductance (gm) and dynamic output resistance (rd)
and that can be expressed as follows:

d. Input resistance
JFET operates with reverse biased gate to source junction. Thus, the input resistance
measured at gate with respect to source is very high.
 𝑉𝐺𝑆
𝑅𝑖𝑛 =
𝐼𝐺

4. JFET Configuration: JFET has three terminals like Gate, Source and Drain. For any
system to work requires two ports as input and output. Each port has two terminals or wires
as signal and ground. Hence, total four terminals are required to work as system. However,
FET has three terminals and to work as system one terminal has to common between input
and out. Thus JFET can be configured as Common source (CS), Common Drain (CD) and
Common Gate (CG).

5. Biasing arrangements for JFET:

Biasing is a process of applying external D.C. source to the device that operates device as
per requirements of user. There are three types of biasing circuits.
There are three types of biasing:
1.Fixed bias
2.Self bias
3.Voltage-divider bias
5.1 Fixed bias: The simplest biasing arrangements for the n-channel JFET is fixed-bias as shown
in figure 12. The VDD is connected to the gate of the JFET and VDS is connected to drain to
source. The current limiting resistor RD is connected between the VDD and drain terminal.
 Figure 12: Fixed Bias
 Applying Kirchhoff’s voltage law in the clockwise direction of the indicated loop gives,

 Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the
notation fixed-biased circuit.
 The resulting level of drain current ID is now controlled by Shockley’s equation:

 Since VGS is a fixed quantity for this configuration, its magnitude and sign can simply be
substituted into Shockley’s equation and the resulting level of ID calculated which is also
depends on VGS = -VGG.
 Further, VDS is calculated as: 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 ∗ 𝑅𝐷

5.2 Self bias: The self-bias configuration eliminates the need for two dc supplies. However,
single power supply as VDD is connected for the biasing. The controlling gate-to-source
voltage is now determined by the voltage across a resistor RS introduced in the source leg of
the configuration as shown in figure 13.
 Figure 13: Self bias configuration
 For the dc analysis, the capacitors can again be replaced by open circuits and the resistor
RG replaced by a short-circuit equivalent since IG = 0 A. The DC biasing circuit for the
self bias arrangement is shown in figure 14.

Figure 14: Redrawn for DC analysis

 The current through RS is the source current IS, but IS = ID and

 For the indicated closed loop

 From Shockley’s equation

  For output circuit

5.3 Voltage-divider bias: Voltage-divider biasing circuit divides the voltage at point gate
terminal due to the R1 and R2 resistors. The Figure 15 shows the voltage divider biasing
arrangement for JFET. It is the basically the voltage divider bias circuit for amplifier. The
Capacitor C1, C2 and Cs are acting as open circuit of DC analysis.

Figure 15: Voltage-divider bias configuration

 For the dc analysis, note that all the capacitors, including the bypass capacitor CS,
have been replaced by an open-circuit equivalent as shown in figure 16.
 Figure 16: Redrawn for DC analysis
 Since IG = 0 A, Kirchhoff’s current law requires that IR1 = IR2. The voltage VG,
equal to the voltage across R2, can be found using the voltage divider rule as follows:

 Applying Kirchhoff’s voltage law in the clockwise direction to the indicated loop,
gives

 Substituting VRS = IS*RS = ID*RS, we have

 For the resulting value of ID: