ES 204 Digital Systems

LAB 1

Naga Sheshu Reddy [22110178]

Srivathsa Vamsi Chaturvedula [22110260]

1 bit Full Subtractor

Structural Code

`timescale 1ns / 1ps

module sub1full(
input a,
input b,
input borin,
output borout,
output diff
);

and a1(g, ~a, ~b, borin);

and a2(f, a, ~b, ~borin);
and a3(h, a, b, borin);
and a4(l, ~a, b, ~borin);
or a5(diff, g, h, f, l);

and b1 (hh, ~a, borin);

and b2 (gg, ~a, b);
and b3 (ff, b, borin);
or b4(borout, hh, gg, ff);

endmodule

Test Bench Code

`timescale 1ns / 1ps

module sub1fullTB();

reg a, b, borin;
wire diff, borout;

sub1full uut(a, b, borin,borout, diff);

initial begin

a = 0; b = 0; borin = 0;
#10;
a = 0; b = 0; borin = 1;
#10;
a = 0; b = 1; borin = 0;
#10;
a = 0; b = 1; borin = 1;
#10;
a = 1; b = 0; borin = 0;
#10;
a = 1; b = 0; borin = 1;
#10;
a = 1; b = 1; borin = 0;
#10;
a = 1; b = 1; borin = 1;
#10;
end
endmodule

Simulation Output
4 bit Full Subtractor

Structural Code

module sub4bit(
input [3:0] a,
input [3:0] b,
output borout,
output [3:0] diff
);

wire [3:0] borout_int;

wire [3:0] diff_int;

sub1full s1(a[0], b[0], 0, borout_int[0], diff_int[0]);

sub1full s2(a[1], b[1], borout_int[0], borout_int[1], diff_int[1]);
sub1full s3(a[2], b[2], borout_int[1], borout_int[2], diff_int[2]);
sub1full s4(a[3], b[3], borout_int[2], borout_int[3], diff_int[3]);

assign borout = borout_int[3];

assign diff = diff_int;

endmodule

Test Bench Code

module sub4bitTB;

reg [3:0] a, b;
wire borout;
wire [3:0] diff;

sub4bit uut (.a(a), .b(b), .borout(borout), .diff(diff));

initial begin

// Test case: 7-3 = 4

a = 4'b0111; b = 4'b0011;
#10;

// Test case: 3-4 = -1

a = 4'b0011; b = 4'b0100;
#10;

// Test case: 2-7 = -5

a = 4'b0010; b = 4'b0111;
#10;

// Test case: 5-0 = 5

a = 4'b0101; b = 4'b0000;
#10;

end
endmodule
Simulation Output