2010 Conference on Precision Electromagnetic Measurements
June 13-18, 2010, Daejeon Convention Center, Daejeon, Korea
DEVELOPMENT OF A PRECISION RESISTIVE VOLTAGE DIVIDER FOR FREQUENCIES
UP TO 100 kHz
T. Hagen and I. Budovsky
National Measurement Institute Australia
Bradfield Rd, Lindfield, NSW 2070, Australia
Abstract
A range of precision resistive voltage dividers for use
in high frequency power standards is currently under
development at the National Measurement Institute,
Australia (NMIA). The paper describes the design of
the resistive voltage divider (RVD) and the methods
of its evaluation. The target uncertainty in the voltage
ratio is 100 PV/V at 100 kHz for both amplitude and
phase at voltages up to 240 V.
Introduction
Most national metrology institutes around the world
establish their own standards of electrical power.
These standards usually contain a voltage divider to
reduce the voltage to values below 10 V, a shunt to
convert current into voltage and a reference
instrument measuring the product of the two voltages.
At power frequencies the use of an inductive voltage
divider (IVD) reduces both amplitude and phase
errors introduced by the voltage conversion to less
than 10-7 [1]. However, the design of high-accuracy
IVDs for audio and higher frequencies is difficult.
This paper focuses on the design of a RVD for
voltages up to 240 V that produces a 1 V output
voltage with minimal amplitude and phase errors at
frequencies up to 100 kHz.
RVD Design
The upper arm of the RVD contains a series chain of
26 high precision resistors. The resistors are arranged
in groups of two. Each group is soldered to the
printed circuit board (PCB) that has cutouts around
the resistor groups to reduce parasitic capacitance
across the resistors. The nominal current through the
resistors has been chosen to be 5mA as a compromise
between the errors caused by power dissipation in the
resistors and parasitic impedances.
To improve the stability of the ratio, a number of
resistors was tested for self heating. The resistors
were then selected for the smallest cumulative effect.
The RVD is designed to work together with the
buffer described in [2] to achieve independence on
‹,(((
6W2
Monday
Tuesday
the load impedance. To account for the buffer input
capacitance, ceramic capacitors have been placed
Wednesday
across every resistor group of the upper arm. The
capacitance value was calculated to keep the product
of resistance and capacitance of every group the same,
as discussed in [3] and thus minimize the phase shift
at the output.
Thursday
The case of the RVD must be earthed for screening
and safety reasons. Previous experience with RVDs
at NMIA and the simulation discussed below showed
high sensitivity of the phase error to the capacitance
between the resistors and the case. To reduce this
Friday
effect, a guard was introduced. The guard is made out
of 25 mm brass pipe sections, cut in half, to cover the
top and bottom of the resistors, as illustrated in
Figure 1.
Figure 1. Layout of the resistor and guard arrangement.
The guard is driven by a second chain of resistors.
Since the requirements for the precision of these
resistors are not high, ¼ W metal film resistors were
used. They are mounted on the same PCB and
connected to the brass sections that are soldered to
the two sides of the PCB. Each section of the guard
covers only one of the two resistors in a group. It has
the same potential as the resistor pin at the side were
it is soldered to the board. This leads to symmetry of
the parasitic currents flowing onto and out of each
resistor, reducing the effect of these currents.
Simulation
195
 A Spice simulation was conducted to investigate the
performance of the RVD prior to the construction of
the first prototype. The parameters included in the
simulation were parasitic capacitance and inductance
of the resistors in the main chain, capacitance from
the resistors to the guard, capacitance from the guard
to the case and capacitance between the guard
sections. The simulation showed that the phase shift
could be adjusted to within 100 Prad with only one
capacitor at the output throughout the frequency
range of 10 Hz to 100 kHz.
Calibration of the RVD
The calibration of the RVD consists of three parts.
First the dc ratio of the RVD is measured against a
reference dc divider described in [4]. Then the ac-dc
difference of the RVD is measured against NMIA
working thermal converters [5]. From the dc ratio and
the ac-dc difference, the ac amplitude corrections to
the ac ratio are determined. Finally, the phase errors
of the RVD are measured using a modification of the
method described in [6].
U
RVD
ACV1 ACV2
Dual-Channel A1
Generator 1V
-10
U1
Ui U2
+10
A2
Figure 2. Setup for the measurement of the RVD phase
errors.
Monday
The setup for the measurement of the phase errors of
the RVD is shown schematically in Figure 2. It
consists of a dual channel generator, producing two
voltages, U and Ui, that are shifted by approximately
90 degrees, and two wattmeters each measuring the
Tuesday
product of U and Ui. The first wattmeter, also called
the Zero Power Factor Reference (ZPFR), consists of
an inverting and a non-inverting amplifier, A1 and A2,
respectively, each with a nominal gain of 10, and two
ac voltmeters, ACV1 and ACV2, measuring the
Wednesday
differences between U and the outputs of A1 and A2.
The output of the ZPFR, calculated by the computer,
is the difference between the squares of the readings
of ACV1 and ACV2. The second wattmeter is the
NMIA high-frequency thermal power comparator
(TPC) [7]. The TPC includes the RVD under test.
Thursday
The measurement is performed in two stages. First,
the cumulative phase error of the ZPFR and the TPC
is measured at each frequency by setting U to 1V and
bypassing the RVD. The RVD is then reconnected,
and the measurement repeated with U close to the
Friday
196
nominal input voltage of the RVD. The difference
between the two sets of measurements gives the
phase error of the RVD. At both stages, the outputs
of the ZPFR and the TPC are the mean of their
respective outputs at +90 degrees and –90 degrees.
This removes the effect of any offsets in the two
wattmeters.
Conclusion
A range of precision voltage dividers is under
development at NMIA to measure voltages up to
240 V with target amplitude and phase uncertainties
less than 100 PV/V and 100 Prad, respectively, at
100 kHz.
References
[1] G. W. Small, I. F. Budovsky, A. M. Gibbes,
J.R. Fiander, “ Precision Three-Stage
1000 V/50 Hz Inductive Voltage Divider,”
IEEE Trans. on Instrum. Meas., vol. 54,
pp.600 – 603, April 2005.
[2] I. Budovsky and T. Hagen, “A precision buffer
amplifier for low-frequency metrology
applications,” Conf. Digest CPEM2010.
Uu
Thermal [3] K.E. Rydler, S. Svensson and V.Tarasso,
Power
Ui
Comparator “Voltage dividers with low phase angle errors
for a wideband power measuring system,”
Conf. Digest CPEM2002, pp. 382 – 383.
[4] I. Budovsky and T. Hagen, “Precision ac-dc
transfer measurements based on a 1000-V
inductive voltage divider,” IEEE Trans. on
Instrum. Meas., vol. 58, pp. 844 – 847, April
2009.
[5] T. Hagen and I. Budovsky, “Single-junction
thermal voltage converters with reduced
uncertainties at frequencies up to 1 MHz,”
IEEE Trans. on Instrum. Meas., vol. 58, pp.
848 – 852, April 2009.
[6] I. Budovsky, A M Gibbes and G M Hammond,
“Voltage divider characterisation at
frequencies up to 200 kHz,” Conf. Digest
CPEM2000, Sydney, pp. 662-663, May 2000.
[7] I. Budovsky, A. M. Gibbes and D. C. Arthur,
“A high-frequency thermal power
comparator,” IEEE Trans. on Instrum. Meas.,
vol. 48, no 2, pp. 427-430, April 1999.