Hard-wired Controller

Hardware components-
Memory (4096*16bit)
MDR,AC -16bit
MAR, PC -12bit
(PC with (E,L,I,C), MAR with (E,L,I,C), and MDR with(E,L,I) signals)
Input output registers- INP, OUP - 8bit
ALU works with AC(E,L) only and carry is stored in flag E
Interrupt flag R (R sets When IE is set and any or both of FGI/FGO set)(when processor s interrupted , interrupt cycle reset R)
Interrupt Enable Flip flop is IE (set / reset by instruction ION / IOF)
Input and Output operation also set/reset flags FGI and FGO
(FGI set when external device write data in INP register. When INP is read by processor FGI resets )
(FGO is reset by processor when new data is written in OUP. Set by external device when it reads OUP)
A sequence Counter(SC) generates 8 clocks (SC is reset by instruction after its completion. Disable signal to Clock is controlled by instruction HLT.
Clock is enabled from external switch)

Following instructions are incorporated-

memory reference instructions-
AND, ADD, LDA, STA, BUN(branch unconditional), BSA(branch and save return address), ISZ (increment memory and skip next instruction if memory
becomes zero)
(these are MRI. Memory can be referred directly (given address contains info. ) or indirectly (given address contains the address where the info. Is stored ) )
Non MRI -Register based instructions-
CLA (AC=0), CLE(E=0), CMA(AC=1's complement of A), CME(E=1's complement of E), CIR(AC rotates right with E),CIL(AC rotates LEFT with
E),INC(Ac=AC+1), SPA(skip next instruction if A15=0),SNA(skip next instruction if A15=1),SZA(skip next instruction if AC=0),SZE(skip next instruction if
E=0),HLT(disable sequence generator)
Non MRI -I/O based instructions-
IN,OUT,SKI(skip next instruction if FGI=1),SKO(skip next instruction if FGO=1),ION(enable IE F/F),IOF(disable IE F/F)
Format of16-bit instruction-
15 14 12 11 0
I opcode Address/non mri inst. bits

3-bits of opcode selects one of the 7 mri instruction(opcode bits- 000 to 110) or non mri instructions(111)
I in case of mri , identifies direct(I=0) or indirect (I=1) instructions
in case of non-mri instructions register ref. (I=0) or I/O ref.(I=1) instructions
12-bit , in mri refers address, in case of non-mri it identifies one of register or I/O instruction

Flow chart of normal instruction execution-

Flow chart of interrupt execution-

Micro operations of hardwired controller

(normal execution R=0)
RT0 : MAR <- PC
RT1 : MDR<- M[MAR] , PC <- PC+1
RT2 : MAR <- MDR(11-0), I <- MDR(15), Decoder <-MDR(14-12)
(interrupt execution when R=1, first two memory locations for interrupt handling data and instruction)
RT0 : MAR <- 0, MDR<-PC
RT1 : M[MAR] <- MDR
RT2 : PC <- 0
RT3 : PC <- 1 , IEN <- 0 ,R <- 0 ;Reset
(In non-mri instruction, when I=0, T3,T4 cycle is idle)
D7IT3 : MDR <- M[MAR]
D7IT4 : MAR <- MDR
memory reference Instructions
AND BUN
D0T5 : MDR <- M[MAR] D4T5 : PC <-MAR ; Reset
D0T6 :AC <-AC . MDR ; Reset
ADD BSA
D1T5 : MDR <- M[MAR] D5T5 : MDR <-PC
D1T6 : AC <-AC + MDR ,E <-Cout ; Reset D5T6 : M[MAR]<- MDR; MAR <-MAR+1
D5T7 : PC <-MAR ; Reset
LDA ISZ
D2T5 : MDR <- M[MAR] D6T5 : MDR <- M[MAR]
D2T6 : AC <-MDR ; Reset D6T6 : MDR <-MDR+1
D6T7 : M[MAR] <-MDR; if MDR=0 then PC<-PC+1 : Reset
STA
D3T5 : MDR <-AC ; Reset
D3T6 : M[MAR] <-MDR ; Reset

Register instructions- I/O instructions-

D7I (conditional for register reference instruction) D7I (conditional for I/O reference instruction) Address
Address bits- b11 to b0 used to identify particular bits- b11 to b0 used to identify particular instruction
instruction D7IT3b11 – IN ; AC< INP, FGI=0; Reset
D7IT3b11 - CLA ; AC<-0; Reset D7IT3b10 – OUT ; OUP<-AC, FGO=0; Reset
D7IT3b10 - CLE ; E<-0; Reset D7IT3b9 – SKI ; if FGI =1 ,PC<-PC+1 ; Reset
D7IT3b9 - CMA ; AC<- 1's complement of AC; Reset D7IT3b8 – SKO ; if FGO =1 ,PC<-PC+1 ; Reset
D7IT3b8 - CME ; E<- 1's complement of E; Reset D7IT3b7 – ION ; IE=1 ; Reset
D7IT3b7 – CIR ; A15<-E,...............E<-A0; Reset D7IT3b6 – IOF ; IE=0 ; Reset
D7IT3b6 – CIL ; A0<-E,...............E<-A15; Reset
D7IT3b5 – INC ; AC<- AC+1; Reset
D7IT3b4 – SPA ; if A15=0 , PC<-PC+1 ; Reset
D7IT3b3 – SNA ; if A15=1 , PC<-PC+1 ; Reset
D7IT3b2 – SZA ; if AC=0 , PC<-PC+1 ; Reset
D7IT3b1 – SZE ; if E=0 , PC<-PC+1 ; Reset
D7IT3b0 – HLT ;disable clock

Logical circuit for Control signals using logic gates (OR gate , AND gate) with decoded bits of MDR and output of sequence counter as input
example for PC- has four control signals – enable(read), load(write),increment and clear with sequence counter and decoded bits of the MDR
PC(E) – T0+D5T5
PC(L) - D4T5+D5T7
PC(I)- RT1+RT3+D6T7(MDR)+D7IT3b4(A15)+D7IT3b3(A15)+D7IT3b2(AC)+D7IT3b1(E)+D7IT3b9(FGI)+D7IT3b8(FGO)
PC(C) - RT2

Design combinational Logical circuit using these control signals for PC

MAR- has four control signals – enable(read), load(write),increment, clear and sequence counter

MDR- has three control signals – enable(read), load(write),increment, and sequence counter

Memory- has two control signals – enable(read), load(write),

AC -

Circuit for interrupt ( R and IE flags)

(T0 .T1 .T2 ). (IE).(FGI+FGO) sets R flag

Complete schematic diagram showing all hardware components ,and logic circuit to generate control signals -