Amir Amirkhany
Basics of Clock and
Data Recovery Circuits
Exploring high-speed serial links
T
he choice of clock
and data recovery
(CDR) architecture
in serial links dic-
tates many of the block-
level circuit specifications (specs).
Block-level specs ultimately determine
the energy efficiency of the system.
Therefore, to design energy-efficient
serial links, it is important to under-
stand the basics of CDR operation,
CDR’s main performance metrics, and
the relationship between circuit-level
Digital Object Identifier 10.1109/MSSC.2019.2939342
Date of current version: 23 January 2020
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1943-0582/20©2020IEEE
parameters and system-level perfor-
mance metrics.
Basic Principles
High-speed serial links find applications
in many electronics devices where
gigabits per second of data must be
transferred over one or several lanes.
Figure 1 depicts some of these use
cases. In televisions, high-data band-
width (BW) must be delivered to the
integrated circuits that drive the pixels
on the display screen. In a smartphone,
e.g., the front and back cameras, touch
controller, memory, and USB connector
all deploy serial links.
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A serial link consists of a transmitter
(Tx) and a receiver (Rx). Figure 2 shows the
typical building blocks of a high-speed
link. The Tx includes a clock source, such
as a phase-locked loop (PLL), serializer,
and driver circuit for driving the output.
The Rx comprises an analog front end, a
CDR circuit to recover a clock and sample
and recover the incoming data, and a
deserializer. The focus of this article is
the CDR circuit at the Rx in terms of three
main questions:
1) How can an Rx generate a clock
to sample the data?
2) What impacts the performance
of CDR?
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 Panel
65 in Pixel Drivers
Rx
Film
Tx
Controller
PCB
(a)
FIGURE 1: The high-speed links applications in (a) a television and (b) a smartphone. PCB: printed circuit board.
RN, PSIJ
Tx Rx
SER DESER
AFE
PLL CDR
RJ, DJ PSIJ ISI, XTALK RJ, DJ
FIGURE 2: The serial link building blocks. RJ: random jitter; DJ: deterministic jitter; PSIJ:
power supply-induced jitter; ISI: intersymbol interference; XTALK: cross talk; SER: serializer;
DESER: deserializer ; AFE: analog front end; RN: random noise.
3) How does a CDR spec impact the on design tradeoffs through the use
rest of the system, such as the Tx PLL of various design examples, will be
spec or the Tx and Rx noise budget? covered. The same notation as past
This article is an abridged version tutorials will be referenced where pos-
of a tutorial given at the ISSCC in Feb- sible, and readers are referred to the
ruary of 2019 [27]. In the past years, past tutorials for some of the detailed
there have been two other tutorials on derivations. In-depth information on
this topic. A tutorial in 2011 [1] spe- jitter definition and measurement is
cifically focuses on digital PLL-based included in [3] and may be used as
CDRs and includes in-depth analysis of a companion.
digital phase-interpolator-based CDRs, When considering CDRs, a fair
their theory of operation, and design question to ask is “Why not just include
examples. Another tutorial [2] covers at the Rx a clock source, such as a crys-
CDR fundamentals as well as various tal oscillator, that matches the Tx’s clock
CDR architectures. In this article, the source?” The answer is that all crystal
theory of operation, with an emphasis oscillators have limited accuracy. An
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Front Back
Camera Camera
Touch Display
CPU
Memory
USB
(b)
Rx that deploys a 100-ppm oscillator,
e.g., slips 100 unit intervals (UIs) in only
1 million bits. For a 10-Gb/s serial link,
that equals merely 0.1 s. Another practi-
cal reason is that a clock source may not
be available at the Rx side due to system
cost considerations.
Figure 3 depicts a basic CDR archi-
tecture. Data recovery mainly involves
techniques such as continuous-time
or decision-feedback equalization. In
this article, the focus is primarily on
the clock recovery portion. In particu-
lar, the article discusses how to gen-
erate a stable clock source for the Rx
(functionality) and how to maximize
the data recovery margin (quality).
The quality of data recovery is
directly related to jitter. Jitter refers to
the deviations of a clock or data wave-
form’s transitions from an ideal clock,
as shown in Figure 4(a). In some lit-
erature, jitter may be represented by a
jitter sequence diagram. Various jitter
measurement metrics, such as period,
cycle to cycle, and so on, have been
introduced over the years [4]. The spe-
cific metric of interest for CDR charac-
terization is the relative jitter between
the received data stream and recov-
ered clock at the Rx. Figure 4(b) depicts
a data stream with jitter and a recov-
ered clock with zero jitter. Because
clock transitions in this figure do not
 track data transitions, the clock edge
may deviate from the center of the data
symbol, resulting in lost data recovery
margin. Conversely, if the clock tran-
sitions fully track data transitions, the
clock edge can always be centered with
respect to data transitions, leading to
the best data recovery performance. Full
jitter tracking is one of the major goals
of a good CDR circuit.
Jitter in serial links can be catego-
rized into three types: data dependent,
source, and CDR jitter. In Figure 2, data-
dependent, i.e., channel-induced, jitter
is caused by intersymbol interference
(ISI) or cross talk. Mitigating the impact
of data-dependent jitter is primarily
the domain of data recovery circuits.
The role of clock recovery circuits is
to suppress this jitter as much as pos-
sible in most CDR implementations.
Source jitter includes the effect of the
Tx PLL, clock distribution random jit-
ter (RJ) and deterministic jitter (DJ),
as well as Tx power-supply-induced
jitter (PSIJ). Source jitter is data inde-
pendent (to the first order), and the
role of clock recovery circuits is to
Mitigating the impact of data-dependent
jitter is primarily the domain of data
recovery circuits.
the expense of an extra lane. In many
implementations, the circuits between
the clock and data paths are matched
as much as possible to achieve maxi-
mum jitter tracking between the data
and clock. Figure 5 displays the block
diagram of such a system where for-
warded-clock frequency is half the
bit rate. In this type of system, data-
dependent jitter does not exist, source
jitter tracking can be maximized with
proper circuit architecture, and self-
generated jitter can be very small due
to the simplicity of the clock path in
the Rx. Forwarded-clock systems are
popular in many standards, such as
DDR2-5, MIPI D-PHY, and High-Defini-
tion Multimedia Interface, where one
Data Recovery
forwarded-clock lane can be shared
between multiple data lanes. However,
in many applications, adding the extra
lane may not be an option.
Main CDR Performance Metrics
To design a good CDR, it is impor-
tant to have metrics that can quantify
performance. Jitter tolerance (JTOL)
is one such metric adopted in many
standards [6]. JTOL is the measure
of how much sinusoidal source jitter
a CDR can tolerate at a given sinusoi-
dal frequency at a given bit error rate
(BER). JTOL includes the effects of ISI,
cross talk, data recovery performance,
and clock recovery performance. Fig-
ure 6(a) shows a typical JTOL graph.

track this jitter as much as possible. Input

CDR self-generated jitter includes Data Data Recovered
AFE DESER Data
the RJ and DJ from clock recovery Samplers
blocks, such as a voltage-controlled
oscillator (VCO) and charge pump as
Recovered Clock
well as Rx clock and data path PSIJ. A
Clock Recovery

good CDR creates only negligible self-

PD Loop Filter
induced jitter.
One alternative architecture to a
CDR-based system is a forwarded-clock
system. In a forwarded-clock system,
the Tx forwards a clock to the Rx at FIGURE 3: A simple CDR architecture. PD: phase detector.

Data
Ideal Lost Margin With
Recovered Zero-Jitter Clock
Clock Recovered Data
Clock
1 1 1
Jittered
Clock Data: 101010 0 0 0

Jitter Zero-Jitter Clock

Sequence
Time Clock With Jitter Tracking
Data UI: Width of 1 b in NRZ or a Symbol in PAM4
(a) (b)

FIGURE 4: (a) Jitter definition and (b) jitter tracking. NRZ: nonreturn to zero; PAM: pulse amplitude modulation.

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 At low jitter frequencies, a typical ensure proper domain crossing from To measure JTOL in a lab, the CDR
CDR should be able to track very the CDR to a CDR-independent clock is driven by an ideal Tx [typically a
large amounts of source jitter. In this domain. CDR’s jitter tracking generally BER tester (BERT)], and sinusoidal jit-
region, the practical tracking of jitter degrades at higher frequencies until it ter is injected at various frequencies
is limited by the depth of the data buf- becomes negligible and creates a floor at the Tx while the CDR BER is mea-
fer in the Rx data path provisioned to for the JTOL curve. sured. Jitter amplitude is increased
at every jitter frequency until the
measured BER falls below the target
Tx Rx threshold. Figure 6(b) depicts a typi-
cal JTOL measurement setup [4].
JTOL is employed to ensure that
SER DESER someone’s Rx works with someone
AFE else’s Tx. In other words, JTOL is
a system characterization method
and very important tool for setting
Match
specs in standards. Using JTOL, the
PLL Shared Tx designer can be tasked with guar-
anteeing that the Tx jitter at a given
Clock-Pattern frequency never exceeds the spec.
Generator Conversely, the Rx designer can be
AFE
tasked with making certain that
the receiver achieves target BER if
the transmit data stream meets the
JTOL spec. JTOL is easy to measure;
FIGURE 5: A forwarded-clock system.
however, it is practically impossible
to simulate at the transistor level
In-Band Out-of-Band at a very low BER. Another metric,
Jitter Jitter therefore, is required to guide the
Typically >1 UI clock recovery circuit design.
(S
Limited by FIFO ho The jitter transfer (JTRAN) function
uld J
Jitter Amplitude

Depth Above Tra TOL defines the ratio of the clock recovery’s
Sinusoidal

PHY Layer ck Ma
Ab sk output jitter to input jitter at a given
ov
eT
his sinusoidal jitter injection frequency.
Lin
Timing Margin e) JTRAN is a clock recovery characteriza-
Available for tion metric that does not include BER, is
Untracked easy to simulate at the transistor level,
Source Jitter Sinusoidal Jitter Frequency and is closely related to JTOL. JTRAN
(a) can be used to define parameters such
Jittery
as CDR BW and phase margin to guide
Data the design process. CDR is a feedback
Pattern Check/
BERT CDR system and is often nonlinear; none-
Error Count
theless, a linearized model can often
be used for qualitative analysis with
Frequency
satisfactory precision. Figure 7(a) shows
Jitter Amplitude (UIpp)

Generator
(Jitter Modulator) a typical JTRAN of a CDR. Again, at
low frequencies, all of the source jit-
Fail (BER > 10–x )
ter is transferred to the output of the
Pass (BER < 10–x )
CDR, while some frequency depen-
dence exists at the midfrequencies.
CDR BW is defined as the 3-dB BW of
Jitter Frequency the JTRAN curve, and jitter peaking
JTOL Measurement Setup (Casper) and peaking frequency are defined as
the peak of JTRAN and its associated
(b)
frequency, respectively. Although jitter
FIGURE 6: (a) A typical JTOL graph [6] and (b) a JTOL measurement setup [4]. FIFO: first in/ tracking is good for a CDR, high jitter
first out; PHY: physical; UIpp: unit interval (peak to peak). amplification (i.e., large jitter peaking)

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 can be detrimental, particularly for a
relay system where a cascade of CDRs
may be deployed. Figure 7(b) shows a
JTRAN measurement setup that con-
sists of a data generation instrument
with jitter injection capability (such as
BERT) and a spectrum analyzer [4].
As mentioned previously, JTOL
and JTRAN are closely related. Con-
sider a CDR with a timing margin of
T at a given BER when source jitter
is zero (Figure 8): This timing mar-
gin includes the impact of everything
(e.g., ISI, cross talk, CDR self-induced
jitter, and data recovery performance)
except for source jitter. Therefore, this
timing margin T is available for any
untracked source jitter:
JTOL( j~) = T data-dependent jitter and source jit-
JTRACK( j~)
= T .
1 - JTRAN( j~)
A note of caution with this equation.
It may be argued that, for better JTOL,
JTOL is a system characterization method and very
important tool for setting specs in standards.
it is desirable to increase the JTRAN
BW. This argument ignores the fact
that T in the equation is also a func-
tion of JTRAN BW because the CDR BW
has a direct impact on how much data-
dependent jitter gets suppressed.
To summarize so far, as we dis-
cussed in the first section, a good
CDR would filter as much of the data-
dependent jitter as possible, track
as much of the Tx data-independent
jitter as possible, and minimize its
own self-generated jitter. Increas-
ing CDR bandwidth will increase
ter tracking, and thus, it reduces the
impact of both source jitter and self-
generated VCO jitter [2]. Therefore,
the choice of the right CDR tracking
bandwidth is a balancing act between
data-dependent jitter filtering and
data-independent jitter tracking (and
self-jitter suppression). To find the
right balance, an accurate system-level
modeling is necessary.
CDR Design Tradeoffs
Figure 9 shows the block diagram of a
simple analog CDR. The phase detector
compares the transitions of the input
data sequence with the locally gen-
erated clock and creates up or down
signals. Because the phase detector’s
operation relies on data transitions,
input data often require transition
encoding schemes such as 8 b/10 b.
Figure 10(a) depicts the block dia-
gram of a Hogge phase detector [11]. For
every rising data transition, both the
DE and DR outputs create a pulse. For

Spectrum Analyzer
Jitter Peaking ∆Pin
0 dB ∆Pout
–3 dB –fmod +fmod
Jitter-Tracking BW Clk/
PLL/ IN
Data fc
CDR
Gen.
CLKin CLKout

JTF (fmod) = ∆Pout/∆Pin

Sinusoidal Jitter Frequency f3 dB
(a) (b)

FIGURE 7: (a) A typical CDR JTRAN graph and (b) a JTRAN measurement setup [4]. CLK: clock; Gen.: generation.

JTRACK HJTRACK(s)
JTRAN
∆
HJTOL(s)

CDR
∆ ω PL ω PH logω
JTOL ( jω ) = [Hanumolu]
JTRACK ( jω )
∆ Assume ∆ = 0.5
=
1 – JTRAN ( jω )

FIGURE 8: The JTOL and JTRAN relationship [2].

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 JTRAN can be used to define parameters
such as CDR BW and phase margin to guide
the design process.
the DE pulse, the timing of the rising
edge depends on the timing of data
arrival while the falling edge depends
on the clock rising edge. For a DR pulse,
the rising and falling edges depend
solely on clock edge timing. As a
result, subtracting the area under the
DE pulse from the area under the DR
pulse creates an output that is linearly
proportional to data versus clock edge
timing, i.e., the phase error, as dis-
played in Figure 10(b). When the CDR
locks, the data-to-clock-rising time is
equal to the clock’s half-period; there-
fore, data are sampled at the middle
of the UI.
A Hogge phase detector has several
limitations. First, most systems today
are low swing due to power consid-
erations. Having a low-swing signal
directly driving combinational logic
creates some challenges. Second, the
flip-flop clk-q output delay causes a
IUP
D UP
PD
DN
IDN
FIGURE 9: A simple CDR architecture.
D –π
CLK
(a)
FIGURE 10: (a) A linear phase detector [11] and (b) the Hogge phase detector’s response. KPD: phase detector gain.
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systematic offset in the locking phase
and is better to be matched in the D
input of the DE logic. Third, the half-
cycle delay between the DE and DR
pulses creates DJ in the CDR output.
All of these issues can be solved by
proper circuit design, but designers
often opt for the simpler, but non-
linear, bang–bang (Alexander) phase
detector (described in the “CDR Archi-
tectures” section).
Figure 11 shows the phase-domain
model for the CDR with a linear phase
detector. Using this model, we can
derive a number of important ana-
lytical equations for the CDR that
will help us with understanding the
design tradeoffs:
H JTRAN (s) = 1 + sRC
1 + sRC + s 2
K VCO K PD I CP
~z = 1 ,
RC
VCO
CLK
R however, to maintain stability, we
C
DE
tdata t clk(0→1)
DR
t clk(0→1) t clk(1→0)
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~ PL . 1
RC
~ PH . K VCO .K PD .I CP .R,
JTRAN BW . ~ ug . ~ PH,
U M = tan -1c m,
~ ug
~Z
Jitter Peaking . 8.686~ Z .
~ ug
In these equations, ~ Z , ~ PL, and ~ PH
are the zero, lower pole, and higher
pole frequencies, respectively, of the
JTRAN function and { M is its phase
margin. These approximations are
accurate when ~ PL % ~ PH .
To gain a sense of its design trad-
eoffs, let us design a 10-Gb/s CDR with a
tracking BW of 5 MHz. For calculations,
let’s assume a linear phase detector with
a gain of KPD = 1/(2pi), and a ring VCO
with a gain of KVCO = 16 GHZ/V. Table 1
lists the CDR BW, phase margin, peak-
ing, and zero frequency as functions of
choices for I CP, loop-filter resistance (R),
and capacitance (C). Note that the values
in Table 1 are obtained from accurate
, formulas rather than the approxima-
C
tions discussed earlier to maintain accu-
racy when the two poles of the system
are comparable.
In the first trial, for reasonable values
of 100 µA, 1 kΩ, and 60 pF for the CDR
components, the CDR BW significantly
exceeds the target spec. The simple, ana-
log CDR offers two knobs for reducing
the BW. We can reduce R by eight times;
must increase C while being conscious
of the required area. Although using
this knob gets us closer to the target
of a 5-MHz BW, the system requires
a large capacitor with considerable
+1
+π
ΦE
–1
1 α
KPD =
π
α Is the Transition Density
α = 0.5 for Random Data
(b)
 peaking and marginally acceptable let us assume the up and down sig- bit (LSB) current digital-to-analog
phase margin. Alternatively, we can nals are binary (Table 2). Therefore, converter (DAC). But, in fact, it is
reduce I CP to 12 µA; however, we are the output current I OUT has a range slightly worse because of the cur-
left with large peaking and a modest of - 4I Unit # I OUT # +4I Unit , where rent subtraction. In any subtrac-
phase margin. It is only by using both I Unit = 12 µA. Therefore, the block tion, although signals subtract, the
knobs together that we can achieve shown in Figure 12(a) is really a errors can add. For example, there
the target BW with good stability. We 2.5-GS/s, ~3-b, 12-µA least significant are exactly 19 UP/DN combinations
should remember, however, that if
any of these variables change due to
process, voltage, or temperature vari- Φ in Φe Φ out
ations, both the tracking BW and jitter – KPD ICP R + 1/(sC ) KVCO/s
peaking of the system would at least
increase proportionally.
Now, let us assume that the fourth (a)
configuration with 400-pF loop capac- HJTRAN(s)
itance and 12-µA charge-pump current
is acceptable. Let us now consider
Peaking
how difficult it is to create the 12-µA
charge pump current.
In most process nodes, a straight
10-G sample/sec charge pump is not
easy to implement. Alternatively,
ωz ω PL ω PH logω
log
the phase detector and the charge
pump can be parallelized to operate (b)
at a lower rate. A four-way parallel
system is shown in Figure 12(a). The FIGURE 11: A CDR analytical model [2]. ~ PL: zero frequency; ~ PH : lower pole frequency; ~ z:
higher pole frequency. ICP: charge-pump current.
output of the four-way system can
be described as
4
TABLE 1. THE ANALOG CDR BW AND PEAKING AS A FUNCTION OF
I out = / (UP[m]I UP[m] - DN[m]I DN[m]) COMPONENT VALUES.
m =1

4 ICP R C BW PM PK fz
+ / 1(UP[m]TI UP[m] - DN[m]TI DN[m])
44444444424444444443. NUMBER (μA) (Ω) (pF) (MHz) (0) (dB) (MHz)
m =1
Error
1 100 1,000 60 44 86 0.4 2.7
The terms TI UP and TI DN represent 2 100 125 400 8 61 2.5 3.1
a current mismatch in the parallel 3 12 1,000 60 7.4 64 2.2 2.7
charge pumps. Thus far, this article
4 12 1,000 400 4.9 85 0.5 0.4
has discussed a linear phase detec-
tor, but for the immediate argument PM: phase margin; PK: peaking; fz: zero frequency.

UP_EN
IUP IUP
D UP[3:0] IOUT D UP[3:0] Adder IOUT
PD PD or CODE[2:0]
+ +
DESER (1:4) R DESER (1:4) Major R
DN[3:0] DN[3:0] Vote
C C
2.5 Gb/s IDN IDN 4X
DN_EN
2X
1X
4 4
IOUT = (UP[m]IUP[m] – DN[m]IDN[m]) Code [2:0] = (UP[m] – DN[m])
m=1 m=1
(a) (b)

FIGURE 12: (a) A four-way parallelized PD and charge pump (CP) and (b) a four-way parallel CP with digital subtraction.

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TABLE 2: SOME UP/DOWN (UP/DN)
COMBINATIONS THAT RESULT IN
ZERO IOUT.
NUMBER UP[3:0]−DN[3:0]
1 4’b0000−4’b0000
2 4’b0010−4’b0001
3 4’b0100−4’b0001
4 4’b1000−4’b0001
5 4’b1001−4’b0110
that should create zero I OUT but due
to the error term, some can current
a positive IOUT and some can create
a negative IOUT. Similarly, there are
many ways to get IOUT = +IUnit and
IOUT = –1 IUnit. As a result, the overall
charge pump may not even be mono-
tonic with respect to UP/DN input
code if it is not designed carefully.
To simplify the design of the par-
allelized charge pump, some CDRs
move the subtraction logic to the digi-
tal domain, as shown in Figure 12(b).
This change relaxes the monotonicity
requirements on the charge pump and
greatly simplifies its design; however,
the digital logic will introduce some
latency into the loop. Some CDRs push
this idea further, using only the sign
of the final subtraction result and a
simple 1-b charge pump instead. This
operation is equivalent to a majority
vote, makes the system nonlinear,
JTRAN
10
0 20 ns
–10
–20
–30
105 106
Frequency
(a)
FIGURE 13: The effect of loop latency on the jitter-transfer function. (a) Jitter transfer functions for various loop latencies. (b) CDR BWs and
phase margins for various loop latencies.
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and reduces the BW, but sometimes it
is a good tradeoff to make.
Thus far, we have neglected loop
latency in our CDR modeling; how-
ever, with the introduction of digi-
tal logic to the loop, which is often
implemented in the lower frequency
domain at the register transfer level
(RTL), we must be cognizant of the
effect of latency on the loop parame-
ters. The loop phase-margin equation
in the presence of loop latency of D is
U M = tan -1 c m - D~ ug .
~ ug
~Z
Therefore, loop latency becomes im­­
portant when D~ ug is not negligible,
e.g., for jitter-tracking BW of 5 MHz,
D % 30 ns. Figure 13 plots the jitter-
transfer function for various values
of loop latency. As shown, even loop
latencies in the nanosecond range
can noticeably change the system
phase margin and, consequently,
its jitter peaking. One nanosecond
is a pipeline stage for a 1-GHz syn-
thesized logic. Therefore, not many
pipeline stages are allowed for any
digital implementation.
To summarize this section, the sim-
ple analog CDR has many limitations:
a linear PD has mismatch issues and
other design issues. It requires a large
cap and small currents to ensure sta-
bility. In particular, the choice of loop
R = 1 KΩ, C = 400 pF, KVCO = 16 GHz/V
0 ns
10 ns
30 ns
107 108 109
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resistor impacts both the BW and sta-
bility. Moving elements of the opera-
tion to the digital domain may relax
some design constraints, but it intro-
duces latency issues.
CDR Architectures
To address the limitations of analog
CDR, various architectures have been
developed. Each has its own benefits
and limitations, and the choice of archi-
tecture depends on power and perfor-
mance specs, as well as the process
node in which CDR is implemented.
Alexander (Bang–Bang)
Phase ­Detector
An Alexander phase detector is a non-
linear phase detector used in most
CDR implementations. Figure 14 shows
the block diagram. This phase detec-
tor takes two samples per symbol (bit)
period: a data sample (dn) and a cross-
ing sample (xn). When there is a transi-
tion in data sequence (dn ! = dn+1), the
xn sign determines whether the clock
is early or late. A CDR with this type
of phase detector locks onto the data
crossing point and “assumes” that the
optimal data sampling point is a half-bit
period away. This leads to a suboptimal
operation when the data eye shape is
not symmetric.
The bang–bang phase detector (BBPD)
is a nonlinear circuit; therefore, the
CDR loop gain and BW are dependent
KPD = 1/2 π, ICP = 12 µA,
D (ns) CDR BW PM (°)
(MHz)
0 5.4 85
2 5.8 82
4 6.2 78
6 6.7 75
8 7.4 71
10 8.3 67
(b)
 dn xn dn+1

D +1
dn+1
DL
xn –π +π ΦE
CLK
–1

dn
DE KPD = ∞

xn (Assuming Zero Jitter)

Useful Range = [–π, π ]
dn xn dn+1
CLK

FIGURE 14: The Alexander (bang–bang) phase detector.

on data jitter, and CDR stability should

be verified with different assumptions +1 + α
about jitter distribution. For a 50% +1 – α
+1
transition density, the BBPD gain can α
be expressed [1] by
–1 + α
1 –1 –1 – α
K PD = (Gaussian jitter),
v 12 dn xn dn+1 xn+1 dn xn dn+1 xn+1
(a) (b)
K PD = 1 (uniform jitter).
v 2r
FIGURE 15: The signal transition diagram for (a) an NRZ no-ISI and (b) an NRZ 1+ az−1 channel.
Because BBPD locks onto the data tran-
sition point, if channel ISI creates
deterministic deviations in the transi-
tion point from the half-symbol point, +1
the CDR can lock onto the suboptimal +2/3
phase or exhibit deterministic jitter. +1/3
The best way to analyze such issues is 0
with the help of the signal transition –1/3
diagram (or trellis) at the Rx input. Fig- –2/3
–1
ure 15 illustrates the trellis diagram for
dn xn dn+1 xn+1 Major Minor Intermediate
nonreturn-to-zero (NRZ) signals over
Transition Transition Transition
no-ISI and 1 + az -1 channels. Let us
consider the latter: the channel out-
FIGURE 16: Transition classification in a PAM4 system for BBPD-based clock recovery.
put at time n can be either +1 - a or
+1 + a if the data transmitted at time
n were +1 and the data transmitted also includes crossing slicers placed up/down generation would lock with a
at time n - 1 were -1 or +1, respec- at +a and -a . As the trellis in Fig- slight phase offset. This issue is more
tively. If the data bit for time n is +1, ure 15 shows, however, only the tran- pronounced in PAM4 Rxs, as shown
the channel output at time n + 1 can sitions from +1 + a to -1 + a and in Figure 16 [7]. Although the optimal
be only +1 + a or -1 + a, depending the transition from -1 - a to +1 - a crossing thresholds are at 0, !1/3,
on whether the transmitted bit at time pass through the half-UI point at the and !2/3, the right transitions should
n + 1 was +1 or -1, respectively. A +a and -a threshold, respectively. be selected for each slicing threshold.
loop-unrolled decision-feedback equal- The other two transitions (+1 - a to A CDR with an Alexander phase
izer with samplers placed at +a and -1 + a) and (-1 + a to +1 - a) pass detector has a natural oscillation
-a thresholds is often used at the the aforementioned thresholds at an frequency determined by its limit
front end to cancel the first postcur- offset from the midpoint. Therefore, a cycle. The period and amplitude of
sor ISI tap a. In such systems, the PD CDR utilizing all of the transitions for this oscillation is proportional to the

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 ever, these CDRs gained popularity
In general, MM CDRs are not as robust only over the last decade as a low-
as oversampled CDRs and should be power alternative to oversampled archi-
deployed with care. tectures. The updated equation for an
MM CDR is given by

CDR loop latency. Figure 17 demon-
strates this relationship. When the
limit-cycle oscillation frequency falls
within or is close to the tracking
BW of the CDR, it adversely affects
the jitter peaking and CDR perfor-
mance. This issue can be addressed
by reducing the loop latency or add-
ing a feed-forward path to the VCO
with small latency, as discussed fur-
ther in this section.
The BBPD is effectively a two-times
oversampling system and doubles the
number of clock phases and front-end
samplers in the CDR. As the complex-
ity of serial links grows and especially
Φe (t)
D
up/dn
ΦCLK(t)
FIGURE 17: The effect of limit-cycle dependency on loop latency.
because designs started deploying
analog-to-digital converters at the
front end, the power overhead of a
two-times oversampled front end
have become prohibitive. Therefore,
lately, many designs have begun using
baud-rate CDRs instead.
Baud-Rate CDRs
Baud-rate CDRs take only one set of
samples per UI and, therefore, require
half the clock phases of BBPD-based
CDRs. A Mueller–Muller (MM) CDR is
the most popular form of baud-rate
CDR. The original paper that describes
the CDR algorithm dates to 1976; how-
Φe(t)
D of the algorithm are proposed in [7]
up/dn
ΦCLK(t)
Tx k = e k d k - 1 - e k - 1 d k
= y k d k - 1 - y k - 1 d k,
where the sampled received data are
y k = R m d mh(mT + x) and the sampled
error is e k = y k - d k h(x).
For an uncorrelated input sequence
dm, it can be shown that
E (Tx k) = E (d 2k) ([h (T + x) - h (-T + x)]) .
Therefore, the timing error is mini-
mized where the postcursor ISI tap
is equal to the precursor ISI. Fig-
ure 18 depicts one implementation
of an MM phase detector for an NRZ
link [16]. The implementation is a
sign-sign variation of the MM algo-
rithm and requires the VREF level to
be adjusted to match h0, the main
tap of the channel. Other variations
and [17] to tune the locking point of
the CDR in favor of the precursor
or postcursor ISI taps. In general, MM
CDRs are not as robust as oversam-
pled CDRs and should be deployed
with care.

CLK
VREF– + errm Error
– Sampler ERR = +1
DFF Dn–1
+VREF
ERRn Target
Sampling
+ errp Point
VREF+ – 0 ERR = –1
DFF

Phase Early: DN = 1 Dn
Data Dn –VREF
Data
Phase Late: UP = 1 ERR = +1
Sampler
CLK
Phase Error:
∆Tn UP DN
∆Tn = Dn × Dn–1 × (ERRn – ERRn–1)
+1 1 0
(a)
PD 0 0 0
Output Truth Table –1 0 1
(b)

FIGURE 18: An MM CDR implementation: (a) PD architecture and (b) early and late regions [16]. ERR: error.

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 Proportional-Integral CDR
As discussed previously, in the sim-
ple analog CDR, the resistor R value
controls both the BW and stabil-
ity of the CDR loop. Therefore, to
reduce BW, we have to either reduce
R and increase C or reduce I CP . Fig-
ure 19 shows a redrawn model of the
analog CDR that is mathematically
equivalent to the model in Figure 11.
However, viewing the CDR in this
framework allows us to conceptu-
alize an alternative implementation
of a CDR where the proportional
and integral gains are independent
variables. Physically, this requires a
VCO that has two control inputs: one
directly driven from the phase detec-
tor and the other driven by the inte- The following are a few important
grator in the integral path. Figure 20 points to note, based on the equations
displays one example implementation in this section:
of this type of CDR [21]. The equations 1) Proportional gain (K P) determines
for the poles, zeroes, and BWs of this the jitter-tracking BW. It can there-
type of CDR are given as fore be used to trade off ISI-in-
duced jitter for source jitter.
1+ s 1 2) For a fixed K P, integral gain (K I) de-
~z
H JTRAN (s) = , termines open-loop ~ z; therefore,
1+ s 1 + s2 1
~ PL ~ PL ~ PH a lower K I increases the phase
~z =
KI , margin and reduces jitter peak-
KP ing. However, K I determines ~ PL
~ PL .
KI , as well, which sets the CDR’s loop
KP
time constant. As a result, a lower
~ PH . K P , K I increases the CDR locking time.
JTRAN BW . ~ ug . K P , 3) Also, K I is the term that makes the
CDR loop second order; ­therefore,
U M = tan -1c m.
~ ug
~Z CDR cannot track frequency change

KPDICPRKVCO
Φ in Φe Φout
1/s In simple-analog CDR, R controls
both BW and stability.
KPDICP(1/C )KVCO 1/s
Reducing BW Requires:
Small R and Large C
(a) Or Small I
Can Re-Architect the Loop to
Have Independent Knobs:
KP Proportional Path: KP
Φ in Φe Φout Integral Path: KI
1/s
With the proper VCO
Kl 1/s architecture, it will have a different
set of knobs to optimize.

(b)

FIGURE 19: (a) An equivalent model of an analog CDR. (b) The model of a proportional-integral CDR.

20-GHz LC-OSC
Samplers
Phase- 20-Gb/s, 2-b Microstrip
Detection Recovered
40 Gb/s UP0+
Logic Data DN0–

CK1 CK0 UP1+ CK2 CK3

Four-Phase, Proportional UP1/DN1 DN1–
20-GHz Clock Control Path UP0/DN0
20-GHz
QVCO INT-ctrl

Integral
Proportional Path
Control Path
Directly From PD
Vbias
CPINT

Vbias_q
Integral Path (No R)

FIGURE 20: An example implementation of a proportional-integral CDR [21].

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 10 10
0 ns 0 ns
10 ns 10 ns
0 20 ns 0 20 ns d

30 ns 30 ns

–10 –10

Dp DI
–20 –20

–30 –30
105 106 107 108 109 105 106 107 108 109
Frequency Frequency
(a) (b)

FIGURE 21: The proportional-integral CDR’s sensitivity to loop latency. (a) The effect of delay in the proportional path and (b) the effect of
delay in the integral path on the CDR’s JTRAN function.

Digital CDR
DCO A proportional-integral CDR architec-
ture lends itself very well to a digi-
KP PDAC tal implementation, the concept of
D
CLK
PD which is shown in Figure 22. Here,
the integrator is replaced by an accu-
KI + IDAC
mulator, thus eliminating the need
Z –1 for a large capacitor, and the integral
and proportional paths are merged
with a digitally controlled oscilla-
tor (DCO). Because the integral path
FIGURE 22: A digital (hybrid) DCO-based CDR. PDAC: proportional path DAC. is less sensitive to delay, it is often
implemented in the RTL.
Although this architecture does
DCO not require a charge pump, it does
require a high-resolution DAC in the
KP PDAC
D CLK integral path, which can have chal-
PD lenging specs. To better understand
∆Σ the requirements on the integral-path
KI + IDAC
Modulator DAC (IDAC), let us perform some calcu-
Z –1 lations using the CDR parameters we
have been using all along. In the digi-
tal CDR, each phase-detector update
Signed Unsigned Signed
Saturate would change the oscillator’s control
M+D D D+1 Carry M+1
+ + + voltage (i.e., current) by K I # LSB IDAC .
D Therefore, to match the analog CDR
Z –1 M Z –1 M
example with I CP = 12 µA, C = 400 pF,
IDAC_in
∆Σ_State and UI = 100 ps, LSB IDAC 1 12 µA #
Integ_out
100 ps/400 pA = 3 µV. This means
that the digital CDR requires a 3-µV,
FIGURE 23: Enhancing resolution with a TR modulator. 10-GS/s DAC, instead of the 12-µA,
10-GS/s charge pump required by the
(e.g. sinusoidal jitter) with zero K I . paths on the CDR’s JTRAN for the same analog CDR. Fortunately, we can use
As a result, there is a limit to how CDR parameters, as depicted in Fig- TR techniques to achieve the desired
small K I can be, a value that is set ure 13. The plots demonstrate that this resolution without much complex-
primarily by the JTOL spec. type of CDR can tolerate significant ity overhead.
Figure 21 shows the impact of delay latency in the integral path without Figure 23 shows a model of the
in the CDR’s proportional and integral much impact on the CDR’s stability. digital CDR with TR modulator in the

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 integral path [1]. The TR modula-
tor toggles the LSB at the DAC input
with the proper duty cycle to create
a high-resolution DAC output. Borrow-
ing an example from [1] with a minor
modification, let us assume that the
accumulator is 7’b00011_00 (M = 5
and D = 2) and the phase detector
generates a series of “1” outputs. The
accumulator, TR state (initial condi-
tion 3’b0_00), and DCO input would
change as follows over multiple phase
detector updates:
■■ TR _state = 3’b0_01, IDAC_in =
3 + 0 = 3
■■ TR _state = 3’b0_10, IDAC_in =
3 + 0 = 3
■ ■ TR _state = 3’b0_11, IDAC_in =
3 + 0 = 3
■■ TR _state = 3’b1_00, IDAC_in =
3 + 1 = 4
■■ TR _state = 3’b0_01, IDAC_in =
3 + 0 = 3
■■ f.
The pattern repeats, with a “1” generated
every fourth cycle. The gain of the inte-
gral path in this architecture is K I /2 D.
Although TR helps with the DAC
resolution problem, the integral path,
including the accumulator and DAC,
still operates at one sample per phase-
detector update. This could lead to high
complexity and power consumption. In
many implementations, the output of
the phase detector is decimated before
it is passed to the integral path. Deci-
mation by N reduces the integral gain
of the CDR by a factor of N. An example
implementation of such a CDR can be
found in [20].
Np
D
PD
NI
FIGURE 24: A fully digital PI-based CDR.
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In many implementations, the output of
the phase detector is decimated before it is
passed to the integral path.
In cases where a local precision oscil-
lator is available at the Rx, it is possible
to remove the oscillator from the CDR
loop and instead use a phase interpola-
tor (PI), as depicted in Figure 24. In this
architecture, the phase-accumulation
logic together with the PI effectively
form a DCO. In such architectures,
the phase-interpolator’s integral non-
linearity and differential nonlinearity
are important for CDR performance. A
detailed analysis of such architectures
is provided in [1], and a design example
can be found in [23].
Summary and Conclusions
This article covered various aspects of
CDR design through the use of exam-
ples. This concluding section reviews
the CDR design flow and provides
brief references to a few topics not
previously covered.
CDR design typically begins by
defining the JTOL spec for the sys-
tem. If the design has to comply with
a standard, the JTOL spec is often
already specified.
JTOL is essentially a means by which
to negotiate the jitter spec between
the Tx and Rx and between the data
recovery and clock recovery circuits
at the Rx. JTOL specifies how much jit-
ter the Tx is allowed to generate and
PI Phase Select
KP
+ +
∆Σ
NI + Z –1
Modulator
Z –1
at 13:44:21
at what frequencies. It also specifies
how much of the budget can be taken
by equalization and how much by
clock recovery.
The next phase in the design is to
create a JTRAN spec for the CDR using
the JTOL spec to guide the transistor-
level design.
A high-level model of the CDR is often
the best way to iterate through architec-
ture choices and derive the block-level
specs. The CDR model should include
everything that impacts the CDR BW
and dynamics. In particular, all poles,
zeroes, and latencies in the loop must
be properly modeled.
An analog bang–bang CDR may be
adequate if a large loop capacitor and
two-times oversampled front ends
(slicers and clocks) are acceptable.
A proportional-integral architec-
ture may provide more flexibility if a
VCO with two frequency adjustment
knobs can be designed.
A baud-rate CDR may reduce the
number of required clock phases,
but it is more sensitive to channel
response. There is also more interac-
tion between the CDR and equaliza-
tion circuits in a baud-rate CDR.
Hybrid architectures may lead to
more optimized designs, but it is impor-
tant to watch for latencies. Often it is a
External Clock Source
PI Clock Source
CLK
PI
PI
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 good idea to include a fast proportional
path (i.e., small delay, no decimation).
When optimizing the CDR archi-
tecture, it is important to budget
for CDR’s self-generated jitter. The
budget can determine the choice
between LC versus ring VCO, and cur-
rent mode logic versus CMOS clock
distribution, or may force a dedi-
cated regulated supply for the clock
path. Power-supply-induced jitter may
sometimes be a large portion of the
self-generated jitter.
CDRs have limited locking range,
and, although gear-shifting the CDR
settings during initialization can
increase the range, it is often not
enough. Therefore, when architecting
the CDR, it is important early on to
determine the initial frequency-acqui-
sition method (Note that frequency
acquisition was not covered in this
article.) Many systems allocate an ini-
tialization state, during which a clock
signal is sent over the data line by the
Tx and can be used by the Rx for the ini-
tial frequency acquisition. Other stan-
dards require the Rx to acquire a lock
without any special training sequence.
Examples of some CDRs with broad
capture range techniques can be found
in [24]–[26].
Clock recovery circuits often inter-
act with the equalization circuits, as
the choice of sampling phase deter-
mines the sampled channel response
of the system. Therefore, it is impor-
tant to simulate clock recovery with
data recovery.
Many of today’s systems require
fast transitions between the power-
down state and the active state. In
such cases, fast wake-up CDR archi-
tectures are required. In digital CDR
architectures, frequency information
may be stored and recovered between
states; however, phase information
must still be acquired after every
state transition. Some examples of
fast wake up CDR architectures can be
found in [2].
Acknowledgments
I thank Dr. Valentin Abramzon, Dr.
Anup Jose, Prof. Sam Palermo, and
Prof. Ali Sheikholeslami for their
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About the Author
[11] C. Hogge, “A self correcting clock recov- Amir A m i rk h a ny (a.amirkhany@
ery circuit,” J. Lightw. Technol., vol. 3, no.
6, pp. 1312–1314, 1985.
samsung.com) received his B.S. degree
[12] J. D. H. Alexander, “Clock recovery from from Sharif University of Technology,
random binary signals,” Electron. Lett.,
vol. 11, no. 22, pp. 541–542, 1975.
Tehran, Iran, his M.S. degree from the
[13] M. Verbeke, P. Rombouts, X. Yin, and G. University of California, Los Angeles,
Torfs, “Inverse Alexander phase detector,”
Electron. Lett., vol. 52, no. 23, pp. 1908–
and his Ph.D. degree from Stanford
1910, 2016. University, California, all in electrical
[14] K. Mueller and M. Muller, “Timing recov-
ery in digital synchronous data receiv-
engineering. He is a senior director
ers,” IEEE Trans. Commun., vol. 24, no. 5, of engineering at Samsung Electron-
pp. 516–531, 1976.
[15] V. Balan et al., “A 4.8–6.4-Gb/s serial link
ics, in charge of the development of
for backplane applications using decision future generations of high-speed inter-
feedback equalization,” IEEE J. Solid-State
Circuits, vol. 40, no. 9, pp. 1957–1967,
faces for Samsung displays. Prior to
2005. Samsung, he was a design manager at
[16] F. Spagna et al., “A 78 mW 11.8 Gb/s se-
rial link transceiver with adaptive RX
Ramus Inc., where he led the devel-
equalization and baud-rate CDR in 32 nm opment of proprietary high-speed
CMOS,” in Proc. IEEE Int. Solid-State Cir-
cuits Conf. (ISSCC), 2010, pp. 366–367.
memory interfaces. He won the best
[17] R. Dokania et al., “10.5 A 5.9pJ/b 10Gb/s student paper award at the 2008 IEEE
serial link with unequalized MM-CDR in
14nm tri-gate CMOS,” in Proc. IEEE Int.
Global Communications Conference,
Solid-State Circuits Conf. (ISSCC) Dig. Tech. has authored or coauthored over 25
Papers, 2015, pp. 1–3.
[18] P. Upadhyaya et al., “A fully adaptive 19-
IEEE conference and journal papers,
to-56 Gb/s PAM-4 wireline transceiver and has more than 40 issued U.S. pat-
with a configurable ADC in 16 nm FinFET,”
in Proc. IEEE Int. Solid-State Circuits Conf.
ents. He is a Senior Member of the IEEE.
(ISSCC), 2018, pp. 108–110. 
CIRCUITS
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