lntegrated Training System

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Logic Gates in Combination

When you look at logic circuit diagrams for digital equipment, you are not going to see just a
single gate, but many combinations of gates. At first it may seem confusing and complex. lf you
interpret one gate at a time, you can work your way through any network. ln this section, we will
analyze several combinations of gates and then provide you with some practice problems.

Fig 5.25 shows a typical example of a logic circuit. The inputs to the Boeing 767 gear warning
system are from microswitches on various landing gear components. The outputs are gear
warning lights which illuminate based upon a combination of those switches, either/or being
closed or open.

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rtt. tL
utcf llm

ltat,alrI
toG F> ontcrror ltnflrt: Loelc . 1
crlfl Pnu tErsoR l^nsEr f^R

Figure 5.25 - Boeing 767 Gear Warning Circuit

35 Module 5.5 Logic Circuits

Use and/or disclosure is
governed by the statement
TTS lntegrated Training System on page 2 of this chapter
O Copyright 2010
 I ntegrated Training System
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Figure 5.26 (view A) shows a simple combination of AND gates. The outputs of gates 1 and 2
are the inputs to gate 3. You already know that both inputs to an AND gate must be HIGH at the
same time in order to produce a HIGH output.

Figure 5.26 - Logic gate combinations:

A. Simple combination of AND gates;
B. Simple combination of AND gates and OR gate.

The output Boolean expression of gate 1 is RS, and the output expression of gate 2 is TV.
These two output expressions become the inputs to gate 3. Remember, the output Boolean
expression is the result of the inputs, in this case (RS)(TV); spoken "quantity R AND S AND
quantity T AND V."

ln view B we have changed gate 3 to an OR gate. The outputs of gates 1 and 2 remain the
same but the output of gate 3 changes as you would expect. The output of gate 3 is now
(RS)+(TV); spoken "quantity R AND S OR quantity T AND V."

ln figure 5.27 (view A), the outputs of two OR gates are being applied as the input to third OR
gate. The output for gate 1 is R+S, and the output for gate 2 is T+V. With these inputs, the
output expression of gate 3 is (R+S)+(T+V).

36
Module 5.5 Logic Circuits Use and/or disclosure is
governed by the statement
TTS lntegrated Training System
on page 2 of this chapter
O Copyright 2010
 lntegrated Training System
***igned ift 66$0*i*ii*n wil*ih*
siub$Spro.co. il* queslitt* pta*l.ie,e e.i4

[H+ 5l +[T+Vl

[E+ 5f [T+Vf

H+ST+V

Figure 5.27 - Logic gate combinations:

A. Simple combination of OR gates;
B. Simple combination of OR gates and AND gate;
C. Output expression without the parentheses.

ln view B, gate 3 has been changed to an AND gate. The outputs of gates 1 and 2 do not
change, but the output expression of gate 3 does. ln this case, the gate 3 output expression is
(R+S)(T+V). This expression is spoken, "quantity R OR S AND quantity T OR V." The

37 Module 5.5 Logic Circuits Use and/or disclosure is

governed by the siatement
TTS lntegrated Training System on page 2 of this chapter
O Copyright 2010
 I ntegrated Training System
ile*igneci i* ass**iazian v;it,,i the
*lubfifipro.**. uk que$iion pra*tite aid

parentheses are used to separate the input terms and to indicate the AND function. Without the
parentheses the output expression would read R+ST+V, which is representative of the circuit in
view C. As you can see, this is not the same circuit as the one depicted in view B. lt is very
important that the Boolean expressions be written and spoken correcfly.

The Truth Table for the output expression of gate 3 (view B) will help you better understand the
output. When studying this Truth Table, notice that the only time f is HIGH (logic 1) is when
either or both R and s AND either or both r and V are H|GH (logic 1).

R S T V f

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 1

0 1 1 1 1

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 I 0 1

1 1 1 1 1

f = (R+S) (T+V)

3B
Module 5.5 Logic Circuits Use and/or disclosure is
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on page 2 of this chapter
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 lntegrated Training System
r\-.,.,/.^A ;a a.r..-,ei!?r with the
t:l,J?tti()p{*. $*. uk q u*sti*r pr*etiee €;d

Now let's determine the output expression for the NOR gate in figure 5.28. First write the
outputs of gates 1, 2, and 3:
AB GH X+ z
+i+
lrl
gatel gate2 gate

Figure 5.28 - Logic gate combinations.

Since all three outputs are applied to gate 4, proceed as you would for any NOR gate. We
separate each input to gate 4 with an OR sign (+) and then place a vinculum over the entire
expression. The output expression of gate 4 is.

(Ae) +(GH1+(H+Zj

The Truth Table shown below is only for gate 4.

The Truth Table shown below is only for gate 4,

(An1 (GH) (X+Z) f

0 0 0 1

0 0 1 0
0 1 0 0
0 I I 0
1 0 0 0
I 0 I 0
1 I 0 0
1 I I 0
1= 1AB) + (GH) + (X + Z)

When you are trying to determine the outputs of logic gates in combination, take them one gate
at a time!

39 Module 5.5 Logic Circuits Use and/or disclosure is

governed by the statement
TTS lntegrated Training System on page 2 of this chapter
@ Copyright 2010