International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

Area Optimized Design for Data Archival to SD Card

* Konatham Naga Lakshmi 1 P. Bala Nagu 2
1 PG Student (M. Tech), Dept. of ECE, Chirala Engineering College, Chirala, A.P, India.
2 Associate Professor, Dept. of ECE, Chirala Engineering College, Chirala, A.P, India .

Abstract: The main objective of this paper is to present the design of an efficient, real-time
data archival system to a Secure Digital flash memory card via softcore. The data access from
the SD card is implemented completely using Verilog and hence there is no use of any
microcontroller or on-chip general purpose processors. And since the complete design is a
single purpose system, no extra hardware is required. The design has four independent
modules for the required different operations on the SD memory card. These four modules are
for single block write, multiple block write, single block read, and multiple block read
operations. The modeled design can be simulated using Modelsim tool and the intended
functionality can be verified with the help of its simulation results and also it can be
synthesized using the Xilinx tool.
Keywords: SD, SDSC, SDXC, SDHC, Volatile, Non-Volatile, Simulation, Xilinx

1. Introduction families are the original Standard-

Secure Digital (or SD) is a non- Capacity (SDSC), the High-Capacity
volatile memory card format for use in (SDHC), the eXtended-Capacity
portable devices, such as mobile (SDXC), and the SDIO, which
phones, digital cameras, GPS combines input/output functions
navigation devices, and tablet with data storage.234 The three form
computers. The Secure Digital factors are the original size, the "mini"
standard was introduced in 1999 as size, and the "micro" size. There are
an evolutionary improvement over many combinations of form factors
MultiMediaCards (MMC). The Secure and device families.
Digital standard is maintained by the Electrically passive adapters allow
SD Card Association (SDA). SD the use of a smaller card in a host
technologies have been implemented device built to hold a larger card.
in more than 400 brands across Host devices that comply with
dozens of product categories and newer versions of the specification
more than 8,000 models.1 provide backward compatibility and
The Secure Digital format includes accept older SD cards, but there are
four card families available in three several factors that can prevent the
different form factors. The four use of a newer SD card:

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

•A newer card may offer greater High Capacity) and SDXC (Secure
capacity than the host device can Digital eXtended Capacity). These
handle. cards redefine the interface so that
• A newer card may use a file system they cannot be used in older host
the host device cannot navigate. devices.
• Use of an SDIO card requires the host • It defined an SDIO card family that
device be designed for the provides input-output functions and
input/output functions the card may also provide memory functions.
provides. These cards are only fully functional
• The organization of the card was in host devices designed to support
changed starting with theSDHC their input-output functions.
family.
• Some vendors produced SDSC cards
above 1 GB before the SDA had
standardized a method of doing so.
The SDA uses several trademarked
logos to enforce compliance with its
specifications and assure users of
compatibility.
Types of cards
Figure 1 Physical size of a SD card
The SDA has extended the SD
specification in various ways:
• It defined electrically identical cards Size comparison of families: SD

in smaller sizes: miniSD and microSD (blue), miniSD (green), microSD (red)

(originally named TransFlash or TF). The SD card specification defines

Smaller cards are usable in larger three physical sizes. The SD and

slots through use of a passive SDHC families are available in all

adapter. By comparison, Reduced Size three sizes, but the SDXC family is

MultiMediaCards (RS-MMCs) are not available in the mini size, and the

simply shorter MMCs and can be SDIO family is not available in the

used in MMC slots by use of a micro size.

physical extender. Standard size

• It defined higher-capacity cards, some • SD (SDSC), SDHC, SDXC, SDIO

with faster speeds and added • 32.0×24.0×2.1 mm (1.26×0.94×0.083

capabilities: SDHC (Secure Digital in)

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

• 32.0×24.0×1.4 mm (1.26×0.94×0.055 cards.1 However, host devices

in) (as thin as MMC) for Thin SD(rare) designed for SDSC do not recognize
Mini size SDHC or SDXC memory cards,
• miniSD, miniSDHC, miniSDIO although some devices can do so
• 21.5×20.0×1.4 mm (0.85×0.79×0.055 through a firmware upgrade.8 Older
in) operating systems require patches to
Micro size support SDHC. For instance,
The micro form factor is the smallest Microsoft Windows XP before SP3
SD card format.6 requires a patch to support access to
• microSD, microSDHC, microSDXC SDHC cards.9 Windows Vista also
• 15.0×11.0×1.0 mm (0.59×0.43×0.039 requires service pack 2.
in)

Figure 3 Official SDXC logo

Figure 2 SDHC official Logo The Secure Digital eXtended

The Secure Digital High Capacity Capacity (SDXC) format supports

(SDHC) format, defined in Version 2.0 cards up to 2TB (2048 GB), compared

of the SD specification, supports to a limit of 32 GB for SDHC cards in

cards with capacities up to 32 GB.2 the SD 2.0 specification.

The SDHC trademark is licensed to 2. Technical Specifications

ensure compatibility.7 Transfer modes

SDHC cards are physically and Cards may support various

electrically identical to standard- combinations of the following bus

capacity SD cards (SDSC). The major types and transfer modes. The SPI

compatibility issues between SDHC bus mode and one-bit SD bus mode

and SDSC cards are the redefinition are mandatory for all SD families, as

of the Card-Specific Data (CSD) explained in the next section. Once

register in Version 2.0 (see below), the host device and the SD card

and the fact that SDHC cards are negotiate a bus interface mode, the

shipped preformatted with the FAT32 usage of the numbered pins is the

file system. same for all card sizes.

Host devices that accept SDHC • SPI bus mode: Serial Peripheral

cards are required to accept SDSC Interface Bus is primarily used by

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

embedded microcontrollers. This bus

type supports only a 3.3-volt Inside a 512 MB SD card:NAND
interface. flash chip that holds the data
• One-bit SD bus mode: Separate (bottom) and SDcontroller (top)
command and data channels and a
proprietary transfer format.
• Four-bit SD bus mode: Uses extra
pins plus some reassigned pins. UHS-
I and UHS-II requires this bus type.
The physical interface comprises 9
Figure 6 Internal Cross Section 2GB SD
pins, except that the miniSD card
adds two unconnected pins in the Inside a 2 GB SD card: two NAND

center and the microSD card omits flash chips (top and middle), SD

one of the two VSS (Ground) pins. controller chip (bottom)

Figure 7 Inside a 16 GB SDHC card

Command interface
Figure 4 Official Pin out for SD cards SD cards and host devices initially
Official pin numbers for each card communicate through a synchronous
type (top to bottom): MMC, SD, one-bit interface, where the host
miniSD, microSD. This shows the device provides a clock signal that
evolution from the older MMC, on strobes single bits in and out of the
which SD is based. SD card. The host device thereby
Interface sends 48-bit commands and receives
responses. The card can signal that a
response will be delayed, but the host
device can abort the dialogue.

Figure 5 Internal Cross Section 512 MB SD

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

Through issuing various supports it. For various card types,

commands, the host device can: support for the four-bit SD bus is
• Determine the type, memory capacity, either optional or mandatory.41
and capabilities of the SD card After determining that the SD card
• Command the card to use a different supports it, the host device can also
voltage, different clock speed, or command the SD card to switch to a
advanced electrical interface higher transfer speed. Until
• Prepare the card to receive a block to determining the card's capabilities,
write to the flash memory, or read the host device should not use a clock
and reply with the contents of a speed faster than400 kHz. SD cards
specified block. other than SDIO (see below) have a
The command interface is an "Default Speed" clock rate of 25 MHz.
extension of the MultiMediaCard The host device is not required to use
(MMC) interface. SD cards dropped the maximum clock speed that the
support for some of the commands in card supports. It may operate at less
the MMC protocol, but added than the maximum clock speed to
commands related to copy protection. conserve power.41 Between
By using only commands supported commands, the host device can stop
by both standards until determining the clock entirely.
the type of card inserted, a host SDIO cards
device can accommodate both SD and The SDIO family comprises Low-
MMC cards. Speed and Full-Speed cards. Both
Electrical interface types of SDIO cards support SPI and
All SD card families initially use a one-bit SD bus types. Low-Speed
3.3-volt electrical interface. On SDIO cards are allowed to also
command, SDHC and SDXC cards support the four-bit SD bus; Full-
switch to 1.8-volt operation. Speed SDIO cards are required to
At initial power-up or card support the four-bit SD bus. To use a
insertion, the host device selects SDIO card as a "combo card" (for both
either the Serial Peripheral Interface memory and I/O), the host device
(SPI) bus or the one-bit SD bus by the must first select four-bit SD bus
voltage level present on Pin 1. operation. Two other unique features
Thereafter, the host device may issue of Low-Speed SDIO are a maximum
a command to switch to the four-bit clock rate of 400 kHz for all
SD bus interface, if the SD card communications, and the use of Pin 8

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

as "interrupt" to try to initiate command messages to pass to the

dialogue with the host device. SD CMD
3. Architecture design •Read response messages from the SD
CMD Host and forward it to the user
accessible register in the SD
Controller Top module.
•Keep track of the status of the CMD
Host module.
SD CMD Host
This module is the interface

Figure 8 Simplified internal architecture towards physical SD/MMC cards

command pin. This module takes care
SD controller top
of the physical sending and receiving
This module is the interface
of the messages, adding start bits,
between the SDC Core and the bus .
stop bits and CRC checksum.
Two WB interfaces (slave and master)
SD (Bd) Buffer descriptor
are used for this. The internal
The transmission and the
registers and buffer descriptors (BD)
reception processes are based on the
are all accessed through the same
descriptors. Two sequential wrings to
WB Slave Interface. The master
this module is required to create one
interface is used for the internal DMA
buffer descriptor. First the source
to fetch and store data to and from an
address (Memory location) of the data
external memory. The module
is written then the card block address
contains the setting and status
is written.
register accessible by user from the
SD DATA Master
WB slave, and the required logic to
Starts to check if there are any
access this.
new BD thats need to be processed if
SD CMD Master
so the module generate a command
The SD CMD Master module
and set up the DMA to read/write to
synchronize the communication from
correct address. If the command line
the host interface with the physical
is free the module send the command
interface . perform has three main
and wait fore response. If response is
tasks:
valid the module starts the DMA if
•Read a set of register from the user
not valid the CMD is resent again.
accessible register in the SD
Controller Top to compose a 40 bit
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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
During transmission the module
keep track for FIFO buffet underflow
or overflows, when the transmission
is completed it check for valid CRC. If
anything goes wrong during
transmission a stop command is sent
and the module try to restart the
transmission n times before giving up.
SD Data Host
This module is the interface
towards physical SD card device Data
port. The interface consist of only 5
signals, one clock SDCLK, and the 1-
4 bit bi-direction Data signal DAT.
The module perform the following
actions.
• Synchronized request for write and
read data and .
• Adding a CRC-16 checksum on sent
data and check for correct CRC-16 on
received commands.
SD FIFO Tx/Rx Filer
This module works as the DMA it
manager the receive and transceiver
FIFO buffer for the data stream. It
keeps track of the status of the FIFO:s
if somethings goes wrong, like full
receiver FIFO or empty transfer buffer
it signals this.
SD Clock Divider
Divide the input clock with 2 4 6
etc..
SD/MMC Operation
The SD/MMC cards bus includes
the following,a serial data line (DAT0-
ISSN: 2231-5381 http://www.ijettjournal.org
DAT3), one command line (CMD) and
a clock line (CLK). All signals are
operating in push pull mode, all
signals except CLK shall have a pull
a up resistor of a recommended size of
10-100kΏ
Bus protocol
Communication over the SD bus is
based on command and data bit
streams that are initiated by a start
bit and terminated by a stop bit. A
command is used start an operation
in the card, most command gives a
response token as reply.
Command transfer
When the bus is free/idle,
meaning command line is high, an
command transfer can be initiated by
sending a start signal. A start signal,
usually referred to as the S-bit, which
is defined as a high-to-low transition
of the CMD line. The command bit is
sent in a MSB to LSB fashion.
Data transfer
To start a data transmission first a
command request for data has to be
sent to the card. A data then
transmission starts with a S-bit on
DAT0 line. The data is sent in a
lowest byte first, highest byte last
manner, with MSB to LSB manner for
each byte.
Core Operation
Note that the Rx and Tx FIFO is
not intended to be implemented as
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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

RAM-block and therefore require a step. First the command index and
lots of logic if setting to high. If FIFO transmission settings for the
overflow or underflow a option is command to be, sent is written into
instead to lower the clock speed to the the Command setting Register. Next
card or enchant the performance of the commands argument bits of the
the system around to not use the command is be written to the
memory as much leaving more free argument register, which then initiate
bus access cycler to the SD core. the transfer. Upon response bit 0 in
Resetting the core the Normal interrupt status register is
The RST_I signal is used for set to 1 and the response is available
resetting all modules. This can also be in response register. If any of the
done by setting the SRST bit in the requested error check fails will this
Software reset register to 1 . be visible in the Error interrupt status
Setting up the core register.
• Reset the core Buffer descriptors
• Set the timeout register The transmission and the
• Assert Software reset reception processes are based on the
Host Interface Operation descriptors. The Transmit
The host interface connects the IP Descriptors (Tx) are used for
Core to the rest of the system (RISC, transmission while the Receive
memory) via the WISHBONE bus. The Descriptors (RxD) are used for
WISHBONE serves to access the reception. The buffer descriptors are
configuration registers and the 64 bits long. The first 32 bits contain
memory. Currently, only DMA the pointer to the associated buffer
transfers are supported for (where data is stored) while the last
transferring the data from/to the 32 bits contain the card block address
memory. to read or write from. The core has a
Configuration Registers internal ram that can store up to 255
The function of the configuration Tx and Rx BD.
registers is transparent and can be Data block transmission
easily understood by reading the To transmit a block of data, the
Registers section RISC has to perform several steps.
Sending commando First make sure the card is initiated
The sending of a command to the correctly and is ready for data with
SDC/MMC card is performed in two the block size of 512 byte with all 4

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

data bits enabled. If interrupt is used, The no of IOB’s required to test

those associated with the command the functionality is less for this
line should be disabled to not receive proposed SD CARD which is obtained
unnecessary interrupts when the data from the design summary report . The
module use the CMD line. Enabling modeled design can be simulated
interrupts generated by the data using Modelsim tool and the intended
module should instead be activated. functionality can be verified with the
Then it has to check the BD status help of its simulation results and also
register to see if there are any free it can be synthesized using the Xilinx
BD. If so it store what to be sent in tool. Fig 9 & 10 Shows the Simulation
the memory after that it writes the Results of the Designed module & Fig
start address of the stored data to the 11 shows the RTL schemetic.
the TX Buffer descriptor register and
the destination block address.The
core continuously reads the first BD,
where it reads the pointer to the
memory storing the associated data
and starts then reading data to the
Figure 9 SD Controller top module simulation results-1
internal FIFO. At the end of the
transmission, the transmit status is
written to the data interrupt status
register and interrupt might be
generated (when enabled). The next
descriptor is then loaded if more is
qued up, and the process starts all
over again. Figure 10 SD Controller top module simulation results-2

4. Results& Conclusions
A bidirectional core for the SD
card design was implemented in
XILINX ISE. Secure Digital (or SD) is a
non-volatile memory card format for
use in portable devices, such as
mobile phones, digital cameras, GPS
navigation devices, and tablet
computers.

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

ProdManualSDCardv1.9.pdf, accessed
April 2010.
[3] C. Lin and L. Dung. “A NAND Flash
Memory Controller for SD/MMC Flash
Memory Card,” IEEE Transactions on
Magnetics, Vol. 43, 2007.
[4] C. Li, Q. Wang, and L. Wang. “A high
efficient Flash storage System for Two
way Cable Modem,” in Proceedings of
Figure 11 Internal RTL Schematic of SD controller
IEEE International Workshop on
Design Statistics
Computer and Information Technology,
# IOs : 150
pp. 551-556, 2008.
# BELS :1
[5] O. Elkeelany and G. Vince. "Portable
# GND :1
Analog Data Capture Using Custom
# IO Buffers : 77
Processing," in Proceedings of The IEEE
# OBUF : 77
39th Southeastern Symposium on
Total memory usage is 186332
System Theory, pp. 120-123, 2007.
kilobytes
[6] D. Young, C. Zhen-Cheng, and S.
Acknowledgements
Han. “Read/write SD Card based on
The authors would like to thank
Microcontroller MSP430,” Journal of
the anonymous reviewers for their
Biomedical Engineering Research, 2004.
comments which were very helpful in
[7] Y. Ming-Ji, L. Yuan, and S. Ji-Yu.
improving the quality and presentation
“Interface Design between Secured
of this paper.
Digital Card and Single Chip
References:
Microcomputer,” Journal Information
[1] M. Abdallah and O. Elkeelany.
Technology, 2008.
“Simultaneous Multi-channel Data
Authors Profile:
Acquisition and Storing System,” in Konatham Naga Lakshmi
proceedings of International Conference is Pursuing her M. Tech
on Computing, Engineering and from Chirala Engineering
Information ICC‟09, pp.233-236, 2009. College, Chirala in the
[2] SanDisk SD card product manual, department of Electronics & Communications

available: Engineering (ECE) with specialization in

http://www.cs.ucr.edu/~amitra/sdcard/ VLSI & Embedded systems.

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 International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013

P. Bala Nagu is working

as an Associate Professor
in the department of
Electronics &
Communication Engineering in Chirala
Engineering College,Chirala. He has Nine
years of teaching experience along with
one year industrial experience.

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