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 CONTENTS
1. Introduction to DFT
2. Fundamentals of Scan Design
3. Scan Insertion
4. Scan Compression Techniques
5. ATPG Basics
6. Stuck-at ATPG
7. At-speed ATPG
8. ATPG Pattern Simulation
9. ATPG Pattern Failure Analysis & Debugging
10. Q & A and Doubt Clarification
7. AT – SPEED ATPG
Delay faults
➢ Delay fault causes excessive delay along a path such that the total
propagation delay falls outside the specified limit.

➢ delay fault occurs when the time interval taken for a transition from the
gate input to its output exceeds its specified range.

➢ The faults caused by the rise and fall times are called transition delay
faults. Due to this finite time it takes for an input of a gate to show up on
the output, faults may arise if the signals are not given the time to settle.

➢ The other model is path-delay fault, which considers the cumulative

propagation delay along a signal path through the CUT—in other words,
the sum of all gate delays along the path
Transition fault
➢ For detecting a slow-to-rise fault on a line, we take a test for a stuck-at-0
fault on that line. This test will set the line to 1 in the fault-free circuit and
propagate the state of the line to a primary output.

➢ Let us call this vector V2 and precede it with any vector V1 that sets the
line to 0. Now the vector-pair (V1, V2) is a test for the slow-to-rise
transition fault on the line. Note that V1 sets the line to 0 and V2 sets it to
1.

➢ V2 also creates an observation path to a primary output. If the line is

slow to rise then that effect will be observed as a 0 at the output instead
of the expected value of 1.

➢ The basic assumption in this test is that the faulty delay of the signal rise
has to be large,since the observation path may be, and often is, a short
path.
Transition Faults
> Slow-to-rise and Slow-to-fall
▶ 2 methods of Transition fault testing can be done
▶ Launch-Off-Capture (LOC)
▶ Launch-Off-Shift (LOS)
LAUNCH-ON CAPTURE (LOC)

> 2 capture clocks

▶ Launch
▶ Capture
> Capture clocks should be at-speed
LAUNCH-ON SHIFT (LOS)

▶ 2 capture clocks
▶ Launch
▶ Capture
▶ Capture clocks should be at-speed.
▶ SE needs to be closed at-speed.
SCEMATIC DIAGRAM OF LOC
SCEMATIC DIAGRAM OF LOS
Launch-on-Shift Launch-on-Capture
Advantages: Advantages:
→Combinational ATPG →Fewer requirements on the scan
• Higher coverage, fewer pattern, control logic and is easier
faster runtime • Shifting can be done at any speed
• Scan enable doesn’t have to be routed
as a critical clock or pipelined

Disadvantages: Disadvantages:
→ Must disable scan enable quickly → Sequential ATPG (at least 2 system
• Scan enable must be routed as a clock cycles)
timing critical clock • Medium coverage, more patterns and
→ Can create non-functional longer runtime
patterns
• Possible to cause overtest
Fault equivalence
➢ Fault equivalence. Two faults of a Boolean circuit are called equivalent if they
transform the circuit such that the two faulty circuits have identical output
functions. Equivalent faults are also called indistinguishable and have exactly
the same set of tests.

➢ Stuck-at-0 at output of AND gate is equivalent to stuck-at-0 at the input pins.

➢ So, while testing we can remove the 2 stuck-at-0 fault at the input pins, since
these two fault will be tested by equivalent fault stuck-at-0 at the output pin.
Fault collapsing
➢ The set of all faults in a circuit can be partitioned into equivalence sets, such that
faults in an equivalent set are equivalent to each other. The process of selecting
one fault from each equivalence set is called fault collapsing.

➢ The process of selecting one fault from each equivalence set is called fault
collapsing.

➢ The set of selected faults is known as the equivalence collapsed set. The relative
size of the equivalence collapsed set with respect to the set of all faults is the
collapse ratio.

➢ In an alternative form of fault collapsing, known as dominance fault collapsing,

we further eliminate the dominating faults from the equivalence collapsed set.
Fault equivalence : circuit example
Fault dominance
Fault dominance : circuit example
FAULT DETECTION (COMBINATIONAL CIRCUITS)

➢ A test vector t detects a fault f iff Zf(t) /= Z(t)

➢ A fault f is detectable if there exists a test t that detects f
FAULT DETECTION (SEQUENTIALCIRCUITS)
A test sequence T detects a fault f iff, for every pair of initial states q and qf, the
output sequences R(q,T) and Rf(qf,T) are different.
 A TYPICAL ATPG SYSTEM

Given a circuit and a fault model

> Repeat
> Generate a test for each undetected fault
> Drop all other faults detected by the test using a fault simulator
> Until all faults have been considered
> Note 1: a fault may be untestable, in which no test would be generated
> Note 2: an ATPG may abort on a fault if the resources needed exceed a
preset limit
COMBINATIONAL ATPG
Test Generation (TG) Methods
> Exhaustive methods
> Boolean Equation
> Structural Analysis

ATPG Algorithms
> D-algorithm
> 9-Valued D-algorithm
> PODEM
> FAN
> Other advanced techniques
D-Algorithm
Test generation from circuit structure
Two basic goals
(1) Fault activation (FA)
(2) Fault propagation (FP)
Both of which requires Line Justification (LJ), i.e., finding input combinations that force
certain signals to their desired values
Notations:
1/0 is denoted as D, meaning that good-value is 1 while faulty value is 0
Similarly, 0/1 is denoted D’
Both D and D’ are called fault effects (FE)
Fault activation
Setting the faulty signal to either 0 or 1 is a Line Justification problem
Fault propagation
(1) select a path to a PO decisions
(2) Once the path is selected a set of line justification (LJ) problems are
to be solved
Line justification
Involves decisions or implications
Incorrect decisions: need backtracking
 Fault Propagation

Fault activation
G1=0 → { a=1, b=1, c=1 } → { G3=0 }
Fault propagation: through G5 or G6
Decision through G5:
G2=1 → { d=0, a=0 } → inconsistency at a → backtrack !!
Decision through G6:
→G4=1 → e=0 → done !! The resulting test is (111x0)

D-frontiers: are the gates whose output value is x, while one or more Inputs
are D or D’. For example, initially, the D-frontier is { G5, G6 }.
Line Justification
D-Algorithm: Line Justification
corresponding decision tree
a k
b q q=1
c l l=1 k=1
d
m fail r=1
n r s o=1
m=1
o n=1
success
e p
f
h
J-frontier: is the set of gates
whose output value is known
(i.e., 0 or 1), but is not implied
 FA → set h to 0 by its input values.
 FP → e=1, f=1 (→o=0) ; FP → q=1, r=1 Ex: initially, J-frontier is {q=1, r=1}
 To justify q=1 → l=1 or k=1
 Decision: l =1 → c=1, d=1 → m=0, n=0 → r=0 → inconsistency at r → backtrack !
 Decision: k=1 → a=1, b=1
 To justify r=1 → m=1 or n=1 (→c=0 or d=0) → Done ! (J-frontier is )
CLOCK SOURCES

▶ On-chip clocks
▶ Tester must conduct extensive edge searches to align the
application and strobe points associated with each pin to
clock-out signal.
▶ Starting and Stopping clocks
▶ Ex : Wait for pll_lock.
▶ Clock pause for IDDQ test.
▶ Is useful when testing frequency requirements exceed the
tester capability

▶ Bypass clocks.
▶ Ease of application.
▶ May not be suitable when tester frequency cannot meet the design
frequency requirements.
▶ In actual scenarios, a combination of on-chip and bypass clocks is used. It has to
be intelligently and carefully implemented.
▶ Need to test all clock DOMAINS, intra-clock DOMAINS.
ON-CHIP TEST CLK CTRL

ATSPEED_CLK

SHIFT_CLK
C
SCAN_EN L TEST_CLKOUT[0:N]
TEST CLK K
AT_SPEED_MOD
CTRL
G
E A
T
E

CONF_IN CONF_OUT
CONF REGISTER
On-chip Clock Controller

On-chip Clock Controllers (OCC) are also known as Scan Clock Controllers (SCC).
OCC is the logic inserted on the SOC for controlling clocks during silicon testing on
ATE (Automatic test Equipment). Since at-speed testing requires two clock pulses in
capture mode with a frequency equal to the functional clock frequency, without OCC
we need to provide these at-speed pulses through I/O pads. But these pads has
limitation in terms of maximum frequency they can support; OCC on other hand
uses internal PLL clock for generating clock pulses for test. During stuck-at testing,
the OCC ensures only one clock pulse is generated in the capture phase. Similarly,
during at-speed testing, the OCC ensures two clock pulses are generated in the
capture phase, having a frequency equal to frequency of the functional clock.

Therefore all the test clocks in a scan friendly design is routed through an OCC,
which controls the clock operation in scan mode (both in stuck-at and at-speed
testing) and bypasses the functional clock in functional mode.
Schematic of a basic On-chip Clock Controller structure (having a n-bit shift register)
When the circuit is in functional mode (Test Mode = 0), the OCC bypasses the functional
clock (Refer Figure 1). But during the shift phase (Shift Enable = 1), the Scan Clock is
propagated at the output of OCC. In capture phase (Shift Enable = 0), the shift register
starts shifting ‘1’ and enables the Clock Gate, to allow single pulse or double pulse,
depending on the type of testing. The OCC generates one clock pulse in stuck-at testing
(At-speed Mode = 0) and two clock pulses in at-speed testing (At-speed Mode = 1).

The behavior of this OCC (having a 5-bit shift register) in at-speed testing is shown in
Figure 2. The two capture pulses came after 5 positive edges of the functional clock (as
we are using a 5-bit shift register).

NOTE: Once the Shift Enable is asserted Low, the n-bit shift register decides the delay in
terms of the number of positive edges of the functional clock, after which the functional
clock is propagated at the output of the OCC.
THANK YOU