Lap Top Repair Book Chapter 1 The Architecture of Laptop Motherboard

Chapter Three
The architecture of laptop

motherboard
Now,the chipset used by the mainstream laptop on the market is only two
manufacturer,the Intel and AMD,Intel is the absolute dominance.Once the most popular
nVIDIA has quit the chipset industry in 2010,on the market,the notebook computer products
with nVIDIA chipset are few.
The architecture of Intel double bridge(GM/PM45 and

below)
The Intel double bridge architecture,including the 855-GM/PM45 chipset.
In the Intel double bridge architecture,CPU and the North Bridge are connected through the
FSB(front side bus),the North Bridge also control memory、PCI-E 16X discrete graphics card and
display output interface.
The bus connected by the North Bridge and South Bridge is called HUBLINK,and renamed
the DMI(Direct Media Interface) later,so the transmission speed increased much faster.
The South Bridge main control peripheral extension interface,mainly in the following.
USB:Devices on the USB line are USB interface、camera、Bluetooth,etc.
Audio card:MODEM and the audio card are on the same line.
SATA:Hard disk and CD-ROM.
IDE:(Early)hard disk and CD-ROM.
PCI-E device:Network card、card reader、expansion card、mini PCI-E slot,etc.
EC:The name of the line connected to the South Bridge is LPC(Low Pin Count,means one of
the bus with a small number of pin-out).The devices controlled by EC are
keyboard、touchpad、BIOS(part of the motherboard BIOS and EC may work by the same LPC
bus,or connected the South Bridge directly via SPI bus),etc.
The architecture of Intel GM45 as shown in figure 3-1.
The architecture of Intel single bridge(above HM55)

After Intel 5 series chipset development,it becomes the bridge,called PCH,that is to say the
North Bridge integrated into CPU.In the architecture of single bridge,CPU main control memory
and PCI-E 16X discrete graphics card,the integrated graphics is also integrated within CPU.
笔记本电脑维修不是事儿
The bus that CPU and PCH bridge connected to are FDI(Flexible Display Interface) and DMI
bus.
PCH control USB、PCI-E 1X、SATA、audio card and other peripheral device.
The connection of PCH and EC is still using LPC bus,devices under EC remain unchanged.
It was nothing that in the architecture of Intel single bridge,although CPU integrated the
graphics card,but the display signal output is not usually output by itself,and after transmitted to
PCH through FDI bus,then completed output by PCH.It’s different from the next AMD single
architecture.
The architecture of Intel HM75 chipset as shown in figure 3-2.
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第 3 章笔记本电脑主板的架构
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The architecture of AMD double bridge(RS780)
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Because the AMD chipset uses AMD 638-pin CPU,so CPU can manage memory directly.
The North Bridge manage all PCI-E device,it’s difference from Intel double bridge,please
remember.The North Bridge also integrated the graphics card,and is responsible to output display
signal.
The South Bridge manage audio card、USB、SATA、EC,etc,and devices under EC remain
unchanged.
Here to mention,the BIOS has a variety of work bus,some work through X-BUS under
EC,some work through LPC bus connected in parallel with EC,and some work through SPI bus
connected South Bridge independently,this is not much associated with the architecture actually.
The architecture of AMD RS780 as shown in figure 3-3.
The architecture of AMD single bridge(A70)

After AMD chipset A45(mobile version is A50) development,it changed to the single
bridge,called FCH.There are a lot of similarities with Intel single bridge,the bridge and devices
managed by EC are almost the same,so no longer elaborated.The CPU of AMD also integrated the
graphics card,called APU,but it can output the display signal directly,and it’s difference with the
architecture of Intel single bridge.
The architecture of AMD A70 chipset as shown in figure 3-4.
The architecture of nVIDIA double bridge(C51M)

nVIDIA is very famous for graphics card and chipset,but they didn’t product PC chipset
anymore.In the desktop computer,there are many single bridge chipset and double bridge
chipset;but in the laptop,there are many double bridge.
In the architecture of nVIDIA double bridge,CPU uses AMD 638,can manage memory
directly.The North Bridge is responsible to manage all PCI-E device and output the display signal
on integrated graphics card,it’s in accordance with AMD double bridge architecture.Devices
managed by South Bridge and EC are not big difference with AMD double bridge.
The architecture of nVIDIA C51M chipset as shown in figure 3-5.
The architecture of nVIDIA single bridge(MCP67)

In the architecture of nVIDIA single bridge,the memory managed by CPU,and the other is
managed by the Bridge,the large heat release of the bridge,it’s easy to weld.
The architecture of nVIDIA MCP67 chipset as shown in figure 3-6.
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Chapter Four
The common concepts of laptop and noun explanation
About laptop motherboard maintenance,often involving some professional terminologies of
the circuit and signal.To understand the schematic circuit diagram and learn to repair well,we must
understand these concepts first.
4.1 Power supply and signal

On the motherboard,some places have 5V voltage,we called 5V power supply,and some places also have 5V
voltage,we called signal,then what’s the difference between them?
1.Power supply
Power supply is an output current of the voltage,and current is large.During working,the voltage can not be set
higher or lower.If the power supply is low,it’s short circuit.In general,set high is not allowed.
The power supply is providing the power to the device,it’s name is
VCC、VDD、VCC3、VDDQ、VTT、VBAT、5VALW、+3VO,etc.
The circuit symbol of power supply is shown in figure 4-1.
In the circuit diagram of Apple products,the power supply is generally beginning with PP and
haven’t other special symbols,as shown in 4-2.
Figure 4-2 The power supply symbol of Apple products
Grounding is to form a loop for power supply.Without Ground(GND),no current will flow
through the device.The name is VSS、GND.
The circuit symbol of Ground(GND) is shown in figure 4-3.
2.Signal
In theory,the voltage signal only considers the voltage change and current is low.In the working process of
the motherboard,it can be set higher or lower at any time according to the needs.The arrow of signal in the circuit
diagram,because of the randomness of the people draw the circuit diagram,is not represent the flow of signal
completely.
The circuit diagram of signal is shown in figure 4-4.
4.2 High level and low level

In the digital logic circuit,the low level is represented by 0,and the high level is represented
by 1.The high and low level in the circuit needs to be decided by the circuit,not to be limited to a
certain value.But in general,0V is low level and 3.3 is high level.
4.3 Jump and pulse

From high level to jump to a low level,also called the falling edge,as shown in figure 4-5.
From low level to jump to a high level,also called rising,as shown in figure 4-6.
From high jump to low then jump to high,also called high-low-high pulse,as shown in figure 4-7.
Figure 4-5 The falling edge waveform
Figure 4-6 The rising edge waveform
Figure 4-7 The high-low-high pulse waveform
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第 4 章笔记本电脑维修常用概念及名词解释
4.4 The clock signal

The clock signal CLK(CLOCK),is to provide a benchmark for the digital circuit work,so that each connected
device unified work pace.The basic unit of the clock is Hz(hertz).There is a main clock generating circuit on the
main board,the function of this circuit is to provide the clock for all devices on the main board,for different
device,the clock circuit will send different frequency,such as to the frequency of CPU is more than 100MHz,to PCI
device is 33MHz,to PCI-E device is 100MHz,to USB controller(integrated in the South Bridge internal)is
48MHz.But the two connected devices must have the same clock frequency and voltage to communicate.For
example,memory and North Bridge need the same clock and voltage to transmit signal normally.After main board
powering on normally and the clock chip working normally,then the clock signal can be measured.We can use the
oscilloscope or multimeter to measure the clock signal.
The clock signal of clock chip benchmark-14MHz is shown in figure 4-8.
4.5 Reset signal

The literal meaning of reset signal RST is the new signal.Just starting,it will reset automatically,and jump from low
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level to high level;during normal operation,press the reset button,from the high level to jump to the low level then
to the high level.For example,for PCI,from 3.3V to jump to 0V,then to 3V,which is a normal reset jump.Reset
signal is generally expressed as ***RST#,such as PCIRST#、CPURST#、IDERST# and so on.
In short,the reset can only be momentary low level,but when the main board works normally,the reset is high
level.We said not reset usually,refers to no reset voltage,that is the measurement point voltage of the reset signal is
0V.
3.3V platform reset from the South Bridge,after dividing into 1.1 v as the CPU reset,shown in figure 4-9.
Figure 4-9 the circuit of the CPU reset.
4.6 The power good signal

The power good signal PG(POWERGOOD) is used to describe the normal power supply,is usually active high.For
example,after sending the CPU voltage normally,then the CPU power supply chip can send PG signal.The common
abbreviations of PG signal are PD、PWRGD、POK、PWRG、VTTPWRGD,CPUPWRGD,etc.
After RT8205 working normally,then send SPOK,is shown in figure 4-10.
Figure 4-10 PG signal diagram.
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4.7 The open signal

Some chip called EN(ENABLE),the high level represents the open signal;and some chip
called SHDN#,namely SHUTDOWN,“#”represents active-low level.Then,it means that signal
is closed when it’s low level;to open,it must be high level.
We need to emphasize that we must be combined to full name in English of signal to
understand signal with “#”(when active-low level),some signal with “#”,when it’s low level,the
main board can work normally.For example,signal VR-PWRGD-CK410# in figure 4-11,sending
the low level to open the clock chip after power supply is normal.
But some signal with “#”,the main board working normally must be high.For example,1999-
SHDN# shown in figure 4-12 is the low level control signal for closing MAX1999.
Figure 4-11 the screenshot of VR-PWRGD-CK410# signal
Figure 4-12 the screenshot of 1999-SHDN# signal
Timing is through EN、PG and other signals to achieve control.
4.8 Chip select signal

CS is the Chip Select.Many of chip on the same bus,then need a signal to distinguish data and address on bus
managed by which chip,so we need a chip select signal.Chip select signal is common in BIOS chip,English name is
CS#,and “#”represents active-low level.It’s sent by CPU,from the North Bridge to the South Bridge,and finally to
the BIOS.It exists or not,which can initially judge whether the North and South Bridge and CPU to work,and
whether BIOS information is destroyed..SPI BIOS pin shown in figure 4-13,and 1 pin CS# is the BIOS chip select
signal.
Figure 4-13 the chart of SPI BIOS pin
4.9 Explanation of common signal name about
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some manufacturers.
Each manufacturer is different in the name of signal,some common types and signal name in
the following list.It should be noted that not all signal names are the same for each manufacturer,it
must be careful to distinguish when we read the circuit diagram.
Some of common signal names about Wistron shown in table 4-1.
Table 4-1 the list of some common signal names about Wistron
AD+ the first voltage that the adapter converts
DCBATOUT common point
+3VL 3.3V linear power supply,to supply power to EC
DCIN power supply input for charging chip
ACIN adapter detection input for charging chip
ACAV-IN adapter detection output for charging chip
PWR-S5-EN a control signal used to open standby voltage of South Bridge
+5VALM、+3VALM the standby power supply of South Bridge
AD-IN#、AC-IN# the adapter detection signal to EC,the low level represents that the adapter is inserted.
KBC-PWR-BTN# press the switch to produce the trigger signal to EC
LID-CLOSE# close cover switch
CLK-EN# after CPU power supply being normal,sent the low level that can be used to open the clock.
G792-RST# the high level sent by the temperature control chip when the temperature is normal
CK-PWRGD after the South Bridge receiving VRMPWRGD,sent the high level for opening the clock.
信号名称 Signal Name 解释 Explanation

AD+ 适配器转换出来的第一个电压
DCBATOUT 公共点
+3VL 3.3V 线性供电，给 EC 供电
DCIN 充电芯片的供电输入
ACIN 充电芯片的适配器检测输入
ACAV_IN 充电芯片的适配器检测输出
PWR_S5_EN 用于开启南桥待机电压的控制信号
+5VALW、+3VALW 南桥待机供电
AD_IN#、AC_IN# 送给 EC 的适配器检测信号，低电平表示适配器已插入
KBC_PWR_BTN# 按下开关产生的送给 EC 的触发信号
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LID_CLOSE# 合盖开关
CLK_EN# CPU 供电正常后，发出的低电平，可用于开启时钟
G792_RST# 温控芯片检测温度正常时发出的高电平
CK_PWRGD 南桥收到 VRMPWRGD 后，发出的高电平，用于开启时钟
Some of common signal names about Quanta shown in table 4-2

Table 4-2 the list of some common signal names about Quanta
VIN the common point voltage
ACIN、ACOK adapter detection
3V-AL、5V-AL、VL 3V、5V linear power supply
+3VPCU、+5VPCU EC standby power supply
3V-S5 the voltage under the condition of S5,the South Bridge power supply,,opened by EC after trigger switch.
+3VSUS、+5VSUS the voltage under the condition of S3,memory power supply,sent by EC and opened by
SUSON
NBSWON# power on the trigger signal,press the power key to produce high-low-high signal to EC.
DNBSWON# EC sent high-low-high effective trigger signal to the South Bridge PWRBTN#
SLP-S4#、SLP-S3# ACPI controller signal sent by the South Bridge is used to opening voltage when the power
is turned on,and used to shutting off when the power is turned off
S5-ON the opening signal of the South Bridge standby voltage sent by EC,its role is to convert PCU to voltage
S5.
SUSON after EC receiving SLP-S5# from the South Bridge,then producing S3 voltage opening signal.
MAINON after EC receiving SLP-S3# from the South Bridge,then producing S0 voltage opening signal.
VR-ON the CPU core voltage opening signal sent by EC.
HWPG by the PG logic and all power supply except the CPU core power supply.
PWROK-EC after EC received high level HWPG signal,delay producing PWROK-EC signal.
DELAY-VR-PWG CPU core voltage power-good signal
VR-PWRGD-CK410# CPU core voltage power managed the clock open signal from chip,low level.
CK-PWRGD the South Bridge sent CK-PWRGD open clock chip after receiving VRMPWRGD.
CPUPWRGD in the South Bridge internal,PWROK pin and VRMPWRGD pin signal through the logic generated
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CPUPWRGD.
PLTRST# the platform reset,after the South Bridge sending CPUPWRGD signal,delay buffer sent PLTRST#
PCIRST# the PCI reset,used for resetting the device on the PCI bus when powered on,making the device work
from an initial state.
CPURST# CPU reset signal,the North Bridge sent CPURST# to CPU after received PLTRST#
BL/C# represents high level,low battery (only for battery model)
D/C# inverse relationship with ACIN(for only D/C#,main board without BL/C#)

VIN 公共点电压
ACIN、ACOK 适配器检测
3V_AL、5V_AL、VL 3V、5V 线性供电
+3VPCU、+5VPCU EC 的待机供电
续表
信号名称解释
3V_S5 S5 状态下的电压，南桥待机供电，触发开关后，由 EC 开启
+3VSUS、+5VSUS S3 状态下的电压，内存供电，由 EC 发出 SUSON 开启
NBSWON# 电源开机触发信号，按下电源开关键产生高-低-高的信号至 EC
DNBSWON# EC 发出的高-低-高有效触发信号至南桥的 PWRBTN#
SLP_S4#、SLP_S3# 南桥发出的 ACPI 控制器信号，开机时用于电压开启，关机时用于电压关闭
S5_ON EC 发出的南桥待机电压开启信号，其作用是将 PCU 转换 S5 电压
SUSON EC 接收到南桥发来的 SLP_S5#后产生的 S3 电压开启信号
MAINON EC 接收到南桥发来的 SLP_S3#后产生的 S0 电压开启信号
VR_ON EC 发出的 CPU 核心电压开启信号
HWPG 由除 CPU 核心供电以外的所有供电的 PG 逻辑相与而来
PWROK_EC EC 收到高电平 HWPG 信号后，延时产生 PWROK_EC 信号
DELAY_VR_PWG CPU 核心电压电源好信号
VR_PWRGD_CK410# CPU 核心电压电源管理芯片发出的时钟开启信号，低电平
CK_PWRGD 南桥收到 VRMPWRGD 后，发出 CK_PWRGD 开启时钟芯片
CPUPWRGD 在南桥内部 PWROK 脚位及 VRMPWRGD 脚位两信号经过与逻辑产生 CPUPWRGD
PLTRST# 平台复位，南桥在发出 CPUPWRGD 信号之后，经过延时缓冲发出 PLTRST#
PCIRST# PCI 复位，用于上电时复位 PCI 总线上的设备，使设备从初始状态开始工作
CPURST# CPU 复位信号，北桥接收 PLTRST#后发出 CPURST#给 CPU
BL/C# 高电平表示，电池电量低（仅用于电池模式）
D/C# 与 ACIN 成相反的关系（适用于仅有 D/C#，没有 BL/C#的主板）
ASUS
Some of common signal names about ASUS shown in figure 4-3
Figure 4-3 the list of some common signal names about ASUS
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AC-BAT-SYS the common point voltage
ACIN adapter detection
+5VAO 5V linear voltage
+3VAO 3V linear voltage
+5VA +5VAO renamed +5VA after jumper
+3VA +3VAO renamed +3VA after jumper JP8101
+3VA-EC +3VA renamed +3VA-EC after through the inductance,as the power supply of EC standby
+5VO 5V standby voltage in S5 dormant state
+3VO 3V standby voltage in S5 dormant state
+5VSUS +5VO renamed +5VSUS after jumper
+3VSUS +3VO renamed +3VSUS after jumper
VSUS-ON SUS voltage open signal
SUS-PWRGD SUS voltage power-good signal,to EC
PM-RSMRST# the reset signal of the South Bridge ACPI controller,can be understood that the South Bridge
standby voltage is normal
PWRSW-EC# boot trigger signal
PM-PWRBTN# after receiving PWRSW-EC,EC sent PM-PWRBTN# effective trigger to the South Bridge
PWRBTN# pin
SUSC-ON、SUSC#-PWR S3 voltage open signal
SUSB-ON、SUSB#-PWR S0 voltage open signal
ALL-SYSTEM-PWRGD generated by memory power supply、bridge power supply、bus power
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supply、graphics card power supply and PG signal logic
CPU-VRON EC delayed 99ms to send VR-ON after sending SUSB-ON,for opening CPU core voltage
EC-CLK-EN EC sent VRMPWRGD to the South Bridge pin,inform the South Bridge that CPU core voltage is
normal
CLK-PWRGD the South Bridge generated CLK-PWRGD to IC clock after receiving VRMPWRGD,for
opening the clock signal
PM-PWROK after receiving ALL-SYSTEM-PWRGD,EC delayed sending PW-PWROK
H-CPURST# the North Bridge sent H-CPURST# to CPU after receiving PLTRST# signal
GATE-PWR-SW# the boot trigger signal
LID-SW# close-lid sleep switch signal,when the machine is closed,the signal is low level
LID-KBC# the close-lid sleep switch detection signal for EC
KBCRSM the keyboard wake-up signal
FORCE-OFF# the forced shutdown signal,generated by the undervoltage protection circuit
HW-PROTECT# CPU overtemperature protection signal
OTP-RESET# CPU overtemeprature indication signal

AC_BAT_SYS 公共点电压
ACIN 适配器检测
+5VAO 5V 线性电压
+3VAO 3V 线性电压
+5VA +5VAO 过跳线后更名为+5VA
+3VA +3VAO 过跳线 JP8101 后更名为+3VA
+3VA_EC +3VA 过电感后更名为+3VA_EC，作为 EC 待机时的供电
+5VO S5 休眠状态下的 5V 待机电压
+3VO S5 休眠状态下的 3V 待机电压
+5VSUS +5VO 过跳线后更名为+5VSUS
+3VSUS +3VO 过跳线后更名为+3VSUS
VSUS_ON SUS 电压开启信号
SUS_PWRGD SUS 电压电源好信号，发给 EC 的
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PM_RSMRST# 南桥的 ACPI 控制器的复位信号，可以理解为南桥待机电压正常

PWRSW_EC# 开机触发信号
PM_PWRBTN# EC 接收到 PWRSW_EC#后发出 PM_PWRBTN#有效触发至南桥的PWRBTN#脚位
续表
信号名称解释
SUSC_ON、SUSC#_PWR S3 电压开启信号
SUSB_ON、SUSB#_PWR S0 电压开启信号
ALL_SYSTEM_PWRGD 由内存供电、桥供电、总线供电、显卡供电等 PG 信号逻辑相与产生
CPU_VRON EC 发出 SUSB_ON 后延时 99ms 发出 VR_ON，用于开启 CPU 核心电压
EC_CLK_EN EC 发出至南桥的 VRMPWRGD 脚位，告知南桥 CPU 核心电压已正常
CLK_PWRGD 南桥收到 VRMPWRGD 后产生 CLK_PWRGD 至时钟 IC，用于开启时钟信号
PM_PWROK EC 收到 ALL_SYSTEM_PWRGD 后，延时发出 PM_PWROK 信号
H_CPURST# 北桥收到 PLTRST#信号后发出 H_CPURST#至 CPU
GATE_PWR_SW# 开机触发信号
LID_SW# 合盖休眠开关信号，当机器合盖时，此信号为低电平
LID_KBC# 发给 EC 的合盖休眠开关检测信号
KBCRSM 键盘唤醒信号
FORCE_OFF# 强制关机信号，由欠压保护电路产生
HW_PROTECT# CPU 过温保护信号
OTP_RESET# CPU 过温指示信号
Compal
Some of common signal names about Compal shown in figure 4-4
Figure 4-4 the list of some common signal names about Compal
B+ comkon point voltage
PACIN the detection output signal is inserted to the adapter,and the high level represents that the adapter is
inserted
VL 5V linear power supply
+3VALW、+5VALW inserting the adapter,that is the opened voltage
ON/OFFBTN# power on key signal
ON/OFF# the trigger signalsent by boot trigger circuit to EC
PBTNOUT# the boot trigger signal sent by EC to the South Bridge
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SYSON S3 voltage open signal
SUSP# S0 voltage open signal
+VCCP the working voltage of CPU front side bus,this voltage distributes in CPU、the North Bridge、the South
Bridge
+CPU-CORE CPU core voltage
VGATE CPU core voltage power-good signal
ICH-POK PWROS for the South Bridge,inform the South Bridge system voltage power good
BCLK the front side bus clock signal
SUS-STAT# sent by the Soth Bridge,the low level indicates that the system will be power-down mode

B+ 公共点电压
PACIN 适配器插入检测输出信号，高电平表示适配器插入
VL 5V 线性供电
+3VALW、+5VALW 插入适配器即开启的电压
ON/OFFBTN# 电源开机键信号
ON/OFF# 开机触发电路转发给 EC 的触发信号
PBTNOUT# EC 发给南桥的开机触发信号
SYSON S3 电压开启信号
SUSP# S0 电压开启信号
+VCCP CPU 前端总线工作电压，此电压分布于 CPU、北桥、南桥
+CPU_CORE CPU 核心电压
VGATE CPU 核心电压电源好信号
ICH_POK 给南桥的 PWROK，告知南桥系统电压电源好
BCLK 前端总线时钟信号
SUS_STAT# 由南桥发出，低电平表明系统将要进入省电状态
4.9.5 DELL
DELL
Some of common signal names about DELL shown in figure 4-5
Figure the list of some common signal names about DELL
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RTC-CELL the motehrboard button battery voltage
+DC-IN power adapter voltage input
+PWR-SRC the common point voltage
ALWON EC sent a ALWON signal to the system power supply chip,to open the system power supply
THERM-STP# overheat protection signal,active-low level
ACAV-IN the adapter detection signal
POWER-SW# a low voltage signal generated by the power switch or keyboard,and EC chip receives this boot
signal
SUS-ON after receiving the trigger signal,EC sent SUS-ON to used to open the South Bridge standby power
supply and memory main power supply
RUN-ON EC sent open S0 state voltage
GFX-ON open discerte graphics card power supply
+VCC-GFX-CORE thediscrete graphics card core power supply
+0.9V-DDR-VTTP memory VTT power supply
RUNPWROK the PGD signal of all RUN power converges this signal
SUSPWROK the reset signal of all SUS power brings together to generate the SUSPWROK signal
+VCCP-1P05VP the front side bus power supply,1.05V
PGD-IN one of the conditions of that CPU power supply chip sent CLK-EN#、PGOOD and others.
CLK-ENABLE# the open signal of clock chip,active-low level
H-PWRGOOD PGD reset signal sent by the South Bridge to CPU
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H-RESET# the North Bridge sent CPU reset signal
+VCHGR charging output voltage
+SBATT Auxiliary battery power supply terminal
+PBATT main batter power supply terminal
SBAT-PRES# insert the auxiliary battery to detection
PBAT-PRES# insert the main battery to detection
IMVP-VR-ON open CPU power supply
IMVP-PWRGD power supply good signal sent by CPU power supply chip

RTC_CELL 主板纽扣电池电压
+DC_IN 电源适配器电压输入
+PWR_SRC 公共点电压
ALWON EC 向系统供电芯片发出一个 ALWON 信号，打开系统供电
THERM_STP﹟ 过热保护信号，低电平有效
ACAV_IN 适配器检测信号
POWER_SW# 电源开关或键盘产生的一个低电压信号，EC 芯片接收此开机信号
SUS_ON EC 收到触发信号后，发出 SUS_ON 用于开启南桥待机供电和内存主供电
RUN_ON EC 发出开启 S0 状态电压
GFX_ON 开启独立显卡供电
+VCC_GFX_CORE 独立显卡核心供电
+0.9V_DDR_VTTP 内存 VTT 供电
RUNPWROK 所有 RUN 电源的 PGD 信号汇聚成此信号
SUSPWROK 所有 SUS 电源的复位信号汇聚到一起产生 SUSPWROK 信号
+VCCP_1P05VP 前端总线供电，1.05V
PGD_IN CPU 供电芯片发出 CLK_EN#、PGOOD 等的条件之一
CLK_ENABLE# 时钟芯片的开启信号，低电平有效
H_PWRGOOD 南桥向 CPU 发出的 PGD 复位信号
H_RESET# 北桥发出 CPU 复位信号
+VCHGR 充电输出电压
+SBATT 副电池供电端
+PBATT 主电池供电端
SBAT_PRES# 副电池插入检测
PBAT_PRES# 主电池插入检测
IMVP_VR_ON 开启 CPU 供电
IMVP_PWRGD CPU 供电芯片发出的供电好信号
32
APPLE
Some of common signal names about APPLE shown in figure 4-6
Figure 4-6 the list of some signal names about APPLE
=PP3V42-G3H-REG 3.42V power supply in the condition of G3 equivalent to the linear power supply of other
machines.
=PP3V-S5-REG 3.3V power supply in the condition of S5 provided the standby voltage to the South Bridge and
others
PP3V3-G3-SB-RTC 3.3V power supply of the South Bridge RTC circuit
=PPBUSA-G3H common point voltage
PM-BATLOW-L the indicator signal of low battery voltage,active-low level
1V8S3-RUNSS S3 state voltage(memory supply) of 1.8V open signal
ALL-SYS-PWRGD from all power supply good signal except CPU power supply converge
VR-PWRGDOOG-DELAY the power-good,sent by CPU power supply after generating CPU voltage
normally,delay to sent the power-good
VR-PWRGD-CK505-L the low level signal of open clock,sent by CPU power supply chip after generating CPU
voltage normally,sent the low level signal of open clock
SMC-BC-ACOK the adapter detection signal,active-high level
SMC-ADAPTER-EN the high level signal,output by SMC after receiving the adapter detection signal
SMC-BATT-CHG-EN the charging enable signal,sent by SMC,active-high level
SMC-BATT-TRICKLE-EN-L the trickle charging signal,sent by SMC,active-low level
ACPRN low level ACPRN sent by charging chip after the adapter is detected
33
ONEWIRE-EN ONEWIRE enable signal,for the adapter to identify circuit(the head of power is green)

=PP3V42_G3H_REG G3 状态下的 3.42V 供电，相当于其他机器的线性供电
=PP3V3_S5_REG S5 状态下的 3.3V 供电，给南桥等提供待机电压
PP3V3_G3_SB_RTC 南桥的 RTC 电路的 3.3V 供电
=PPBUSA_G3H 公共点电压
PM_BATLOW_L 电池电压低指示信号，低电平有效
1V8S3_RUNSS 1.8V 的 S3 状态电压（内存供电）开启信号
ALL_SYS_PWRGD 除 CPU 供电以外的所有供电好信号相与而来
VR_PWRGOOD_DELAY CPU 供电芯片正常产生 CPU 电压后，延时发出的电源好
VR_PWRGD_CK505_L CPU 供电芯片正常产生 CPU 电压后，发出开启时钟的低电平信号
续表
信号名称解释
SMC_BC_ACOK 适配器检测信号，高电平有效
SMC_ADAPTER_EN SMC 收到适配器检测信号后，输出的高电平信号
SMC_BATT_CHG_EN SMC 发出的充电使能信号，高电平有效
SMC_BATT_TRICKLE_EN_L SMC 发出的涓流充电信号，低电平有效
ACPRN 充电芯片检测到适配器后发出的低电平 ACPRN
ONEWIRE_EN ONEWIRE 使能信号，用于适配器识别电路（电源头亮绿灯）
INVENTEC
Some of common signal names about INVENTEC shown in figure 4-7
Figure 4-7 the list of some common signal names about INVENTEC
+VADP adapter interface voltage
ADP-EN# adapter enable,active-low
ADP-PRES adapter detection output,it can be used to open the system power supply directly
+VBATR common point voltage
+V3AL、+V5AL linear power supply
PWR-SWIN-3# the signal sent by trigger switch to EC
KBC-PW-ON the power signal,is sent by EC after EC receiving trigger switch,is used to open the system
standby power supply under the battery mode
VCCI-POR#3 the initial reset signal of EC
34
+V3A、+V5A standby power supply system
LIMIT-SIGNAL the adapter intermediate pin,power identification signal
OCP over-current protection

+VADP 适配器接口电压
ADP_EN# 适配器使能，低电平有效
ADP_PRES 适配器检测输出，可用于直接开启系统供电
+VBATR 公共点电压
+V3AL、+V5AL 线性供电
PWR_SWIN_3# 触发开关送给 EC 的信号
KBC_PW_ON EC 收到开关触发后发出的开机信号，电池模式下用于开启系统待机供电
VCC1_POR#_3 EC 的最初的复位信号
+V3A、+V5A 系统待机供电
LIMIT_SIGNAL 适配器中间针，功率识别信号
OCP 过流保护
4.9.8 ThinkPad（IBM）
ThinkPad(IBM)
Some of common signal names about ThinkPad(IBM) shown in figure 4-8
Figure 4-8 the list of some common signal names about ThinkPad(IBM)
DOCK-PWR20-F the adapter voltage
CV20 the voltage between adapter and common point
VINT20 the common point
DISCHARGE forced to close adapter,battery discharge signal
-PWRSHUTDOWN over-temperature and under-voltage protection signal,used to isolate the adapter
VCC3SW 3.3V voltage,output by TB chip,pull-up -PWRSHUTDOWN,to supply power to the Lenovo chip
-EXTPWR the adapter detection signal,output by the charging chip,active-low level
-EXTPWR-ASIC the adapter detection input signal of the Lenovo chip
35
-EXTPWR-H8 the adapter detection input signal of H8S
VL5 the 5V linear voltage,generated by the standby chip
DCIN-DRV the spacer tube,used to control adapter,turned-on the adapter spacer tube fully at high level
BAT-DRV the spacer tube,used to control the battery,isolated the battery in a high level
M1-ON the high level signal of standby voltage sent by Lenovo chip for opening the South Bridge
VCC5M 5V standby voltage of the South Bridge
VCC3M 3.3V standby voltage of the South Bridge,is also the power supply of H8S
TH-DET N thermistors connected in series,detect temperature.When the temperature is normal,this pin is lower
than 0.5V
ACDET the adapter of the charging chip detects input pin
SWPWRG the standby voltage good of the Lenovo chip
VREGIN20 the voltage with a small current generated after the adapter or battery accessing to,for the power
supply of TB chip.
BAT-VOLT VREGIN20 voltage detection pin,the threshold is 2.9V
MPWRG TB chip detects VCC3M、VCC5M are normal,sent PG,RSMRST# to the South Bridge
-H8-RESET the reset sent by Lenovo chip to H8S
VDD15 TB chip detects M voltage is normal,bootstrap boost 15V.To provide power to xx-DRV of TB chip
output
VCPIN28 TB chip detects M voltage is normal,bootstrap boost 28V(is 25V in fact),N channel field-effect tube
for driving and protecting the isolating circuit
A-ON A voltage is turned on(S3 voltage,such as memory power supply)
36
B-ON B voltage is turned on(S0 voltage,such as the bus power supply)
B-DRV B voltage drive signal,sent by TB chip
BPWRG power-good,sent by TB chip after detecting VCC3B、CVCC5B normal
AMT-ON ME module voltage is turned on
SLP-M# sent by the South Bridge,used to control the opening of AMT power supply
AMTPWRG AMT power-good
-PWRSWITCH、-PWRSW power switch signal
BATMON-EN battery voltage monitoring open
M-BATVOLT main battery voltage feedback
M1-DRV、M2-DRV main battery charging and discharging driving signal
BAT-CRG battery large current charge control switch
CHARGE-OUT12 12.6V charging voltage,control output by charging chip
M-TRCL the main battery trickle charging control switch
S-TRCL the auxiliary battery trickle charging control switch

DOCK_PWR20_F 适配器电压
CV20 适配器与公共点之间的一个电压
VINT20 公共点
DISCHARGE 强制关闭适配器，电池放电信号
-PWRSHUTDOWN 过温、欠压保护信号，用于隔离适配器
VCC3SW TB 芯片输出的 3.3V 电压，上拉-PWRSHUTDOWN，给联想芯片供电
-EXTPWR 充电芯片输出的适配器检测信号，低电平有效
-EXTPWR_ASIC 联想芯片的适配器检测输入信号
-EXTPWR_H8 H8S 的适配器检测输入信号
VL5 待机芯片产生的 5V 线性电压
DCIN_DRV 用于控制适配器的隔离管，高电平时完全导通适配器隔离管
续表
信号名称解释
BAT_DRV 用于控制电池的隔离管，低电平时隔离电池
37
M1_ON 联想芯片发出的开启南桥的待机电压的高电平信号
VCC5M 南桥的 5V 待机电压
VCC3M 南桥的 3.3V 待机电压，同时也是 H8S 的供电
TH_DET 串联 N 个热敏电阻，检测温度。温度正常时，此脚低于 0.5V
ACDET 充电芯片的适配器检测输入脚
SWPWRG 联想芯片的待机电压好
VREGIN20 适配器或电池接入后产生的一个小电流的电压，给 TB 芯片供电
BAT_VOLT VREGIN20 的电压检测脚，阈值 2.9V
MPWRG TB 芯片检测到 VCC3M、VCC5M 正常后，发出的 PG，给南桥的 RSMRST#
-H8_RESET 联想芯片发给 H8S 的复位
TB 芯片检测到 M 电压正常后，自举升压的 15V。给 TB 芯片输出的 xx_DRV 提供动
VDD15
力
TB 芯片检测到 M 电压正常后，自举升压的 28V（实际 25V），用于驱动保护隔离电
VCPIN28
路的 N 沟道场效应管
A_ON A 电压开启（S3 电压，如内存供电）
B_ON B 电压开启（S0 电压，如总线供电）
B_DRV TB 芯片发出的 B 电压驱动信号
BPWRG TB 芯片检测到 VCC3B、CVCC5B 正常后，发出的电源好
AMT_ON ME 模块电压开启
SLP_M# 南桥发出用于控制开启 AMT 供电
AMTPWRG AMT 电源好
-PWRSWITCH、
电源开关信号
-PWRSW
BATMON_EN 电池电压监控开启
M_BATVOLT 主电池电压反馈
M1_DRV、M2_DRV 主电池充放电驱动信号
BAT_CRG 电池大电流充电控制开关
CHARGER_OUT12 充电芯片控制输出的 12.6V 充电电压
M_TRCL 主电池涓流充电控制开关
S_TRCL 副电池涓流充电控制开关
38
Chapter Five
The basic application circuit of electronic element
Electronic components of laptop are capacitors、resistors、diodes、transistors、field effect
transistor、gate circuit、comparator、voltage regulator and so on.They are the most changeful
when used in the circuit.For the people who have just touched with laptop repair,it’s quite difficult
to understand a basic electronic circuit.It makes the circuit-based become a stumbling block for
maintenance people.This chapter mainly introduces the basic application of the electronic
components in the circuit,and dose not include the understanding and measurement of
components.If the reader is not familiar with the understanding and measurement of
components,can refer to the relevant basic book,there are a lot of such books on the market.
Basic application circuit of capacitor
1.Filter capacitor
Filter capacitor used in the power rectifier circuit,and used to filter out the AC components.It requires that larger
capacitance adopts the high-capacity tantalum capacitor,and smaller capacitance adopts SMD
capacitor.PC90、PC89、PC93 in figure 5-1 are 330µF tantalum capacitor.
Figure 5-1 Filter capacitor
2.Coupling capacitor
Coupling capacitor usually adopts chip capacitor,used on the signal line of PCI-E and
SATA,the feature is in series in the signal circuit,the role is used to isolate DC and ensure the
transmission of high-speed signals.As shown in figure 5-2,four side by side capacitor is the
coupling capacitor,and both ends are thin lines.
3.Resonant capacitor
Resonant capacitor is only used in the crystal oscillator circuit,the general capacitance is tens of pF,and
respectively connected between two pins of the crystal oscillator and ground,the parameters of the resonant
capacitor will affect the resonance frequency and the output amplitude of the crystal oscillator.
Resonant capacitor adopts chip capacitor,as shown in figure 5-3,C180、C181 are the resonant capacitor.
Figure 5-2 Coupling capacitor
Figure 5-3 Resonant capacitor
Basic application circuit of resistance

The application of resistance in the board circuit are mainly pull-up resistance、pull-down
resistance、protective resistance、thermal resistance.
30
第 5 章电子元件的基础应用电路
1.the pull-down resistance
In general,the resistance connected the voltage is the pull-up resistance(in figure 5-4),and the resistance
connected the grounding is the pull-down resistance(in figure 5-5).Pull-up is to clamp uncertain signal at a high
level through a resistance,the resistance works current-limited effect at the same time.And pull-down is in the same
way.
Figure 5-4 pull-up resistance
Figure 5-5 pull-down resistance
The application of pull-up and pull-down resistance shown in figure 5-6:when R206 is installed and R205 is not
installed,the INTVRMEN is high level,open the internal voltage regulator of ICH7(the default value);when R205 is
installed,R206 is not installed,INTVRMEN is low level,close the internal voltage regulator of ICH7.
RC delay circuit(shown in figure 5-8):+VCC-RTC charge C1704 first through R1701,the RTCRST# voltage will
slowly rise,the time required that it rises to equal with +VCC-RTC voltage is the delayed time.A simple calculation
of the delayed time can be used R*C,such as 20kΩ*1µF=20ms.
Figure 5-7 the voltage division circuit
Figure 5-8 RC delay circuit
2.protective resistance
The protective resistance plays the role in protective
31
effect.When the circuit load becomes large,beyond the range of resistance can afford,resistance
will be open circuit,make the corresponding circuit to stop working,so as to achieve the purpose of
protecting the components.The resistance of protective resistor is generally blow 10Ω.Ιn the figure
5-9,R243 is the protective resistor.
Figure 5-9 the physical map of protection resistance
3.Thermal resistance
The thermal resistance is divided into two,“the higher the temperature,the lower the resistance”(NTC,the negative
temperature coefficient) and “the higher the temperature,the higher the resistance”(PTC,the positive temperature
coefficient).The thermal resistance shown in figure 5-10,but we can not distinguish NTC or PTC from the physical.
Figure 5-10 the thermal resistance
The basic application circuit of the

diode
The forward voltage drop of the common silicon is 0.7V,and the
germanium diode is 0.3V.In the figure 5-11,the positive electrode is on
the left,the negative electrode is on the right,3.3V input from the left,if it’s a silicon tube,2.6V will
be output from the right.
1.Or gate application of diode(shown in figure 5-12)
Power failure with 3V BAT power supply,after plugging with 5VALW power supply,in order to save battery
power,can ensure that VCCRTC always have electricity.Such diodes are generally composite diodes,the material
object shown in figure 5-13.
32
Figure 5-12 Or gate application of diode
Figure 5-13 Composite diode physical map
2.AND gate application of diode(shown in figure 5-14)
As long as any signal at the left end of the diode have low level,diode will conduct,pull HWPG low.
Figure 5-14 AND gate application of diode
3.Clamping applications of diode(shown in figure 5-15)
33
(1)VIN voltage(assumed to be 18.5V) after resistance PR29,PR28 series partial pressure,the voltage after partial
pressure is 7.6V.
(2)Now the positive electrode voltage of PD9 is 7.6V,the negative electrode voltage is 3.3V,so the positive
electrode is greater than the negative electrode,and over the conduction voltage drop 0.7V.
(3)PD9 conduction,the diode cathode is only higher than the negative electrode 0.7V after conducting,so the A
point voltage is clamped to about 4V.
Clamping diodes are generally next to the USB interface or VGA interface,used to prevent static
electricity,shown in figure 5-16.
Figure 5-16 Anti-static clamping diode
4.Voltage stabilizing diode
When the diode reverse voltage to a certain value,the reverse
current will suddenly increase,which is called the breakdown
phenomenon.In the state of breakdown,the current through the
tube changes a lot and the voltage of both ends of the tube is
almost constant,by using this feature,it can achieve voltage regulation,which is called the voltage stabilizing
diode.In the figure 5-17,U9000 is 2.5V voltage stabilizing diode,when the negative voltage applied is more than the
regulated value,then the reverse breakdown current will appear,so the voltage of both ends can be fixed.R9000 is
34
the limit current resistance,and the reverse breakdown current of the voltage stabilizing diode is between 5-40mA.
In the figure 5-18,PD12 is 5.1V voltage stabilizing diode,when VS is 19V,applied to the negative,can be broken
down,the voltage reaching the positive is remaining 13.9V,and after the partial pressure of PR87 and PR90 to send
chip 6 pin SHDN# as open,the purpose is to limit VS minimum voltage.Only VS exceeds a certain value,the partial
pressure after the reverse breakdown can meet the rising edge threshold value of SHDN#.
Figure 5-17 the application of the voltage stabilizing diode
Figure 5-18 the application example of the voltage stabilizing diode
Basic application circuit of transistor
35
In the laptop circuit,the main application of the transistor is switching action:E pole of NPN transistor connects
ground:when B pole input high level,C pole is low level;when B pole input low level,C pole is high level.Specific
content as follows:
Common NPN type:when VB>VE 0.7V,B-E is conducted,and C-E is also conducted.
Common PNP type:when VB<VE 0.7V,E-B is conducted,and E-C is also conducted.
In the figure 5-19,when A point is high level 0.7V or more,applied to B pole of transistor via resistance,then the
transistor C-E will be conducted,and Y output low level.
In the figure 5-20,PQ41 is the digital NPN transistor with inner zone resistance,it’s same as the common
transistor,also has the feature of high level conduction and low level cut-off.However,the voltage of B pole must be
greater than the voltage of E voltage for a certain value,about this value,you need to check the relevant data
sheet.According to the manual,the conduction voltage is VI(on)=1.9V,as shown in figure 5-21.
Figure 5-22,is the application of transistor switching action:only when +VLDT voltage is greater than 0.7V,added
to the B pole of PQ26,making it to be conduction.;pull the B pole of PQ25 low,PQ25 is cut-off;+3VRUN pull
VLDT-PG up directly,generating high level to send to rear pole.
Figure 5-19 the application of common transistor
Figure 5-20 the application of the digital transistor
Figure 5-21 the screenshot of DTC144EUA data manual
Figure 5-22 the application of transistor switching action
36
Basic application circuit of field-effect tube

The switching action of the field-effect tube shown in figure 5-23.When S5-ON is high level(above 2V),PQ68 is
conducted,Y is pulled to the ground;when S5-ON is low level,PQ68 is cut-off,Y is pulled on 5V by 5VPCU.
In the figure 5-24,when SUSON is high level,PQ70 is conducted,pull down the G pole of PQ73,PQ73 is cut-
off;+15V pull SUSD up on 15V,to send to the G pole of PQ56and PQ76;PQ56 and PQ76 can be conducted
completely,generating 3VSUS、5VSUS(the condition of N channel MOS full conduction:VG>VS 4.5V or more).
37
Figure 5-23 the switching action of the field-effect tube
Figure 5-24 examples of application of field-effect tube
Basic application circuit of gate circuit

1.NOT gate
In the figure 5-25,U27 is the NOT gate:when DGPU_SELECT# is high level,U27 outputs a low level of
38
IGPU_SELECT#;when DGPU_SELECT# inputs level,IGPU_SELECT outputs high level.
2.AND gate
The application of the AND gate shown in figure 5-26:only when EC_PWROK and IMVP_PWRGD are high
level,then U25 can output high level of SYS_PWROK.
3.Three-state gate
The application of the three-state gate shown in figure 5-27:only when OE is low level,the output level is
consistent with the input level(equal to the follower);when OE is high level,no matter what state the input is,the
output is always keep high impedance state.But in the figure 5-27,OE has been forced to ground,so it’s no
difference between this circuit and follower in the level logic.
Figure 5-25 the application of the NOT gate
Figure 5-26 the application of the AND gate
Figure 5-27 the application of the three-state gate
39
Basic application circuit of comparator

Basic application of comparator shown in figure 5-28,the 3V battery is added to the inverting
input of the comparator,compared with the voltage of VIN partial pressure.When VIN is greater
than 15.67V,the voltage of partial pressure will be higher than 3V,the comparator open drain
output(7 pin and PU48 comparator internal are disconnect),RSMVCC3 pulls up ACIN to be high
level to the chip;when VIN is less than 15.67V,the comparator will output low level(7 pin and 4
pin internal are short circuit),ACIN is pulled to the ground.
CPU overheating protection circuit shown in figure 5-29.The comparator 6 pin is divided into
2.5V by +5VALM.At the room temperature,the resistance of PH1 is 10kΩ,+5VS partial pressure
through PH1 and PR161,applied to the comparator 5 feet,will be less than 2.5V of comparator 6
pin.The comparator output low level,make PQ39 cut-off,MAINPWON is not pulled down,at the
same time,because the comparator output low level,leading to PR167、PR163 series,and form
series with PR161,so that the 2 pin voltage of PH1 is pulled down again.
When the temperature of PH1 increases,the resistance is reduced to less than 2.55kΩ,the
voltage of the comparator 5pin achieved will be higher than 2.5V of 6 pin,the comparator outputs
5V high level,make PQ39 conduct,pull down MAINPWON,the system power supply is shut
down;at the same time,the high level comparator output,making PR167、PR163 and PH1 be
series,thus pull up the 2 pin voltage of PH1 again.This PR167 is the hysteresis resistance,the
author called it as “fence resistance”.The role is to make the CPU temperature protection value not
stay at a point,such as 90 degrees over temperature protection,50 degrees to return to normal.
Figure 5-28 the application of camparator
Figure 5-29 the comparator in a temperature control circuit
40
Basic application circuit of the converter

Multiplexer(MUX) is used in the second generation dual graphics switching circuit:S is the control signal,when S
is low,B0 connects A,when S is high,B1 connects A,as shown in figure 5-30.
Figure 5-30 the definition of converter pin
VOUT=VFB×(1+R8114/R8104)
Basic application of the voltage regulator

As shown in figure 5-31,U8100 is low dropout regulator(LDO),which input power supply from 1
pin,output voltage from 5 pin,two resistances connected by 4 pin control high-low of the output
voltage,the reference voltage is 1.24V.3 pin is the open signal of chip,high level opens output and
low level stops output.The calculation formula of output voltage is:VOUT=VFB×(1+R8114/R8104)
41
The voltage regulator in figure 5-32 is common in the memory VTT power supply,+3VALW is the control voltage
of chip,VIN is the input voltage,REFEN is partial pressure of +1.5V to 0.75V,the conditions are satisfied,the chip
output +0.75VSP from 4 pin.This chip is mainly used for the current amplification,can provide 1.5A current.
There is also a commonly used voltage regulator 431L,as shown in figure 5-33,is the 1.24V precision voltage
regulator:+3VPCU current limiting through R139,and stable output reference voltage of 1.24V through 431L(C
and R connected together,as a voltage regulator diode).
Figure 5-31 the voltage regulator
Figure 5-32 common voltage regulator in memory VTT power supply
Figure 5-33 precision voltage regulator 431L
42
Chapter six
The use of circuit diagram and point position diagram
The circuit diagram reflects the structure and working principle of the electronic circuit
directly,so it’s generally used in the design and analysis of the circuit.The electronic file format of
laptop motherboard circuit diagram is *.PDF,a circuit diagram usually have dozens of pages to
hundreds of pages,their ligature is horizontal and cross,and varied in form,beginners often do not
know from where to start and how to read it.Understanding the motherboard diagram circuit is a
threshold for maintenance personnel to further improve.we must have a certain basic knowledge.
In addition,because the component on the laptop motherboard is too dense,even understand
the principle in the circuit diagram,it’s also quite difficult to find the damaged components in the
real object.Some manufacturers did not even print components position number,which requires
maintenance personnel must know how to use the point position diagram,in order to identify the
location of components quickly and accurately.
第 6 章电路图和点位图的使用
表 6-1 部分主板零件未安装列表
厂家 Manufacturer 符号 Symbol 示例 Example
广达 Quanta
仁宝 Compal
华硕 ASUS
纬创 Wistron
英业达 Inventec
三星 Sumsung
苹果 Apple
IBM
41
The use of circuit diagram

The file format of laptop circuit diagram is *.pdf.We can use Adobe Reader or Foxit software to
open this file.When you open a drawing,in general,the first page is a schema or directory,as shown
in figure 6-1.
The figure marked the page where each function module,for example,CPU occupies page 4 and
page 5.If you want to view the page with CPU,you can input the page number in the following
page frame,as shown in figure 6-2.
In the figure 6-3,CLK_CPU and CLK_CPU_BCLK through the resistance,no longer regarded as
the same signal,but to be regarded as two signals.
The pin name of components and the signal named by manufacturer can not be considered the
same concept,as shown in figure 6-4,PLTRST# is the pin name of C26 pin,but PLT_RST# is the
signal named by manufacturer,check where the signal connected to,you should find the
PLT_RST#.
Figure 6-5 is the test point T83,for factory testing.
Jumper point/isolation point,usually connected with tin directly,convenient to the
troubleshooting,the circuit symbol shown in figure 6-6.
42
Figure 6-7 is the physical map of the isolation point.
* or @ is printed on the device,indicating that the device is not installed in the board of the current
version.NO STUFF also indicates that there is no installation.Not installed,it represents that both
ends are disconnected,as shown in table 6-1
Table 6-1 the list of some parts of the motherboard not installed
If the parts are not installed,but can not be disconnected,then add the "short" words,or connected
with a straight line,as show in figure 6-8.
The signal back with "#"、“-L" or the front with "-",etc,indicates that the signal is active-low
level.The word of "efficient" needs to be considered carefully,and need to combine with the
English front of "#" to understand.As shown in figure 6-9,in fact,PERST# and 2231_SHDN#
signals are high level in the boot state,but did not conflict with the expression of "active-low level".
In the common drawings,the digital followed by signal,indicates the page the signal connected
to,but in the product drawing of IBM and Apple,as shown in figure 6-10,75D3 and others indicate
the place that the signal connected to page 75 coordinate position D-3,positioning is more
accurate,it's convenient to find signal.
In addition,the direction of the arrow,represents the trend of the signal,as shown in figure 6-11,but
due to the randomness of drawing staff,leading to not believe all.
When the line is crossed,only the point indicates that the line is connected together,as shown in
figure 6-12.
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In the figure 6-13,the signal is the same kind of signal line,will be drawn together,to another
page,then separate,not to say that these signal lines are connected actually.
Figure 6-1 architecture diagram
Figure 6-2 page input box
Figure 6-3 screenshot of the clock signal
Figure 6-4 PLT_RST# signal diagram
Figure 6-5 circuit symbol diagram of the test point
Figure 6-6 circuit symbol diagram of the isolation point
Figure 6-7 the physical map of the isolation point
Figure 6-8 circuit diagram of parts direct connection
Figure 6-9 active-low level signal circuit diagram
Figure 6-10 screenshot of Apple product circuit
Figure 6-11 screenshot of the signal
Figure 6-12 the circuit diagram of cross connected and disconnected
Figure 6-13 the similar signal circuit diagram
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1．CASTW—*.lst
2．Test Link—*.brd
45
46
47
3．Boardview—*.brd、*bdv、*bv
48
4．TSICT—*.asc
49
The use of common point position figure

1.CASTW—*.lst
CASTW is the point position figure used by IBM,the most outstanding characteristics of this
point position figure is that we can see the actual direction of signal.The red indicates that the
signal is in the current layer,and the yellow indicates that the signal is in the other layer.Here "the
other layer" refers to the other side of PCB,also refers to the middle layer of PCB.Common
operations and shortcut menu shown in figure 6-14.
2．Test Link—*.brd
The point postion figure of Landrex corresponds to the file format of BRD.Common
operations are as below:click C key to find components(also supports three components);click N
key to find signal;double-click the left mouse button to enlarge;click the right mouse button to
shrink;click R key to rotate the screen;click the space key to page.The specific operation can be
viewed through "help" menu.Note the operation example of figure 6-15~figure 6-21,the signal
found by clicking N key is "+15V" voltage.Voltage is also regard as a signal(or network).
When we click to select the pin of components,the name of signal will be shown in the below
status bar,as shown in figure 6-22.A common operation is:when the welding plate appear the
phenomenon of PIN dropping,we can refer to the point position figure,to check which PIN need to
fill PIN and which don't need to fill.
3．Boardview—*.brd、*bdv、*bv
The software of Boardview point position figure is used in the file of Tuo Fu(program
BoardViewR4,the file format is *.brd)、Hong Han(program BoardView.the file format is *.bdv)、
Wei Yang(program BoardView1.3,the file format is *.bv) and other company.
The screenshot of Tuo Fu BiardviewR4 shown in figure 6-23,press the shortcut key "D" to
find the components,press the shortcut key "N" to find the signal.
The screenshot of Hong Han shown in figure 6-24,press the shortcut key "D" to find the
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components,press the shortcut key "E" to find the signal.

The screenshot of Wei Yang BView1.3 shown in figure 6-25,press the shortcut key "C" to
find the components,press the shortcut key "E" to find the signal.
4．TSICT—*.asc
TSICT software is generally used by ASUS,Gigabyte also uses it.The common operations are
as below.
Click the "models" menu to load the file,if there are contents in the BOM box,selected it,then
click the OK button,as shown in figure 6-26.
Input the device label in the input box on the left bottom,to find the device;click "TOP" and
"Bottom" to select the positive and negative side of the motherboard,as show in figure 6-27.
The mouse will be stopped on the device,select "display connected devices and PAD"to find
connected point from the context menu,as shown in figure 6-28.
Click the right key in the blank position,and click Net query,you can find the signal,as shown
in figure 6-29.
If you move the bitmap,and can not find,you can click AUTO to automatically return to the
initial state,as shown in figure 6-30.
Figure 6-14 the screenshot of IBM point position figure
Figure 6-15 the operation drawing 1 of Landrex point position figure
Figure 6-22 the schematic diagram 8 of empty pin
Figure 6-23 the interface map of Tuo Fu point position figure
Figure 6-24 the interface map of Hong Han point position figure
Figure 6-25 the interface map of Wei Yang point position figure
Figure 6-26 the schematic map of TSICT point position figure opening files
Figure 6-27 the interface of TSICT point position figure finding the device
Figure 6-28 the operation example of ASUS point position figure
Figure 6-29 ASUS point position figure finding the signal
Figure 6-30 the position map of AUTO key
51
Chapter seven
The introduction of EC and BIOS
EC(Embedded Controller) is a 16 bits single chip microcomputer,which is featured in laptop,it is
because of the use of EC,reflecting an important difference between laptop and desktop.
In desktop,the keyboard and the mouse are independent of the system host,is generally connected
with the host system by PS/2 or USB interface.But in the laptop,in order to achieve the purpose of
portability,it's necessary to use the built-in keyboard(matrix decoding keyboard) and the built-in
mouse(such as the touchpad、trackpoint are built-in mouse device).So the laptop needs a special
keyboard controller,the special EC of the laptop is equipped with this feature.
Moreover, a most important problem in design of notebook is to make the system more
power,increase the battery life,it must have good heat dispersion performance,and try to minimize
the system noise,according to the temperature to control the stalling of CPU fan.Laptop power
management,such as laptop computer into standby or shutdown、the electric power dispatching of
the external power supply system、power detection of intelligent battery、charging and
discharging task,as well as some practical shortcut buttons,these important functions are
accomplished by EC.
In fact,EC of the laptop is an extension of the traditional KBC(Keyboard Controller),equipped
with two part function of KBC and embedded control,so EC is also called as KBC.
EC is widely used in the design of laptop with intelligent power-saving function,it undertakes task
of laptop built-in keyboard、touchpad、laptop battery intelligent charging and discharging
management and temperature monitoring and others.EC plays an important role in design of
portable、intelligent、personalized of the laptop.
EC interior has a certain capacity of Flash to store the EC code.The position of EC in the system is
not next to the North and South Bridge,in the process of open system,EC control the timing
sequence of most of important signal.In laptop,no matter in the boot or shutdown state,EC is
always open,unless the battery and adapter completely removed.
In the shutdown state,EC has kept running,and waiting for the user's boot information.And after
第 7 章 EC 和 BIOS 介绍
the boot,EC continue to control the keyboard controller、charging indicator light and fan and
other device,and even control the system standby、sleep and other state.
BIOS is the abbreviation of "Basic Input Output System" in English,and the Chinese name is
"basic input/output system" after literal translation.In fact,it is a group of program curing to a
ROM chip on the computer motherboard,holds the most important basic input/output
program、the system settings information、self-check program after booting and the system self-
triggered program of the computer,it's main function is to provide the lowest level and the most
direct hardware setup and control for the computer.
It should be noted that,although the BIOS is referred to the program curing in the ROM,but in
maintenance,we usually called the ROM chip curing the program as BIOS.
Figure 7-1 is the physical map of EC and BIOS,a large square chip is EC,a small rectangle chip is
BIOS.
Figure 7-1 the physical map of EC and BIOS
The working conditions and functions of EC
1.The basic working condition of EC
(1)Standby power supply:the name of EC standby power supply is usually
VCC0、AVCC、VCCA,etc,a small number of EC standby power supply is VBAT.
(2)Standby lock:it’s usually an external 32.768kHz crystal before,now most is free of
crystals.
(3)Standby reset:the most beginning of the EC reset signal,which name is usually
ECRST#、WRST#、VCC_POR#,etc,the reset of SMSC H8S is RES*.
(4)Program:EC need to get the corresponding program,configure the GPIO pin,then to
work.The program may be stored in the EC,also may be stored in the ROM under EC.
2.The bus communicated EC and the South Bridge
EC connects with the South Bridge by LPC(Low Pin Count) bus.
VCC3:the power supply of LPC bus,3.3V.
LPCCLK:LPC CLOCK provides 33MHz frequency for LPC,about 1.6V.
LRESET#:LPC reset signal,3.3V.
LPC_AD[0:3]:address data complex line,these four signals are used to transmit the address and
data of LPC bus.
LPC_FRAME#:the cycle frame of LPC,when this signal is active,indicates the start or end of a
cycle of LPC.
3.EC controls LCD backlight
LID_SW#:lid-close switch.There are two functions of LID_SW#:in shutdown state,this
signal is used for EC to determine whether it can turn on;pull down this signal after starting
up,which can turn off the backlight.Now commonly using the Hall element(magnetic sensor) to
control this signal.
LCD_BACKOFF:backlight control
LCD_BL_PWM:brightness control
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4.EC manages the battery charging

(1)Pre-charge
If the battery voltage is less than 0.9V,it is determined that the battery has been
damaged,will not charge the battery,because charging the damaged battery may cause safety
problems,such as explosion or burning.
When the battery voltage is lower than the discharge end voltage(3V) and greater than
0.9V,with 1/10 current of the constant current charging current to charge with small current,and
the time is short,generally for a few minutes.If you use a large current to charge the battery with
full discharge,it will damage the battery.
(2)Constant current charging
When the battery voltage is greater than a certain threshold,it will be the constant current
charging,and the feature is constant current.Most of the energy of the battery(80%) is stored at this
stage for a long time.The charge current is generally controlled at an appropriate value,if the value is
too large,which will affect the charging efficiency,and the capacity will be reduced after full.
(3)Constant voltage charging
When the battery voltage reaches the end voltage of the charging,the battery is charged with
constant voltage,and the feature is that the battery voltage is kept constant.
The charging current is gradually smaller.When the current is less than 1/10 of constant
current charging current,charging end.The battery capacity will be fully replenished.
(4)Trickle charge
When the charging current is less than 1/10 of the value of constant current charging,the
charging current is close to 0,which is the trickle charge,and the feature is the battery voltage
constant.
The purpose is to supplement the self-discharge of the battery,the self-discharge rate off the
lithium battery is usually 5%~10% per month.
How to judge whether EC comes with the program
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EC needs the program(EC CODE) configuration to complete its various work,the program
may be stored in its internal ROM,also may be stored in the motherboard BIOS.If the EC comes
with the program,when doing maintenance,you must find the same motherboard to disassemble.If
EC not comes with the program,you can find the same type of chip to replace.How to judge
whether EC comes with the program?
First,observe the appearance,EC with stickers、marked on the surface is usually bring their
own procedures.EC in the figure 7-1 not comes with the program,and EC in the figure 7-2 comes
with the program.
Second,observe the architecture,in machines can be repaired on the current market,there are
four kinds of connection ways for EC and BIOS,as shown in figure 7-3.
Firstly,BIOS connects to EC through X-BUS and SPI bus,then EC connects to the South
Bridge through LPC,in general,in this case,EC code is placed in the BIOS,that is share a chip with
BIOS.
Secondly,BIOS connects to the South Bridge through SPI bus,there is not ROM under EC,it
uses its own internal ROM.Common in ThinkPad and Apple,some models of the latest Lenovo
also use this way.
Thirdly,the main BIOS connects to the South Bridge through SPI bus,hang a SPI ROM chip
under EC for storing EC CODE,such EC is not comes with the program.
Fourthly,EC and the South Bridge connect BIOS through SPI bus,such EC is not comes with
program.
Figure 7-2 EC comes with the program
Figure 7-3 the relational graph of EC and BIOS
Function and working conditions of BIOS

BIOS is the program to provide the lowest level and the most direct hardware control in the
computer system.It controls the input device and output device of the computer system,and is a
hub connected the software program and hardware device.For the PC,BIOS includes the
controlling keyboard、display screen、disk drive、serial communication device and some other
functions of the code.The computer technology develops into today,there are all kinds of new
technologies,many of the techniques of software part is to use BIOS to manage and
accomplish.For example,PnP technology(Plug and Play) is accomplished by adding PnP module in
the BIOS.Again,the hot swap technology also transmit the hot swap information to the
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configuration management program of BIOS by the system BIOS,and reconfigured(such as

interruption、DMA channel and other allocation) by the program.In fact,the hot swap technology
is also PnP technology.
In addition to the motherboard,on the other device,such as network card、graphics
card、MODEM、digital camera、hard disk and so on,are also have the so-called BIOS,some
SCSI cards and some interface cards with special function also have its own BIOS.For
example,BIOS on the graphics card is used to complete the communication between the graphics
card and the motherboard.The start and using of the hard disk also needs HDD BIOS to
complete.In the process of the boot,the motherboard BIOS will call and execute these additional
BIOS program,to complete the initialization of these hardware.So theoretically speaking,each kind
of hardware can have its own BIOS.But too many BIOS,it will not only increase the cost,and will
lead to compatibility problems,therefore,in general,integrated the standardized device in the
motherboard,for those unique specification of manufacturers,appears with the form of additional
BIOS.These BIOS on the external and the motherboard BIOS using Flash ROM as BIOS ROM
chip,also easy to upgrade,to modify its defects and enhance its compatibility.
1.The function of BIOS
(1)POST power on self test:after the computer power-on,POST(Power On Self Test) program
check each device in the system.Usually complete POST includes to test CPU、640KB basic
memory、more than 1MB of extended memory、ROM、CMOS memory、serial and
parallel、graphics card、soft and hard disk and keyboard,once found the problem during self
test,the system will give message or whistle warning,
(2)BIOS system start the bootstrap program:after the system finishing POST self test,ROM
BIOS according to the boot sequence stored in the system CMOS settings to search the soft and
hard disk drives and CD-ROM、network server and others for booting drive effectively,read the
operating system boot record,then give the system control power to the boot record,and completed
the sequence boot of the system by the boot record.
(3)Interrupt service routine:responsible for the allocation of the motherboard hardware
interrupt number assigned.
(4)Program settings:refers to enter the CMOS settings after booting.
001/010/100：1M=128KB
002/020/200：2Mb=256KB
004/040/400：4Mb=512KB
008/080/800：8M=1MB
160：16Mb=2MB
320：32Mb=4MB
640：64Mb=8MB
2.BIOS capacity identification
For example,the model of SST 39VF040，three digits with underlined are
different,representing different capacity.
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001/010/100：1M=128KB
002/020/200：2Mb=256KB
004/040/400：4Mb=512KB
008/080/800：8M=1MB
160：16Mb=2MB
320：32Mb=4MB
640：64Mb=8MB
Note:8b(bit)=1B(byte)
（1）TSOP48
3.The package type of BIOS
There are many kinds of BIOS package,the specific as follows.
(1)TSOP48
BIOS with TSOP48 package are under EC,through X-BUS,the material object shown in
figure 7-4.
Figure 7-4 BIOS with TSOP48 package
The definition of pin shown in figure 7-5.
A0~A18:the address line D0~D15:the data line CE#:Chip select VCC:power supply 3.3V
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OE#:output enable WE#:write enable RESET#:reset VSS:ground connection
Figure 7-5 the definition of BIOS pin with TSOP48 package
（2）TSOP40
(2)TSOP40
BIOS with TSOP40 package are generally X-BUS bus,the material object shown in figure 7-
6,and the definition of pin shown in figure 7-7.
Figure 7-6 the material object of BIOS with TSOP40 package
Figure 7-7 the definition of X-BUS BIOS pin with TSOP40
（3）TSOP32
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(3)TSOP32
BIOS with TSOP32 are generally X-BUS bus,pin function is similar to TSOP40,the definition of pin shown in
figure 7-8.
Figure 7-8 the definition of X-BUS BIOS pin with TSOP32 package
（4）PLCC32
(4)PLCC32
BIOS with PLCC32 package are also X-BUS bus in the laptop,the definition of pin shown in figure 7-9,and the
material object shown in figure 7-10.
CS#:chip select OE#:enable WE#:write enable VCC: power supply pin GND:ground A0~A17:the
address signal line D0~D7:the data signal line
Figure 7-9 the definition of X-BUS BIOS pin with PLCC32 package
Figure 7-10 the material object of BIOS with PLCC32 package
（5）SOP8
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(5)SOP8
BIOS with 8 pin are SPI bus,the definition of pin shown in figure 7-11,the material object shown in figure 7-12.
CS#:chip select SO:serial signal output WP#:write protection GND:ground SI:serial signal input
SCLK:serial clock HOLD:pause VCC: power supply
Figure 7-11 the definition of SPI bus BIOS pin
Figure 7-12 the material object of SPI bus BIOS
（6）SOP16
(6)SOP16
BIOS used by IBM X200 part of the model uses 16 pin SPI bus,the definition of pin shown in figure 7-13,the
material object shown in figure 7-14.The definition of pin is similar to 8 pin SPI,NC is Not Connected.
Figure 7-13 the definition of SPI bus 16pin BIOS
Figure 7-14 the material object of SPI bus 16 pin BIOS
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Chapter 8
The basic working process of notebook computer
As a professional notebook computer maintenance personnel,in addition to have a certain
basic knowledge,also need to understand the working process and Intel chipset standard timing of
the laptop and other maintenance theories knowledge.This chapter focuses on the boot process and
Intel standard timing.
8.1 The general boot process of notebook computer
The working process of the laptop follow a certain sequence.In the repair of the laptop,in
most cases,timing applied on the power-on part in the system boot,so also called Power
Sequence,mainly refers to a laptop motherboard having done from standby to CPU get RESET
signal.So literally,timing is time and sequence.The motherboard from standby to power-on,and
then to CPU work,we feel just a short time,is almost a second,but in the work of the motherboard,it
will happen a lot of things in a second,from the standby voltage producing,to press the switch,and
to the motherboard received the switch signal,then to send out each working voltage.And the
motherboard made so much action,it will strictly obeyed an established order,that is to say,in the
process of these steps,if the first step isn’t completed,then the next step is not start.And there is
strict time requirements between each step,some will be accurate to a few milliseconds,for
example,PWRGD signal generation requires that each voltage stabilize about 5ms will be sent.
From the above introduction,we can see that the timing has very important significance for
the normal working of a motherboard,the most common fault,such as no electricity,no boot and
others,there have an important relationship with the timing.It can be said that if you master the
timing,then you have a basic idea of maintenance for all kinds of faults of the laptop.
Hard starting process and Intel chipset standard timing
In general,the boot process of the laptop with Intel chipset(below series 4) is as follows:
Without any electrical equipment supply power (no battery and no power),through 3V button
battery to produce VCCRTC to supply RTC circuit of the South bridge,to keep the operation of the
internal time and save the CMOS information.
After plugging in the battery or adapter,produce the common point.
Then produce the EC standby power supply(usually linear voltage),after the standby power supply
is normal,EC supply power to crystal oscillator to produce the EC standby clock,the standby
power supply delay produce EC reset,EC reads the program configuration own pin(BIOS chip
select waveform as shown in figure 8-1).
第 8 章笔记本电脑的基本工作流程
Figure 8-1 BIOS chip select waveform
If EC detected the power adapter,it will automatically send a signal to open the standby power
supply of the South bridge(VCCSUS3_3,V5REF_SUS),and send RSMRST# signal to the South
bridge to notice the South bridge that the standby voltage is normal;if EC is not detected the
adapter(battery mode),EC need to receive the switch trigger signal,then will open the South bridge
standby power supply,to save power.
Press the switch,after EC receiving the switch signal,delayed send a high-low-high boot
signal to the South bridge PWRBTN# pin.
After the standby condition of the South bridge is normal and receiving PWRBTN#
signal,raising SLP_S5#,SLP_S4#,SLP_S3# signal in turn.
SLP_S5# or SLP_S4# control the production of the memory main power supply etc,SLP_S3#
control the production of the bridge power supply,the bus power supply(VCCP),the independent
graphics power supply etc(some is controlled directly by SLP signal,and some is controlled by EC after
SLP sending to EC).
EC delay send signal or other circuit switching to open CPU core voltage(VCORE).Thus,the
voltage of the machine has been fully opened.
After CPU power supply being normal,CPU power management chip send PG to the South
bridge VRMPWRGD pin at last.
After CPU power supply being normal,open the clock chip through the conversion
circuit,then produce various clock.
The South bridge received the power supply,clock,VRMPWRGD,and received EC or power
supply circuit delay conversion PWROK,the South bridge will send CPUPWRGD to inform CPU
that its core voltage has been successfully opened,and send PLTRST# and PCIRST# signal at the
same time.
After the North bridge receiving PLTRST#,send CPURST# signal to CPU,then CPU
officially start to work.
The above is the hard start process,in the process of hard start,we can divide the power supply
of the laptop into 4 levels.
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G3 power:voltage generated just plug the power,generally supply to power switch and EC,is usually
produced by linear way.
S5 power:the standby voltage of the South bridge,supply to VCCSUS3_3 of the South
bridge,power in the state of power off is usually produced by PWM way.
S3 power: the power supply of the memory,the power in the state of S3 sleeping.
S0 power: the main power supply to the normal operation of the machine,also called RUN
power,including the bridge main power supply,the bus power supply,CPU power supply and
others.
Sometimes,3V,5V produced by PWM way under the condition of G3 or S5 are also called the
system power supply.For example,Quanta series PCU voltage is the system power supply,but it
exits under the condition of G3.And for example,ASUS A8E South bridge standby voltage is
produced by PWM way,it is the system power supply.
Figure 8-2 is Intel chipset standard sequence diagram.
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Figure 8-2 Intel series 4 chipset standard sequence diagram
According to the sequence diagram shown in figure 8-2 is explained as follows.

G3:the power of the whole system are closed.
S5:power off state.
S4:dormant state.
S3:sleeping state.
S0:power on state.
VCCRTC:the power supply of the South bridge RTC circuit,3V,supply power to CMOS chip
(RAM) inside the South bridge.
RTCRST#:the reset signal of the South bridge RTC circuit,3V.ICH9 added another RTC reset
signal later,the name is SRTCRST#.
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32.768kHz : after the South bridge receiving VCCRTC and RTCRST#,supply power to the
crystal oscillator,the crystal oscillator running.The voltage of two pins of the crystal oscillator is
0.1~0.5V.
V5REF_SUS:5V standby voltage.
VCCSUS3_3: 3.3V standby voltage.
VCCSUS1_05: the South bridge internally produced the power supply 1.05V for itself,not to
consider this voltage when we analyze the timing.
RSMRST#: inform the South bridge that 3.3V standby voltage is normal,voltage 3.3V is
controlled by the external circuit.
SUSCLK: after the South bridge receiving RSMRST#,then send the 32kHz clock,most machines
do not use,it can be ignored.
PWRBTN#: POWER BUTTON,3.3V-0-3.3V pulse signal.
SLP_S5#: 3.3V,the control signal when the South bridge exit the power off state.
SLP_S4#: 3.3V,the control signal when the South bridge exit the dormant state.(usually just
use S5# or S4#,used to control the production of the memory power supply,and another is
idle.)
SLP_S3#: 3.3V,the control signal when the South bridge exit the sleeping state.(usually used
to control the bridge power supply,the bus power supply,the independent graphics power
supply,CPU power supply etc.)
VDIMM: the memory power supply.
VCORE/VCC: refers to the bridge power supply,the bus power supply,the independent power
supply,CPU power supply etc.
VRMPWRGD:inform the South bridge that CPU power supply is normal,3.3V.
CLK GEN: the clock chip starts to work,send various clock.
PWROK: inform the South bridge that power supply is normal (SLP_S3# complete
task),3.3V.
CPUPWRGD:the South bridge send PG to CPU,1.05V.
PLTRST#: the platform reset,the South bridge send the first reset,3.3V is generally sent to the
North bridge,EC,MINI slot etc.
PCIRST#: PCI reset,the South bridge send the second reset,the 3.3V computer is not usually
used.
CPURST#:after the North bridge receiving PLTRST#,send the reset of CPU,1.05V.
Next to the Intel bridge (such as GM45) as an example,see CPURST#,addressing process of
CPU and power-on self-test process.
In the process of the computer hard start,CPURST reset signal is sent and keep a low level of
a certain time,when the power supply circuit has been stable,then removed the RESRT low level
and keep a high level,CPU start to work,the hard start finished,and start to the soft start.
CPU will check FSB front bus line is busy or not through the DBSY# signal of the interface
circuit.When DBSY# is low level,it means that FSB bus is busy,only released it,CPU will be the
62
next step work;when DBSY# is high level,it means that FSB is not busy,CPU will through ADS#
address strobe signal line to tell the North bridge ready to send the data.
ADS waveform as shown in figure 8-3.
After the North bridge receiving this signal,if its in good condition and has been ready,the
North bridge will send a low level of H_TRDY# to CPU,told the CPU is ready,and can receive the
data.Then CPU will through A31~A0 send FFFF0H address signal,which is a jump instruction in
the BIOS.A0~A31 to FSB front bus interface of the North bridge,through FSB frequency
conversion,level conversion and address decoding send to the North bridge.After the North bridge
receiving CPU addressing instruction,through DMI bus send to the South bridge.
The North bridge and the South bridge DMI bus consists of 16 lines,point to point transmission,signal lines
including DMI_RXP(0:3),DMI_RXN(0:3),DMI_RXN(0:3),DMI_TXN(0:3),as shown in figure 8-4.
Figure 8-3 ADS# waveform
Figure 8-4 DMI bus signal diagram
After the South bridge receiving the addressing instruction of the North bridge,then start to search
BIOS,first search whether there is BIOS on the PCI bus(see figure 8-5).When there is no BIOS on
PCI bus,according to the PCI bus signal set to determine where BIOS is.If BIOS is under EC,after
the South bridge through PCI decoding module,then to communicate with EC on the LPC
bus,when EC receiving the addressing instruction,then through X-BUS or SPI bus to BIOS.BIOS
returns the data to the CPU,CPU running POST self-check program in the BIOS,and start self-
check action.
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Figure 8-5 BIOS location settings
The key signal to determine whether PCI bus action:PCI_FRAME# (Cycle Frame).
PCI frame period signal is low level,it means that PCI bus start work,and when it is high
level,it means that PCI bus is not to work.
The key signal to determine whether LPC bus action:LPC_FRAME#(LPC frame period).
The key signal to determine whether BIOS action:CS#(chip select).Selected when low
level,and is not selected when high level.
After CPU reading BIOS self-test correctly, then start to execute the process of POST
instruction.
When CPU addressing is normal, received POST self-test program returned by BIOS,
then start initialized the chipset(the South bridge and the North bridge),and also
initialized PCI-E bus(independent graphics).
After the South bridge initializing, grab the memory through SMBUS bus to be initialized,
the waveform is shown in figure 8-6.
After the memory self-test finishing, BIOS stores the self-test program into the memory.
Then called the BIOS program from the memory to test each device one by one, such as the
keyboard controller, network cards, sound cards etc.
Testing the graphics cards, find BIOS of the graphics cards, and call them to complete the
initialization of the graphics cards.
The graphics cards starts to read the screen information through EDID bus(shown in figure 8-
7), after reading the screen, then sends a signal to open the screen power supply and backlight.
Figure 8-6 SMBUS waveform of the memory
Figure 8-7 EDID waveform
Display the boot picture, and start to test the extended memory and give the corresponding
address.
Test some standard equipment, including hard disk, CD drives, serial ports, parallel ports,
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floppy drive etc.

After testing the standard equipment, the plug and play code supported by the system will
start to test and configure the plug and play equipment in the system, and distributes the interrupt
address, DMA channel and I/O port and other resources for these equipment.
After all hardware testing and being assigned the interrupts address,that is,all the hardware set
up a hardware system, then it will generate a ESCD file (it is the method that the system BIOS
exchange hardware configuration information for the operation system,the data is in CMOS),CPU
will compare the generated ESCD with the last ESCD,if finds the difference,it will update the data
in ESCD.
After updating ESCD,CPU will complete POST and the interrupt service routine,and then
carry out the bootstrap program of the system.The boot code of the system BIOS start the
operating system according to the boot sequence specified by users,find the boot files in the
starting device first,then write in the memory,BIOS give the control power of the computer to the
boot files,the operation system guided by the boot files,such as Windows XP,Windows 7 and so on.
About ACPI specification
ACPI summarize
ACPI（Advanced Configuration & Power Interface）is the standard of the advanced
configuration and the power interface.Before ACPI proposed,the universal power management
standard is APM with a BIOS level developed by Microsoft.ACPI is to replace the previous APM.
ACPI is jointly developed by Intel,Microsoft,Toshiba,is to have a common power
management interface between the operating system and the hardware,and to improve the disunity
interface developed by the different manufacturers on the power management before.
From Windows 98/SE,Windows ME and Windows 2000,Windows XP starting to support
ACPI.From the laptops to the desktops and servers are included in this specification.
ACPI can make the system to enter a low power consumption of “sleep state”,such as standby
and sleep,the purpose is to control the power consumption of the computer.
All state of ACPI can be divided into G(Global),D(Device),S(Sleeping),C(CPU).
G(Global) state of ACPI
Global refers to all system,and can be divided into the following 4 kinds.
G0:Working state.The user program can be executed normally,but the device
dynamically allocate their own state.When not used this device,this device can enter
other non operating state.Under this state,the system responds the external events in real
time.And the machine can not be disassembled and assembled under this state.
G1:Sleeping state.Under this condition,the system consumes less power,and no user’s
program is executed.The system looks like in the shutdown state,because the display screen is
turned off at this time.As long as any wake-up activation events message into the system,it will
soon be restored to a working state.Under this state,the machine can not be disassembled and
assembled.
G2/S5:Soft Off state.System only keeps very little power under this state,no users and the
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operating system programs are executed.The state takes a long time to return to a working
state.Under this state,the machine can not be disassembled and assembled.
G3:Mechanical Off state.Under this state,the power of the whole system is closed,there is no
current through the system,the system can only reopen the power supply switch to active.Under
this state,the power consumption is zero.
D(Device) state
Device refers to some devices,such as modems,hard drives,CD-ROM,etc,also can be divided
into the following 4 kinds.
D0:Fully-On.The normal working state.
D1:It can save less power consumption,the device function with keeping activities is much
more than which in D2 state.This sate is determined by the device itself,and some devices cannot
enter into the D1 state.
D2:Some functions are shut down,it can save a lot of power.This state is determined by the
device itself,some devices cannot enter into the D2 state.
D3:Off.The power of the device under this state is completely removed,so the next time when
the power is supplied once again,it needs the operating system to make a setting again.Under this
state,the device does not decode the addressing line.This state needs the longest wake-up time.All
devices can enter into this state.
S(Sleeping) state of ACPI
S state means Sleeping,and refers the system enter into the sleeping state in G1,also can be
divided into S0,S1,S2,S3,S4,S5.
S0:In fact,this is our normal working state,all devices are fully open,the power
consumption is generally more than 80W.
S1:CPU internal clock has been shut down under this state,but the contents of the system
(CPU,Cache,chipset) are not lost,the other parts are still working normally.At this time,the power
consumption is generally below 30W.In fact,some of CPU cooling software is developed in this
working principle.
S2:Similar to S1,at this time,CPU is in the state of stop,the content of CPU and Cache has
been lost,and the bus clock is also shut down,but the rest of the device is still running.
S3:This is STR(Suspend to RAM) we familiar with,in addition to the information of the
memory,the content of CPU,Cache,chipset is lost,the content of the memory is provided by the
hardware,the power service data is exist.The power consumption is less than 10W at this time.
S4:is also called STD(Suspend to Disk),the system main power supply is shut down,but the
system information will stored in the hard disk.By the operating system implementation after
Windows 2000,all the data of the memory saved to hiberfil.sys file in the hard disk,the hard disk is
not charged.
S5:All devices are shut down,which is soft shutdown,the power consumption is closed to 0.
The most commonly used is the S3 state,that is Suspend to RAM state,referred to STR.As the
name implies,STR is that to save the data of the working state before the system entering STR into
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the memory.Under the state of STR,the power still continues to supply the power for the most
necessary devices,such as memory,to ensure that the data is not lost,while other devices are in a
closed state,the power consumption of the system is very low.Once we press the power button,the
system will be awakened,immediately read the data from the memory and return to before working
state of STR.The read-write speed of the memory is very fast,so users feel that it takes just a few
seconds to enter and leave STR state.And S4 state,that is,STD,the data is stored in the hard
disk.Because the read/write speed of the hard disk is much slower than the memory,so it dose not
so fast like STR in using.
C state of ACPI
The C state of ACPI refers to the state of CPU,and can be divided into the following 5 kinds.
C0:the normal working state of CPU.
C1:CPU suspends work automatically,the software is completely unaffected under this
state,and there is a minimum time to wake up.The hardware wake-up time in this state must be
small enough,so the operating software can completely ignore the hardware wake-up time in this
state when determine whether use this device or not.
C2:Similar to C1,the South bridge send STPCLK# to CPU,and stop CPU internal clock,but
CPU continues to monitor the consistency of the bus and cache.The sequence of C0-C2-C0 is
shown in figure 8-8.
Figure 8-8 the sequence of C0-C2-C0
C3:C3 sleeping state,that is,close the external clock,the South bridge send STP_CPU# to
clock to close CPU clock,the South bridge send DPSLP# to CPU at the same time,to inform CPU
into C3 deep sleeping state.The sequence of C0-C3-C0 is shown in figure 8-9.
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C4:Similar to C3 sleeping state,after the South bridge sending STP_CPU and closing CPU
clock,the South bridge send DPRSLPVR and DPRSTP# signal to CPU power management chip,to
close the CPU core voltage.The sequence of C0-C4-C0 is shown in figure 8-10.
3VSB:3.3V standby voltage,supply the power to the wake-up of ACPI controller,the network
card,PCI and others in the South bridge.3VSB is the customary name,the name of each
manufacture is different,but the same chipset,the name in the South bridge is the same.
The standard name of 3VSB in the three chipset:Intel is VCCSUS3_3;nVIDIA is
+3.3V_DUAL;AMD is S5_3.3V or VDDIO_33_S.
RSMRST#:the normal signal of the standby voltage,the voltage is 3.3V.
The name of RSMRST# in the three chipset:Intel and AMD are RSMRST;nVIDIA id
PWRGD_SB.
SLP_S3#、SLP_S4#、SLP_S5#:the signal of the low level control enter S3,S4,S5 state.For
example,the system is in the state of S0 when running normally,three signals should be invalid,is
3.3V.SUSB#,SUSC# and others are similar to SLP_S*# signal.The state of the sleep signal in each
sleeping state is shown in figure 8-11.
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Figure 8-11 the state of the sleep signal in each sleeping state.
PWRBTN#:Power Button.At shutdown,pull low PWRBTN# signal,ACPI will set high

SLP_S5#、SLP_S4#、SLP_S3# to 3.3V in turn.If PWRBTN# continues being the low level for
4s,the system will be forced into the S5 state.
Clock,PWRGD and the reset circuit
If we analogy to the each device of the computer system is a group of people,then the clock
chip is like a password.But this is not a password,is the group with integrated multiple password.It
provides the different frequency to the main system chip and the slot on the motherboard,but there
will have the same frequency between connected devices,then it can exchange data information
normally between these chips.
PG and the reset in this section,is for the South bridge,one is the working condition of the
South bridge,and another is the affair the South bridge done after getting this working condition.
The clock circuit
The working condition of the clock chip.
As shown in figure 8-12,the working condition of the clock chip is following:
The power supply:+3VS produces +CLK_VDD、+CLK_VDD1 through L16 and L32 and
provides 3.3V,+1.05V produces +CLK_VDDSRC through L15 and provides 1.05V.
The open signal CK_PWRGD/PD#:the high level 3.3V opened.
14.318MHz benchmark crystal Y2.
CPU_STOP#、PCI_STOP#:CPU and PCI clock stop instructions,it needs to be the high level
when working normally.
SMBCLK、SMBDATA system management bus:used to transfer BIOS instructions.
FSLA、FSLB、FSLC frequency selection:according to the different CPU to produce the
different front bus clock.
The clock signal distribution of GM45 chipset
The clock signal distribution of GM 45 chipset is shown in figure 8-12,the specific is
following.
CLK_CPU_BCLK、CLK_CPU_BCLK# of 71,70 pin is the front bus clock that the clock
chip send to CPU,more than 100MHz,the specific value is set by FSA/FSB/FSC.
CLK_MCH_BCLK、CLK_MCH_BCLK# of 68,67 pin is the front bus clock that the clock
chip send to the North bridge,more than 100MHz,the specific is set by FSA/FSB/FSC.
24,25,28,29 pin is the set display clock that the clock chip send to the North bridge,96MHz
and 100MHz.
32,33 pin is the SATA controller clock that the clock chip send to the South bridge,100MHz.
35,36 pin is the PCI-E module clock that the clock chip send to the South bridge,100MHz.
57,56 pin is 100MHz core clock that the clock chip send to the North bridge.
44,45 pin is 100MHz clock that the clock chip send to MIMI PCI-E slot,used for wireless
network cards,etc.
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48.47 pin is 100MHz clock that the clock chip send to the onboard card.
15 pin is 33MHz clock that the clock chip send to the EC chip.
17 pin is 33MHz clock that the clock chip send to the South bridge,used in the reset circuit in
the South bridge.
20 pin is 48MHz clock that the clock chip send to the SD card reader chip and USB controller
in the South bridge.
7 pin is 14.328MHz reference clock that the clock chip send to the South bridge.
58,43,46,21 pin is the request signal of each clock,the low level is effective.
Figure 8-12 the clock signal distribution of GM45 chipset
The clock signal distribution of HM55 chipset

The clock signal distribution of HM55 is shown in figure 8-13,the characteristic is that the
clock chip is just sent to PCH clock,then sent out each clock by PCH to other devices.If it supports
the display set,and the display set supports DVI/DP/HDMI/e-DP interface,the bridge needs
25MHz crystal.
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The clock signal distribution of above HM65 chipset

The clock signal distribution of above HM65 chipset is shown in figure 8-14,the
characteristic is that it must be 25MHz crystal when the bridge integrates the clock chip.
Figure 8-14 the clock signal distribution of above HM65 chipset
The clock signal distribution of AMD double chipset

The clock signal distribution of AMD double chipset is shown in figure 8-15,the clock chip sends
each clock,but is just not responsible for sending 33MHz clock,33MHz clock is sent by the South
bridge.
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Figure 8-15 the clock signal distribution of AMD double chipset
The clock signal distribution of AMD single bridge

The clock signal distribution of AMD single bridge is shown in figure 8-16,the characteristic
is that the bridge integrates the clock chip.
Figure 8-16 the clock signal distribution of nVIDIA chipset
The clock signal distribution of nVIDIA chipset

The clock signal distribution of nVIDIA chipset is shown in figure 8-17,the characteristic is
that the bridge integrates the clock.
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Figure 8-17 the clock signal distribution of nVIDIA chipset
PWRGD and the reset circuit

The explanation of VRMPWRGD、PWROK、CPUPWRGD、PLTRST#、PCIRST# signal
in the South bridge is following:
VRMPWRGD:this signal should be connected to the PWRGD signal of CPU power
supply chip,used to indicate that the CPU core voltage is stable.This signal phase with
PWROK signal in the South bridge.The text of VRMPWRGD pin definition is shown in
figure 8-18.
Figure 8-18 the screenshot of the text about VRMPWRGD pin definition
PWROK:when the signal is effective,PWROK inform that all power of ICH has been
generated and stable for 99ms,PCICLK has been stable for 1ms.When PWROK becomes lower
level,ICH produces PLTRST# with low level.Note:PWROK must be inactive for three RTCCLK
clock cycles at least.The screenshot of the text about PWROK pin definition is shown in figure 8-
19.
CPUPWRGD:CPU power good,this signal should be connected to PWRGOOD pin of the
processor,indicates that CPU power supply is effective.This is an output signal,formed by the
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phase of PWROK and VRMPWRGD.The text of CPUPWRGD pin definition is shown in figure 8-
20.
Figure 8-19 the screenshot of the text about PWROK pin definition
Figure 8-20 the screenshot of the text about CPUPWRGD pin definition
PLTRST#:ICG produces PLTRST# signal to reset all devices (such as

SIO,FWH,LAN,GMCH,TPM,etc) on the entire hardware platform.When PWROK and
VRMPWRGD are high level,ICH will delay 1ms and drive PLTRST# to be high level.The text of
PLTRST# pin definition is shown in figure 8-21.
Figure 8-21 the screenshot of the text about PLTRST# pin definition
PCIRST#:this is the second reset signal,which is produced by the PLTRST# delayed

buffer.The text of PCIRST# pin definition is show in figure 8-22.
Figure 8-22 the screenshot of the text about PCIRST# pin definition
At last,after the RSTIN# pin (the pin definition is shown in figure 8-23) of the North bridge
receiving PLTRST# sent by the South bridge.Delayed 1ms send CPURST# to CPU,to complete
the hard start.HCPURST# pin definition is shown in figure 8-24.
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Figure 8-23 the screenshot of the text about RSTIN# pin definition
Figure 8-24 the screenshot of the text about HCPURST# pin definition
The sequence of the reset circuit is shown in figure 8-25.
Figure 8-25 the sequence of the reset circuit
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Chapter 9
The explanation of PWM circuit
PWM is that pulse width modulation,it is a very effective technique of using the digital output
of the microprocessor to to control the artificial circuit,is widely used in many fields from
measurement,communication to power control and transformation.This way is used in most of the
power supply circuit in the laptop.Compared with the linear regulated power supply,the PWM
circuit has the advantages of high efficiency,high output power,but also has the disadvantages of
complex circuit.
The introduction of PWM circuit

The PWM circuit in the laptop motherboard is generally composed of PWM chip and MOS
and the coil and the capacitance.
The brief introduction of the working principle of PWM
PWM regulates the output voltage by adjusting the effective pulse period T1,which accounts
for the proportion of the entire pulse period T(duty cycle).As the figure 9-1 an example,the validity
period of the highest voltage amplitude is about 5V,the duty ratio is about 50%,so the output
voltage is 5V*50%=2.5V.
Figure 9-1 PWM waveform
The working principle of PWM power supply

The principle of PWM power supply circuit is shown in figure 9-2,PWM chip controls the
high speed switch of the upper and lower tube to adjust the voltage,when the upper tube is
opened,the VIN passes through the upper tube to charge LC energy storage circuit and supply
power to the rear; the chip through FB monitor to charge full,then closes the top tube,and opens
the down tube,forms the discharge circuit of LE energy circuit,and continues to supply power to
the rear.T1 in the figure is the open state,T2 is the closed state,as long as control the duty cycle of
第 9 章 PWM 电路精解
T1,then it can control the height of output voltage.
Figure 9-2 the principle figure of PWM power supply circuit

The working process of PWM power supply
The specific working process of PWM power supply can be subdivided into four stages:
Before T1,the dead time,the top tube and down tube are cut off,at this time,the top and down tube
drive signals are low level,and two tubes are cut off.
The period of timeT1 ,the top tube drive signal is high level,the down tube drive signal is low
level,at this time,the top tube is conducted,and the down tube is cut off.VIN voltage through the D-
S pole of the top tube and L1,then flows through the
load,and flows to the ground finally,when the current flows
through the inductance,produces the positive on the left and
the negative on the right induced voltage on the inductance.
Figure 9-3 the waveform of the top and down tube
drive signal
The period of time T1～T2,at this time,closes the top tube,the current flowed through the
inductance disappeared suddenly,because of the inductive effect of the inductance,both ends of the
inductance will produce a reverse voltage,the direction of this voltage is the positive on the right
and the negative on the left.The enlarged drawing of the top and down tube signal waveform is
shown in figure 9-3,after UGATE becoming to be low,LGATE will be driven to be high after
delaying time,this period of time is also the dead time.
The period of time T2,at this time,the top tube drive is low level,and the down tube drive is
high level.So the top tube is cut off,the down tube is conducted,the induced voltage with the
positive on the right and the negative on the left inducted on the inductance through the right end
of L1 to the load,flows through the S-D pole of the down tube,then flows to the negative terminal
of the voltage,that is the left end of L1.
The real object of the single phase PWM circuit is shown in figure 9-4,is usually used
for the memory power supply,the bridge power supply,the bus power supply,the graphics
card power supply and others.
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Figure 9-4 the real object of the single phase PWM circuit
The real object of the multiphase PWM circuit is shown in figure 9-5,is usually used for the
CPU core power supply.
Figure 9-5 the real object of the multiphase PWM circuit
The meaning of common English abbreviation in PWM circuit

SKIP、SKIPSEL:the work mode setting.
TON、RT、FS:the frequency setting(set the frequency by the resistance connecting the
ground or the power supply).
BOOT、BST、BOOST:boot-strap pin,the power source of the G pole of the top tube.
UGATE、DH、HDRV、DRVH:the top tube drive.
LGATE、DL、LDRV、DRVL:the down tube drive.
FB:the feedback adjusting pin.
COMP:feedback compensation,correct the error of the feedback circuit.
OUT、VOUT、VO:output voltage detection input pin.
PHASE、SW、LX:the phase pin,connects the S pole of the top tube/the D pole of the down
tube/the inductance,forms the loop with BOOT,and some can be the current detection.
CSP/CSN:the current detection pin.
ILIM、TRIP、CS:the over current protection threshold value setting,the limited current
setting.
The boot-strap circuit
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In the PWM power,the top tube is usually N channel,the output voltage is from the common
point.Because the power chip is limited to the driving ability of the top tube,and almost all of the chips
are used the boot-strap circuit to improve the driving ability.The name of boot-strap pin are usually
BOOT,BST,BOOST.PWM circuit using the method of boot-strap is shown in figure 9-6.
As the figure 9-6 an example,explains the principle of boot-strap:
B+ of 19V supplies power to the high-end tube PQ5,at this time,the G pole is no power,so the
S pole outputs 0V.At the same time,B+ of 19V is input to PU3,the internal produces the linear
voltage VL with 5V,through the internal diode supplies power to BOOT1,if skips the pressure
drop,its still 5V,added to 1 pin of PC33,to charge it,the capacitor stored 5V voltage.
BOOT1 of 5V supplies the power to UGATE1,sends the high level about 5V,is sent to the G
pole of PQ5,at this time,the G pole of the moment PQ5 is 5V,the S pole is 0V,the channel of PQ5
can be conducted completely,19V flows through PQ5 and PL4 to charge PC35,the voltage output
by PQ5 is gradually increased.
Figure 9-6 PWM circuit using the boot-strap
method
When the voltage output by PQ5 is gradually

increased,if this voltage is 2V,and 2V is added to 2 pin
of the capacitance PC33 at the same time,because of
the feature of the capacitance,it just stores the power
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with 5V,at this time,adds 2V,so,the left of the capacitance (that is BOOT1)will become to be 7V,and
7V continues to supply power to UGATE1,the G pole of PQ5 will also become to be 7V,keeps PQ5
VG>VS,and is higher than 4.5V,PQ5 keeps conducted completely,the voltage of the S pole will also
follow to rise,adds again to PC33.So,we can measured the square wave with the highest 19V and the
lowest 0V on the left of PL4.Because the power of the capacitance PC33 always not be discharged,the
voltage of BOOT1 will forever be higher than the left of PL4 to 5V,that is 19+5=24V,the waveform of
UGATE1 is also that the lowest is 0V,and the highest is 24V.
Output voltage regulation circuit
As shown in figure 9-7,through two sampling resistance connected by FB feedback pin
dividing into voltage,compared with the internal reference voltage,so as to realize the output
voltage regulation.The computational formula is
VOUT=FB×(1+R1/R2)
If FB=0.8V,R1is equal to R2,then VOUT=1.6V。
PWM power needs to detect at any time that if the output voltage meets the required
standard,avoids that the output voltage is too high or the output voltage is too low.In the figure 9-
8,OUT pin is used for the output voltage detection.
Figure 9-8 the figure of the voltage and current detection circuit
When the output voltage is over voltage,the chip internal uses OVP(over voltage
protection);when the output voltage is too low,the chip internal uses UVP(low-voltage
protection).3.3V of standby voltage over-voltage protection waveform is shown in figure 9-9.
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Figure 9-9 .3.3V of standby voltage over-voltage protection waveform
PWM power needs to detect the output current at any time .When its over-current,the chip
internal starts using OCP(over-current
protection)mechanism.There are two methods of detecting
current:
As shown in figure 9-8,PWM chip can detect the
current through CSH,CSL pin:series a milliohm
resistance,CSH detects the resistance input end
voltage,CSL detects the resistance output end voltage.To
calculate the differential pressure at both ends of the
resistance,divides the the resistance value to get the current,the computational formula is
I=(CSH−CSL)/R.
Figure 9-10 the figure of the current detection
As shown in figure 9-10,no CSH and CSL chip,it can detect through the down tube between
PHASE pin and PGND pin:after the down tube conducting,the resistance value is dozens of
millionhm,detects conducted voltage drop of the down tube to get the current.By this method to
detect the current,its not very precise.During calculating,we should use the maximum value of the
worst case in the data manual of the field effect transistor,and considers that the resistance value
after the field effect transistor conducting will be increased with the rising of the temperature,so its
also need the certain allowance.The benefit of this way is reliable,and its the nondestructive over-
current detection.
When the output voltage is over or the output current flows through,the chip will use the internal
output discharging mode.In this mode,the top tube G pole driver signal is turned off to be 0V low
level,the G pole driver signal of the down tube is driven to 5V high level,at this time,the top tube is cut
off,the down tube continues to be conducted,the charge stored on the output filter capacitance is
quickly discharged to the ground through the down tube,the output voltage is closed.
Special reminder:in the PWM circuit,is strictly prohibited to remove the chip then power
up.The G pole of the top tube is suspended,which will cause that VIN is added to the rear stage
directly,and burns the components.
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In the laptop,most of PWM power IC can work in the different two modes,PWM mode and
SKIP (pulse separation mode),the purpose is to adapt to different sleep state,and outputs the
different current(output voltage constant).There is SKIP# in the chip,is used to realize the mode
switch,when SKIP# is low,the chip works in the pulse separation mode(SKIP mode),at this
time,the output current is small,such as 3V standby voltage,it just needs to work in the SKIP mode
when in the standby mode.But after powering on,the output current of 3V standby voltage must be
increased,because some of the system voltage at this time is from the 3V standby voltage
conversion,so that the output current must be increased,SKIP#(usually controlled by SLP_S3# sent
by ICH) of the chip is high,the chip works in PWM mode,the output voltage is constant,but the
output current is greatly increased.
In PWM mode,the voltage load capacity is strong,the output current is large.The waveform in
PWM mode is shown in figure 9-11,the frequency is 299.4kHz.
Within the unit time,the less the PWM waveform,the smaller the output current.The
waveform in SKIP# mode is shown in figure 9-12,the frequency is just 34.63kHz.
Figure 9-11 the waveform in PWM mode
Figure 9-12 the waveform in SKIP mode
Analysis of the standby power chip

Analysis of MAX8734A
MAX8734A(is in common use with MAX1999) is the standby power
chip with high efficiency and four of the output produced by MAXIM
company to use for the laptop.The main features:not need the current
detection resistance;1.5% output voltage accuracy;supplies the linear
output with 3.3V and 5V;the maximum current with 100mA;can output
two path of PWM power supply:3.3V and 5V;the operating voltage range
of 4.5～24V;the choice of the pulse mode and PWM mode;over-voltage
and under-voltage protection.
Figure 9-13 the pin name of MAX8734A(the top view)
The introduction of the pin definition and common used pin
80
The pin name of MAX8734A is shown in figure 9-13.

The definition of the pin function of MAX8734A is shown in table 9-1.
Table 9-1 the definition of the pin function of MAX8734A
1 the vacant pin
2 the power good,open drain output.If the output of any path is forbidden or the output is 10%
lower than the standard value,PGOOD is pulled low.
3 3.3V SMPS enable input.ON3 connects to REF,3.3VSMPS will start after 5V SMPS being
stable.
4 5V SMPS enable input.ON5 connects to REF,5V SMPS will start after 3.3V SMPS being
stable.
5 3.3V SMPS current limit adjustment
6 shutdown control input.The main switch of the chip,the opening of the linear voltage.
7 3.3V SMPS feedback input.FB3 connects GND to choose the fixed output 3.3V,FB3 connects
to the resistance divider between OUT3 and GND,it can achieve the adjustable output of 2～5.5V.
8 2V reference voltage output.It can only provide 100 current,and it will lead to lower output
accuracy with REF load.
9 5V SMPS feedback input.FB5 connects GND to choose the fixed output 5V,and connects
FB5 to the resistance divider between OUT5 and GND,it can achieve the adjustable output of
2～5.5V.
10 over-voltage and under-voltage protection enable pin.When PRO# connects VCC,forbids the
protection.PRO# connects the ground,then opens the protection function
11 5V SMPS limit current regulation.
12 low noise mode control.When SKIP# connects the ground,works in the idle mode,when
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SKIP# connects VCC,works in the PWM mode,when SKIP# connects REF or is vacant,works in
the ultrasonic mode.
13 frequency selective input.When TON connects VCC,chooses 200/300kHz working
mode,when it connects the ground,chooses 400/500kHz working mode(respectively corresponding
the switching frequency of 5V,3.3V SMPS)
14 the bootstrap capacitor connection terminal of 5V SMPS
15 the inductance connected 5V SMPS.Its the internal low-end power supply rail of DH5.LX5
is the current detection input of 5V SMPS
16 the high-end G pole driver of 5V SMPS
17 the analog supply voltage input of PWM core.It needs a 1 capacitor bypass
18 5V linear regulation output.It can provide 100 current.If the voltage of OUT5 end is higher
than the LDO5 switch threshold,then LDO5 regulator is turned-off,and LDO5 connects to OUT5
through a small resistance.
19 the low-end tube G pole driver of 5V SMPS
20 the main power input
21 5V SMPS output voltage detection input.When the voltage of this pin is higher than 4.56V,it
will replace the internal LDO5 output.
22 3.3V SMPS output voltage detection input.When the voltage of this pin is higher than
2.91V,it will replace the internal LDO3 output.
23 ground connection
24 the low-end G pole driver of 3.3V SMPS
25 3.3V linear regulator output.It can provide 100mA current.If the voltage of OUT3 terminal
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is higher than the LDO3 switch threshold,then LDO3 regulator is turned-off,and LDO3 connects to
OUT3 through a small resistance.
26 the high-end G pole driver of 3.3V SMPS
27 the inductance connected 3.3V SMPS.Its the current detection input of 3.3V SMPS
28 the bootstrap capacitor connection terminal of 3.3V SMPS

脚名
定义
位称
1 N.C. 空脚
电源好，开漏输出。如果任一路输出被禁止或输出比标准值低
2 PGOOD
10%，PGOOD 被拉低
3.3V SMPS 使能输入。将 ON3 与 REF 相连，3.3V SMPS 会在 5V
3 ON3
SMPS 稳定后启动
5V SMPS 使能输入。将 ON5 与 REF 相连，5V SMPS 会在 3.3V
4 ON5
SMPS 稳定后启动
5 ILIM3 3.3V SMPS 限流调节
6 SHDN 关断控制输入。芯片的总开关，线性电压的开启
3.3V SMPS 反馈输入。将 FB3 连接 GND 选择固定输出 3.3V，将
7 FB3 FB3 连接至 OUT3 和 GND 之间的电阻分压器，能够实现 2～5.5V
的可调输出
2V 基准电压输出。只可提供 100µA 电流，用 REF 带负载会导致
8 REF
输出精度降低
5V SMPS 反馈输入。将 FB5 连接 GND 选择固定输出 5V，将
9 FB5 FB5 连接至 OUT5 和 GND 之间的电阻分压器，能够实现 2～5.5V
的可调输出
过压和欠压保护使能脚。PRO#接 VCC 时，禁止保护。PRO#接
10 PRO
地时，开启保护功能
11 ILIM5 5V SMPS 限流调节
低噪声模式控制。SKIP#接地时，工作在空闲模式，SKIP#接
12 SKIP VCC 时工作在 PWM 模式，SKIP#接 REF 或悬空时，工作在超声模
式
频率选择输入。TON 接 VCC 时，选择 200/300kHz 工作模式，接
13 TON 地时选择 400/500kHz 工作模式（分别对应 5V、3.3V SMPS 的开关
频率）
续表
脚名
定义
位称
83
14 BST5 5V SMPS 的自举电容连接端

连接 5V SMPS 的电感。是 DH5 的内部低端电源轨。LX5 是 5V
15 LX5
SMPS 的电流检测输入
16 DH5 5V SMPS 的高端管 G 极驱动
17 VCC PWM 核的模拟电源电压输入。需要一个 1μF 电容旁路
5V 线性稳压器输出。可提供 100mA 电流。如果 OUT5 端电压高
18 LDO5 于 LDO5 开关门限，那么 LDO5 稳压器关断，并且 LDO5 通过一个
小电阻连接到 OUT5
19 DL5 5V SMPS 的低端管 G 极驱动
20 V+ 主电源输入
5V SMPS 输出电压检测输入。当此脚电压超过 4.56V 时，会替代
21 OUT5
内部 LDO5 输出
3.3V SMPS 输出电压检测输入。当此脚电压超过 2.91V 时，会替
22 OUT3
代内部 LDO3 输出
23 GND 接地
24 DL3 3.3V SMPS 的低端管 G 极驱动
3.3V 线性稳压器输出。可提供 100mA 电流。如果 OUT3 端电压
25 LDO3 高于 LDO3 开关门限，那么 LDO3 稳压器关断，并且 LDO3 通过一
个小电阻连接到 OUT3
26 DH3 3.3V SMPS 的高端管 G 极驱动
27 LX3 连接 3.3V SMPS 的电感。是 3.3V SMPS 的电流检测输入
28 BST3 3.3V SMPS 的自举电容连接端
The electrical features of SHDN# threshold value in the MAX8734A data manual are
described as shown in figure 9-14.
The screenshot of the description of the electrical features of SHDN# threshold value of
MAX8734A
SHDN# input threshold value level:the lowest value of the rising edge is 1.2V,usually is
1.6V,the maximum is 2.0V.
SHDN# input threshold value level:the lowest value of the falling edge is 0.96V,usually is
1.00V,the maximum is 1.04V.
In the MAX8734A data manual,the electrical features of ON3 and ON5 threshold value is
described as shown in figure 9-15.
84
Figure 9-15 the screenshot of the description of the electrical features of the open signal
threshold value in the MAX8734A data manual
Explanation
ON3 and ON5 input voltage:when its less than 0.8V,the switching power supply is turned off.
ON3 and ON5 input voltage:when it is 1.7～2.3V,delays start.
ON3 and ON5 input voltage:when its higher than 2.4V,opens directly.
In the MAX8734A data manual,the electrical features of over-voltage protection threshold
value described as shown in figure 9-16.When the output voltage is higher than the set voltage to a
certain value,then it will start the over-voltage protection:the minimum value is 8%,usually is
11%,the maximum value is 14%.For example,sets to be 3.3V,achieves 3.3+3.3*11%=3.663V,then
to protect.
Figure 9-16 the screenshot of the description of the electrical features of the over-voltage
protection in the MAX8734A data manual
In the MAX8734A data manual,the electrical features of the output under-voltage protection
threshold value described as shown in figure 9-17.If the output voltage can only reach 70%(the
common value) of the set voltage,then it will start the under-voltage protection.
Figure 9-17 the screenshot of the description of the electrical features of the under-voltage
protection threshold value in the MAX8734A data manual
The switching circuit of OUT,LDO5 and OUT3,LDO3 is shown in figure 9-18:when OUT5/3
is higher than 4.56/2.91V,it will replace the internal linear voltage output.
Output voltage regulation
FB3/FB5 connects to the ground,you can choose a fixed output 3.3V and 5V.If FB3/FB5
connects to the resistance divider between OUT3/OUT5 and the ground,then it can adjust the
output in the range of 2～5.5V.The specific calculation formula is VOUT=VFB*(R1+R2)/R2,is shown
in figure 9-19.
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Figure 9-18 the switching graph of OUTx and LDOx of MAX8734A
Figure 9-19 the output voltage regulation diagram of MAX8734A
The typical application diagram is shown in figure 9-20.

First,V+ inputs,V+ through the resistance divider input or the high level sent by the external
acts the open for SHDN#,MAX8734A will produce LDO5,the internal structure is shown in figure
9-21.
Figure 9-20 the typical application diagram of MAX8734A
86
Figure 9-21 the internal block diagram of MAX8734A

LDO5 supplies power to VCC,is shown in figure 9-22.
After VCC input being sent MAX8734A,the chips produce 2V reference voltage REF,is
Figure 9-22 the relationship between LDO5 of MAX8734A with VCC
Figure 9-23 the production of the reference voltage of MAX8734A
After REF being stable,outputs the linear voltage LDO3 of 3.3V.The timing sequence
waveform of V+,LDO5,LDO3 is shown in figure 9-24.
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Figure 9-24 the timing sequence of the linear voltage of MAX8734A
ON5 connects VCC,ON3 connects REF,is shown in figure 9-25,so,the chip produces PWM
power supply of 5V first,after being stable,then produces PWM power supply of 3.3V.
FB3 and FB5 are connected the ground,is shown in figure 9-26,chooses the fixed output 3.3V
and 5V.After all outputs being stable,the chip open drain outputs PGOOD finally,is pulled up by
the VCC through 100kΩ.
Figure 9-25 the origin of the opening signal
Figure 9-26 FB setting
Control timing relationship

The original of MAX8734A control timing relationship in English is shown in table 9-2.
Table 9-2 MAX8734A control timing relationship(the original in English)
Explanation
88
If SHDN# is low level,then,no matter what ON3 and ON5 is,the linear 5V,linear 3V,5V
switching power supply and 3V switching power supply will be closed,there is no output.
If SHDN# is higher than 2.4V,and ON3 and ON5 are low level,the linear 5V and linear 3V
will be opened(the linear 3V will start after REF being stable),5V and 3V switching power supply
are closed.
If SHDN# is higher than 2.4V,ON3 and ON5 are high level,LDO5,LDO3,5V switching
power supply and 3V switching power supply will be opened,there is a voltage output.
If SHDN# is higher than 2.4V,ON3 is high level,ON5 is low level,the linear 5V,the linear 3V
and 3V switching power supply are opened,5V switching power supply is closed.
If SHDN# is higher than 2.4V,ON3 is low level,ON5 is high level,the linear 5V,the linear 3V
and 5V switching power supply are opened,3V switching power supply is closed.
If SHDN# is higher than 2.4V,ON3 is high level,ON5 connects REF pin,the linear 5V,the
linear 3V and 3V switching power supply are opened,5V switching power supply will start after
3V being stable.
If SHDN# is higher then 2.4V,ON3 connects REF pin,ON5 is high level,the linear 5V,the
linear 3V and 5V switching power supply are opened,3V switching power supply will start after
5V being stable.
TPS51125 is an economical and efficiency dual channel synchronous buck controller
produced by TI in the US to use for the standby voltage of the laptop.The voltage is 5.5～28V,the
output voltage is 2～5.5V adjustable,with 5V and 3.3V two path of 100mA linear voltage output
and 2V reference voltage output with internal error 1%,integrates the over-voltage,under-voltage
and over-current protection,with the function of over-heat protection.It provides VCLK output of
270kHz to use to drive the external bootstrap circuit,in the case of no reduction in the working
efficiency of the main converter to generate the gate drive voltage for the rear power conversion
switch.TPS51125 supports efficient,fast transient response and provides a combination of enable
signal.Out-of-Audio™ mode light load operation realizes low noise,and its efficiency is higher
than the traditional mandatory PWM.
The introduction of the pin definition and the common pin
The name of the pin of TPS51125 is shown in figure 9-27.
89
Figure 9-27 the name of the pin of TPS51125(the top view)

The pin definition of TPS51125 is shown in table 9-3.
Table 9-3 the pin definition of TPS51125
1 Channel 1 open and current limit set pin.The direct grounding closes the output,sets the
threshold value of the over-current through the resistance grounding
2 the feedback of channel 1
3 2V reference voltage output
4 the frequency setting
5 the feedback of channel 2
6 channel 2 open and current limit pin.The direct grounding closed the output,sets the threshold
value of the over-current through the resistance grounding
7 channel 2 output voltage detection.The function:① voltage detection;②is used to replace the
linear voltage
8 the linear voltage output of 3.3V
9 the starting pin of channel 2,boot-strap terminal
10 the top tube drive of channel 2
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11 the phase pin of channel 2.Function:①the top tube conducts the loop;②the current detection
12 the down tube drive of channel 2.
13 the main starting signal.Function:①open the linear when its vacant,ready to open VCLK
and PWM;②only open the linear when through the resistance grounding,close VCLK and ready to
open PWM;③direct grounding,close the whole chip.
14 PWM mode and pulse mode select pin
16 the main power supply input,is the origin of the linear voltage power supply
17 the linear voltage output of 5V
18 the frequency output of 270kHz,is used for the boot-strap circuit of 15V
19 the down tube drive of channel 1
20 the phase pin of channel 1.Function:①the top tube conducts the loop;②the current detection
21 the top tube drive of channel 1
22 the starting pin of channel 1,the boot-strap terminal
23 the power good output,open drain output
24 the voltage detection of channel 1.Function:①voltage detection;②is used to replace the
linear voltage
脚位名称定义
通道 1 开启和限流设定脚。直接接地关闭输出，通过电阻接地
1 ENTRIP1
设定过流阈值
2 VFB1 通道 1 的反馈
3 VREF 2V 基准电压输出
4 TONSEL 频率设定
5 VFB2 通道 2 的反馈
通道 2 开启和限流设定脚。直接接地关闭输出，通过电阻接地
6 ENTRIP2
设定过流阈值
91
通道 2 输出电压检测。作用：①电压检测；②用于替换线性电
7 VO2
压
8 VREG3 3.3V 的线性电压输出
9 VBST2 通道 2 的启动脚，自举升压端
10 DRVH2 通道 2 的上管驱动
11 LL2 通道 2 的相位脚。作用：①上管导通回路；②电流检测
12 DRVL2 通道 2 的下管驱动
主开启信号。作用：①悬空时打开线性，准备打开 VCLK 和
13 EN0 PWM；②通过电阻接地时，只打开线性，关闭 VCLK 和准备打
开 PWM；③直接接地，关闭整个芯片
14 SKIPSEL PWM 模式和跳脉冲模式选择脚
15 GND 接地
16 VIN 主供电输入，是线性电压的供电来源
17 VREG5 5V 的线性电压输出
18 VCLK 270kHz 频率输出，用于 15V 自举升压电路
19 DRVL1 通道 1 的下管驱动
20 LL1 通道 1 的相位脚。作用：①上管导通回路；②电流检测
21 DRVH1 通道 1 的上管驱动
22 VBST1 通道 1 的启动脚，自举升压端
23 PGOOD 电源好输出，开漏输出
24 VO1 通道 1 的电压检测。作用：①电压检测；②用于替换线性电压
In the TPS51125 data manual,the threshold value of EN0 described as shown in figure 9-
28:when the voltage of EN0 is less than 0.4V,the chip will be closed;when the voltage of EN0 is
higher than 0.8V,opens the linear and closes VCLK;when the voltage of EN0 is higher than
2.4V,opens the linear and VCLK.
Figure 9-28 the screenshot of the description of electrical features of EN0 threshold value in the
TPS51125 data manual
In the TPS51125 data manual,the threshold value of ENTRIP# described as shown in figure 9-
29:the minimum value of the turn-off level threshold value of ENTRIP1 and ENTRIP2 is 350mV,the
general value is 400mV,the maximum value is 450mV;the minimum value of the hysteresis is
10mV,which means that the minimum value of the open level is 360mV,the general value is 30mV,that
is 430mV,the maximum value is 60mV,that is 510mV.
92
Figure 9-29 the screenshot of the description of the electrical features of EN pin threshold value
of TPS51125
The equivalent circuit of the ENTRIPx in the chip is shown in figure

9-30.
TPS51125 produces REF first,then produces VREG*,is shown in
figure 9-31,after EN being produced,VIN converts to be VREF
first,then VREF is input to the inverted input terminal of the
comparator of VREG5 and VREG3,controls the production of
VREG5 and VREG3.
In the TPS51125 data manual,the electrical features of VCLK described as shown in figure 9-
32:VCLK is the waveform of 270kHz,is 4.92V in the high level,is 0.06V in the low level(the
typical value).
Figure 9-31 the internal schematic diagram of the production of VREF and VREG* in the
Figure 9-32 the screenshot of the description of the electrical features of VCLK in the
The schematic diagram of the boot-strap of TPS51125 VCLK is shown in figure 9-

33.First,VCLK is low level,VO1 charges C1 through D0,5V.When VCLK comes,4.92V add
5V(ignore the diode voltage drop) is 10V.The voltage of 10V flows through D1 and C3 voltage
rectifier filter,then charges C2 through D2.Add again is 15V,outputs 15V(the measured voltage is
between 12～14V) through D4 and C3 rectifier filter.
93
Figure 9-33 the boot-strap circuit of 15V
The original table in English of the open signal control relationship of TPS51125 is shown in
figure 9-4.
Table 9-4 the signal control relationship of TPS51125(the original table in English)
Explanation
When EN0 is ground connection,no matter what the state of ENTRIP1 and ENTRIP2
is,VREF,VREG5,VREG3,channel 1,channel 2 and VCLK are closed.
When EN0 is ground connection through the resistance,and ENTRIP1 and ENTRIP1 are low
level,VREF,VREG5,VREG3 are opened,channel 1,channel 2,VCLK are closed.
When EN0 is ground connection through the resistance,ENTRIP1 is high,ENTRIP2 is
low,channel 2 and VCLK are closed,others are opened.
When EN0 is ground connection through the resistance,ENTRIP1 is low,ENTRIP2 is
high,channel 1 and VCLK are closed,others are opened.
When EN0 is ground connection through the resistance,ENTRIP1 and ENTRIP2 are
high,VCLK is closed,others are opened.
When EN0 is vacant,ENTRIP1 and ENTRIP2 are low,two channels and VCLK are closed,others
are opened.
When EN0 is vacant,ENTRIP1 is high,ENTRIP2 is low,only channel 2 is closed,others are
opened.
When EN0 is vacant,ENTRIP1 is low,ENTRIP2 is high,channel 1 and VCLK are closed,others
94
are opened.
When EN0 is vacant,ENTRIP1 and ENTRIP2 are high,all of them are opened.
Analysis of RT8206A/RT8206B
RT8206A/RT8206B is the standby power supply chip produced by RichTek,the internal of
the chip includes a linear voltage regulator module,which provides the output of 5V 70mA.It can
provide a fixed output the adjustable voltage of 3.3V and 5V or 2V to 5.5V.The range of the main
power supply input:6～25V.
The introduction of the pin definition and the common pin
The top view of the pin name of RT8206A/RT8206B is shown in figure 9-34.
Figure 9-34 the pin name of RT8206A/B(the top view)

The definition of the pin function of RT8206A/RT8206B is shown in table 9-5.
Table 9-5 the pin definition of RT8206A/RT8206B
1 2.0V reference voltage output terminal
2 the switching frequency setting terminal,connects VCC(200kHz/250kHz),connects

REF(300kHz/375kHz),connects GND(400kHz/500kHz)
3 the switching power supply input,connects the capacitor of 1μF directly with the
ground
4 LDO module open signal input,in the high level,LDO/REF is opened,in the low
level,LDO/REF is closed
5 the vacant pin
6 the input of the chip main power supply
7 5V 70mA LDO voltage output,after the system power supply 5V being produced,LDO
module is closed,and through internal switch of 1.5converts to 5V power supply produced
by external SMPS
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8 the vacant pin
9 the voltage output by connecting 5V SMPS,is used to convert LDO voltage output
10 SMPS1 output voltage detection
11 SMPS1 feedback input.When FB1 connects to VCC or the ground wire,SMPS1 is the
fixed output 5V voltage mode;when FB1 connects to the resistance partial pressure between
VOUT1 and the ground,you can set the output voltage to be 2～5.5V
12 SMPS1 output current threshold setting
13 SMPS1 power good signal output,when SMPS1 output voltage is less than the standard
7.5%,this signal becomes to be the low level
14 SMPS1 enable signal input.If EN1 is high level,SMPS1 is opened,if its low level,SMPS1
is closed.If connects to REF,SMPS1 is opened after SMPS2 working
15 high-end OSFET driver signal output terminal
16 the connecting end of SMPS1 output inductance
17 the connecting end of SMPS1 boost capacitor
18 the output terminal of low-end MOSFET driver signal
19 the input terminal of 5V power supply
20 the connecting end of 14V boost feedback;（RT8206B）is vacant pin
21 ground terminal
22 ground terminal
23 the output terminal of low-end MOSFET driver signal
24 the connecting end of SMPS2 boost capacitor
25 the connection of SMPS2 output inductance
26 the output terminal of high-end MOSFET driver signal
27 the input terminal of SMPS2 enable signal
28 the output terminal of SMPS2 power good signal
29 SMPS working mode setting end.connect the ground:custom mode.Connect

REF:ultrasonic mode.Connect VCC:PWM mode
30 SMPS2 output voltage detection
31 SMPS2 output current threshold setting
96
32 SMPS2 feedback input.When connects FB2 to VCC or the ground wire,SMPS2 is the
fixed output 3.3V voltage mode.connects FB2 to the resistance partial pressure between
VOUT2 and the ground,you can set the output voltage to be 2～5.5V
脚名
定义
位称
1 REF 2.0V 基准电压输出端
开关频率设置端，接 VCC（200kHz/250kHz），接
2 TON
REF（300kHz/375kHz），接 GND（400kHz/500kHz）
3 VCC 开关电源供电输入，与地直接连接一个 1μF 的电容
ENLD LDO 模块开启信号输入，高电平，LDO/REF 开启，低电平，
4
O LDO/REF 关闭
5 NC 空脚
6 VIN 芯片主供电的输入
5V 70mA LDO 电压输出，当系统供电 5V 产生后，LDO 模块关闭，
7 LDO
并通过内部 1.5Ω的开关切换到由外部 SMPS 产生的 5V 供电
续表
脚名
定义
位称
8 NC 空脚
9 BYP 连接 5V SMPS 输出的电压，用于切换 LDO 电压输出
VOUT
10 SMPS1 输出电压检测
1
SMPS1 反馈输入。连接 FB1 到 VCC 或地线时，SMPS1 为固定输出
11 FB1 5V 电压模式；连接 FB1 到 VOUT1 与地之间的电阻分压，可以设置输
出电压为 2～5.5V
12 ILIM1 SMPS1 输出电流门限设置
PGOO SMPS1 电源好信号输出，当 SMPS1 输出电压低于标准 7.5%时，此
13
D1 信号将变为低电平
SMPS1 使能信号输入。如果 EN1 为高电平，SMPS1 开启，低电平，
14 EN1
SMPS1 关闭。如果连接到 REF，SMPS2 工作后开启 SMPS1
UGAT
15 高端 MOSFET 驱动信号输出端
E1
PHAS
16 SMPS1 输出电感连接端
E1
BOOT
17 SMPS1 升压电容连接端
1
LGAT
18 低端 MOSFET 驱动信号输出端
E1
19 PVCC 5V 供电输入端
SECF
20 （RT8206A）14V 升压反馈连接端；（RT8206B）空脚
B
97
21 GND 接地端
22 PGND 接地端
LGAT
23 低端 MOSFET 驱动信号输出端
E2
BOOT
24 SMPS2 升压电容连接端
2
PHAS
25 SMPS2 输出电感连接
E2
UGAT
26 高端 MOSFET 驱动信号输出端
E2
27 EN2 SMPS2 使能信号输入端
PGOO
28 SMPS2 电源好信号输出端
D2
SMPS 工作模式设置端。接地：自定义模式。接 REF：超声波模式。
29 SKIP
接 VCC：PWM 模式
VOUT
30 SMPS2 输出电压检测
2
31 ILIM2 SMPS2 输出电流门限设置
SMPS2 反馈输入。连接 FB2 到 VCC 或地线时，SMPS2 为固定输出
32 FB2 3.3V 电压模式；连接 FB2 到 VOUT2 与地之间的电阻分压，可以设置
输出电压为 2～5.5V
In the RT8206 data manual,the threshold value of ENx and ENLDO described as shown in
figure 9-35.
Figure 9-35 the screenshot of the description of the electrical features of ENx and ENLDO
threshold value of RT8206
The explanation is below.

When ENx is less than 0.8V,closes SMPS;between 1.8～2.3V,delay starts;when its higher than
2.5V,opens SMPS.
ENLDO,the minimum value of the rising edge(from low level to high level) is 1.2V,the
typical value is 1.6V,the maximum value is 2.0V.
ENLDO,the minimum value of the falling edge(from high level to low level) is 0.49V,the
typical value is 1V,the maximum value is 1.06V.
The original in English of control timing sequence of RT8206A/RT8206B is shown in table
9-6.
98
Table 9-6 the control timing sequence of RT8206A/RT8206B(the original in English)
Explanation
When ENLDO is low,no matter what the state of EN1 and EN2 is,LDO and 3V,5V switching
power supply are closed.
When ENLDO is high lever more than 2V,EN1 and EN2 are low level,LDO is output after
REF being stable,5V,3V switching power supply are closed.
When ENLDO is higher level more than 2V,EN1 is low,EN2 connects REF pin,LDO is
output after REF being stable,5V,3V switching power supply are closed.
When ENLDO is high level more than 2V,EN1 is low,EN2 is high,LDO is output after REF
being stable,5V switching power supply is closed,3V switching power supply is opened.
When ENLDO is high level more than 2V,EN1 connects REF pin,EN2 is low,LDO is output
after REF being stable,5V,3V switching power supply are closed.
When ENLDO is high level more than 2V,EN1 connects REF pin,EN2 also connects REF
pin,LDO is output after REF being stable,5V,3V switching power supply are closed.
When ENLDO is high level more than 2V,EN1 connects REF pin,EN2 is high,LDO is output
after REF being stable,3V is opened directly,5V is output after 3V being stable.
When ENLDO is high level more than 2V,EN1 is high,EN2 is low,LDO is output after REF
being stable,5V is opened,3V is closed.
When ENLDO is high level more than 2V,EN1 is high,EN2 connects REF pin,LDO is output
after REF being stable,5V is opened directly,3V is output after 5V being stable.
When ENLDO is high level more than 2V,EN1 is high,EN2 is also high,LDO is output after
REF being stable,5V,3V are opened directly.
Analysis of the memory power supply chip
Analysis of ISL88550A
Used for the power supply chip ISL88550A of the memory power supply,it can output one
path of PWM(the memory main power supply) and two path of LDO(the memory REF power
99
supply and VTT power supply).

The name of the pin of ISL88550A is shown in figure 9-36.
Figure 9-36 the name of the pin of ISL88550A(the top view)
The definition of the pin function of ISL88550A is shown in table 9-7.
Table 9-7 the table of the pin definition of ISL88550A
1 frequency selection:TON connects AVDD(200kHz),when its in vacant,connects
REF(450kHz),connects the ground(600kHz)
2 over-voltage/under-voltage protection control input.Connects AVDD(open the over-voltage
protection and the discharging mode,open the under-voltage protection).When its in vacant(open
the over-voltage protection and the discharging mode,close the under-voltage protection),connects
REF(close the over-voltage protection and the discharging mode,open the over-voltage
protection),connects the ground(close the over-voltage protection and the discharging mode,close
the under-voltage protection)
3 2V reference voltage output
4 the limiting current setting
5 PWM power good
100
6 LDO power good
7 when STBY# is low,VTT will be closed,is the high resistance state
8 soft start
9 VTT voltage detection input
10 the terminal reference voltage,the value is the same with VTT
12 the terminal voltage output,connects to VTTS to keep it to be half of VREFIN
13 the input voltage of VTT voltage regulator,in the application of the memory power
supply,will usually connect it to PWM output terminal
14 the external reference voltage input,is used to adjust VTT and VTTR,the voltage output by
them is the half of REFIN
15 the feedback of PWM.When it connects AVDD,fix output 1.8V,when it connects the
ground,fix output 2.5V.If its adjusted by the resistance partial pressure,it can output the voltage
between 0.7～3.5V
16 the output voltage detection input of PWM
17 the main power supply input,the range of 2～25V
18 the top tube driver of PWM
19 the phase pin of PWM.the function of the top tube drive loop and the current detection
20 the boot-strap terminal
21 the down tube driver of PWM
22 the power supply of the chip,the origin of the driving force of the down tube
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25 the working mode setting.when it connects AVDD,low noise forced PWM mode,when
connects the ground,jump pulse mode
26 the main power supply of LDO and PWM
27 turn-off the control input A,the rising edge clear fault latch,connects the high level open chip
28 the test pin

脚名
定义
位称
频率选择：TON 连接 AVDD（200kHz），悬空时（300kHz），连接
1 TON
REF（450kHz），接地（600kHz）
过压/欠压保护控制输入。连接 AVDD（开启过压保护和放电模式,
开启欠压保护）
OVP/UV
2 悬空时（开启过压保护和放电模式，关闭欠压保护），连接 REF（关
P
闭过压保护和放电模式，开启欠压保护），接地（关闭过压保护和放
电模式、关闭欠压保护）
3 REF 2V 基准电压输出
4 ILIM 极限电流设定
5 POK1 PWM 电源好
续表
脚名
定义
位称
6 POK2 LDO 电源好
7 STBY# 当 STBY#为低时，VTT 会被关闭，呈高阻态
8 SS 软启动
9 VTTS VTT 电压检测输入
10 VTTR 终端基准电压，值与 VTT 一样
11 PGND2 接地
12 VTT 终端电压输出，连接到 VTTS 使之保持为 VREFIN 的一半
VTT 稳压器的输入电压，在内存供电应用中，通常会把它连接到
13 VTTI
PWM 输出端
外部基准电压输入，用于调节 VTT 和 VTTR，它们输出的电压为
14 REFIN
REFIN 的一半
15 FB PWM 的反馈。接 AVDD 时固定输出 1.8V，接地时固定输出
102
2.5V。通过电阻分压调节的话，可以输出 0.7～3.5V 之间的电压

16 OUT PWM 的输出电压检测输入
17 VIN 主供电输入，2～25V 范围
18 UGATE PWM 的上管驱动
19 PHASE PWM 的相位脚。上管驱动回路以及电流检测作用
20 BOOT 自举升压端
21 LGATE PWM 的下管驱动
22 VDD 芯片的供电，下管的驱动动力的来源
23 PGND1 接地
24 GND 接地
工作模式设定。连接 AVDD 时低噪声强制 PWM 模式，连接地时
25 SKIP#
跳脉冲模式
26 AVDD LDO 和 PWM 模块的主供电
SHDNA
27 关断控制输入 A，上升沿清除故障锁存器，连接高电平开启芯片
#
28 TP0 测试脚
The original in English of the control logical relationship between SHDN# and STBY# of
ISL88550 is shown in table 9-8.
Table 9-8 the open signal control relationship of ISL88550(the original in English)
Explanation
When SHDNA# connects the ground,no matter what the state of STBY# is,PWM,VTTR are
closed,VTT is also closed(discharge to 0V).
When SHDNA# connects AVDD,STBY# connects the ground,PWM and VTTR are
opened,VTT will be closed(the high resistance state).
When SHDNA# and STBY connects AVDD,PWM,VTT,VTTR are opened.
The typical application of ISL88550A is shown in figure 9-37.
103
Figure 9-37 the typical application of ISL88550A
The specific working process:

5V supplies power to 22V,4.5～25V supplies power to 17 pin.
3 pin produces 2V reference voltage.
The South bridge sends the high level of SLP_S5#/SLP_S4# to 27 pin SHDNA#.
PWM is opened,outputs VDDQ,1.8V(FB connects AVDD,sets to be the fixed output 1.8V).
VDDQ is returned to OUT detection,the chip outputs POK1;at the same time,VDDQ supplies
power to REFIN.
Output VTTR,the voltage is the half of REFIN,that is 0.9V(as shown in figure 9-39,after
REFIN entering the chip,through two of 10kΩ resistance series divides into the voltage to be
0.9V,then outputs VTTR with 0.9V through voltage follower).At the same time,the chip outputs
POK2.
The South bridge sends the high level of SLP_S3# to STBY# pin.
Outputs a voltage from the external to 13 pin VTTI as the power supply of VTT regulator.
Outputs VTT,the voltage is the half of REFIN,0.9V.
104
Figure 9-38 the screenshot of the internal relationship of REFIN and VTT,VTTR of
ISL88550A
Another common memory power supply chip RT8207,is also responsible to output three
paths of power supply:the memory main power supply,the memory REF voltage,the memory VTT
voltage,the pin definition is shown in table 9-9.
Table 9-9 the pin definition of RT8207
1 the ground pin of the internal integrated VTT regulator
2 the voltage detection input pin of VTT output
3 the ground connection
4 output discharging mode setting pin.Connect to VDDDQ trace discharge;connect to the
ground,the non trace discharge;connect to VDD,not discharge
5 VTTREF voltage output pin,is sent to the memory reference voltage
6 the diode emulation mode open pin.Connect to VDD to open the diode emulation
mode;connect to the ground,is always working in the forced CCM mode
7 the vacant pin
8 the reference input pin of VTT and VTTREF.The output voltage of VTT and VTTREF is the
half of VDDQ.If FB connects VDD or GND,VDDQ can be acted as the output voltage feedback
input pin
105
9 VDDQ(PWM) output voltage setting pin.Connects to GND,outputs 1.5V;connects to
VDD,outputs 1.8V;it can set the adjustable output voltage between 0.75～3.3V through the
resistance partial pressure
10 SLP_S3# sent by the South bridge,is used to control the output of VTT
11 SLP_S5# sent by the South bridge,is used to control the output of PWM and VTTREF
12 connects to VIN through a resistance,sets the frequency
13 the open drain output pin of the power good,it means that PWM control output VDDQ
voltage has normal
14 the power supply
15 the power supply
16 connects to VDD through a resistance,sets the limited current
17 the vacant pin
18 the ground connection(the ground connection of the driver of the down tube)
19 the down tube drive
20 the phase pin.It can be used as the current detection pin:detects the current through the
detection of the pressure drop of the down tube.
21 the top tube drive
22 the boot-strap pin
23 the power supply of the regulator of VTT
24 the output of VTT

脚名
定义
位称
1 VTTGN 内部集成的 VTT 稳压器的接地脚
106
D
VTTSN
2 VTT 输出的电压检测输入脚
S
3 GND 接地
输出放电模式设定脚。连接到VDDQ 跟踪放电；连接到地，非跟踪
4 MODE
放电；连接到 VDD，不放电
VTTRE
5 VTTREF 电压输出脚，给内存基准电压
F
二极管仿真模式开启脚。连接到VDD 开启二极管仿真模式；连接到
6 DEM
地，始终工作在强制CCM 模式
7 NC 空脚
VTT 和 VTTREF 的基准输入脚。VTT 和 VTTREF 的输出电压是
8 VDDQ VDDQ 的一半。如果 FB 接 VDD 或 GND，VDDQ 可以作为输出电
压反馈输入脚
VDDQ（PWM）输出电压设定脚。连接到 GND，输出 1.5V；连接
9 FB 到 VDD，输出 1.8V；通过电阻分压可以设定输出电压 0.75～3.3V 之
间可调
10 S3 南桥发来的 SLP_S3#，用于控制 VTT 的输出
11 S5 南桥发来的 SLP_S5#，用于控制 PWM 和 VTTREF 的输出
12 TON 通过一个电阻连接到 VIN，设定频率
续表
脚名
定义
位称
13 PGOOD 电源好开漏输出脚，表示 PWM 控制输出 VDDQ 电压已经正常了
14 VDD 供电
15 VDDP 供电
16 CS 通过一个电阻连接到 VDD，设定极限电流
17 NC 空脚
18 PGND 接地（下管的驱动器的接地）
19 LGATE 下管驱动
相位脚。可以作为电流检测脚：通过检测下管的导通压降检测电
20 PHASE
流
21 UGATE 上管驱动
22 BOOT 自举升压脚
VLDOI
23 VTT 的稳压器的供电
N
24 VTT VTT 的输出
The typical application of RT8207 is shown in figure 9-39.
107
Figure 9-39 the typical application of RT8207
The original in English of the control logical relationship between S3 and S5 of RT8207 is
shown in table 9-9.
Table 9-9 the control logical relationship of RT8207(the original in English)
Explanation
In the S0 state,S3 is high,S5 is high ——VDDQ,VTTREF,VTT are opened.
In the S3 state,S3 is low,S5 is high ——VDDQ and VTTREF are opened,VTT is closed(the
high resistance state).
In the S4/S5 state,S3 ans S5 are low ——VDDQ,VTTREF and VTT are closed(discharge to
the ground).
The working process of RT8207 is shown in figure 9-40.
108
Figure 9-40 the working process of RT8207
Analysis of the bridge/bus power supply chip

The bridge power supply and the bus power supply chip is relatively simple,is usually used a
single PWM or dual PWM controller.
Analysis of the single PWM controller RT8209
常用的单 PWM 控制器 RT8209 可用于桥供电、总线供电、内存主供电等很多电路。注
意：RT 系列芯片本体一般都不会有真实型号，只有产品代号。例如，RT8209BGQW，芯
片本体只有“A0=”字样，如图 9-41 所示。此类芯片的实际型号识别需要下载RT 芯片的封
装文件，目前最新流传出的最新版本是09 年的，文件名为
Richtek_Marking_Code_090424.PDF，可以在迅维网（www.chinafix.comThe common single
PWM controller RT8209 can be used for the bridge power supply,bus power supply,the memory main
power supply and other circuits.Note:RT series chip body usually do not have a real model,only the
product code.For example,RT8209BGQW,the chip body is only the word “A0=”,is shown in figure 9-
41.About the actual type recognition of this series chip,you need to download the packaging file of RT
chip,at present,the latest version of the new efferent is 2009,the name of this field is
Richtek_Marking_Code_090424.PDF,you can download in the website:www.chinafix.com.
Figure 9-41 the mark of RT8209 series chip body
The pin definition of RT8209 series chip is shown in figure 9-42.
109
Figure 9-42 the pin definition of RT8209 series chip (the top view)
The important pin:in addition to the PWM related pin,the power supply pin VDD,VDDP are
usually connected to 5V,CS is the current limit set,TON is the frequency setting,the definition of
the open pin EN/DEM is the start using/the diode emulation mode control input(the threshold
value of EN/DEM in RT8209 data manual described as shown in figure 9-43).Connected to
VDD,is the diode emulation mode,connected to the GND turn off chip,is CMM(the continuous
current) mode when its vacant.Generally,its the vacant state during working,and is the ground state
when its turned off.
Figure 9-43 the screenshot of the description of the electrical features of EN/DEM pin threshold
value in RT8209 data manual
The application of RT8209A/B/C is shown in figure 9-44,the description of the working

process is below.
The power supply inputs 4.5～5.5V to VDD,VDDP pin,pulls up TON pin through the
resistance to set the frequency,and pulls down CS pin through the resistance to set the limited
current.
EN inputs the high level,or the external circuit is disconnected,makes it to be vacant.
Starts PWM,outputs VOUT.
Detect the voltage from VOUT pin.
Open drain output PGOOD,is pulled up to be the high level by VDDP.
110
Figure 9-44 the application of RT8209A/B/C
Analysis of the dual PWM controller TPS51124

The input voltage range of the dual PWM power supply chip TPS51124 which is commonly
used in the bridge power supply and the bus power supply is
from 3V to 28V,and the output voltage range is from
0.76V to 5.5V.
The pin name of TPS51124 is shown in figure 9-45.
The explanation of the important pin:15 pin and 16 pin
are the power supply,4 pin is the frequency selection,from 5
pin to 14 pin,are the first path of PWM power supply
control,the 1 pin,2 pin and from 17 pin to 24 pin,are the
second path of PWM power supply control,TRIP1/TRIP2 sets
respectively the over-current limit of the two path of
PWM,EN1/EN2 opens respectively the two path of PWM.
In the TPS51124 data manual,the power supply range of V5IN and V5FILT described as
shown in figure 9-46:the power supply range of V5IN and V5FILT is from 4.5V to 5.5V.
Figure 9-46 the screenshot of the description of the power supply range of V5IN and V5FILT
in the TPS51124 data manual

In the TPS51124 data manual,the threshold value of EN described as shown in figure 9-47,the
lowest threshold value of EN is 1V,is usually 1.3V,the maximum is 1.5V.
Figure 9-47 the screenshot of the description of the electrical feature of EN pin threshold value
111
In the TPS51124 data manual,the frequency setting described as shown in figure 9-48.
Figure 9-48 the screenshot of the description of the frequency setting of TPS51124
When TONSEL is the ground connection,the first path of PWM works in 240kHz,the second
path of PWM works in 300kHz.
When TONSEL is vacant,the first path of PWM works in 300kHz,the second path of PWM
works in 360kHz.
When TONSEL connects V5FILT,the first path of PWM works in 360kHz,the second path of
PWM works in 420kHz.
In the TPS51124 data manual,the electrical features of FB pin described as shown in figure 9-
49.In the SKIP mode,the reference value of FB voltage regulation is 764mV,in the PWM mode,the
reference value is 758mV.the error precision is about 0.9% in 25℃,the error precision is about 1.3%
in 0～85℃,and the error precision is about 1.6% in -40～85℃.
Figure 9-49 the screenshot of the description of the electrical features of FB pin reference value

The typical application of TPS51124 is shown in figure 9-50.
112
Figure 9-50 the typical application of TPS51124

The description of the working process is below.
The power supply outputs 4.5～5.5V to 15 pin and 16 pin.
EN1 or EN2 input
Starts the first path of PWM or the second path of PWM.
Detect the voltage from VO1 or VO2.
Open drain output PGOOD1 or PGOOD2.
Analysis of CPU core power supply
CPU generally requires a number of power supply,for example,CPU of 478 needs three kinds of
power supply,the first generation I3/I5/I7 needs five kinds of power supply,but only VCC pin is the core
power supply.In this section,we mainly explains the working principle of several common CPU core
power supply chip.
The features of CPU VCORE power supply
The multiphase output is that the output of multiple current sources are connected
together,supplies power to CPU,which meets the demands of CPU large current.The real object of
two phase CPU power supply is shown in figure 9-51.
Since the working voltage required by CPU at the different times is different,so it needs the
control way to adapt automatically the requirements of the different CPU on the voltage,that is,the
VID control of the output voltage.
VID is the voltage identification technology,loaded with different CPU,it will produce the
different voltage.
VID can be divided into PVID(parallel VID) and SVID(serial VID).
Figure 9-51 the real object of two phase CPU power supply
AMD early and before Intel 5 series chipset(HM55,etc),are all belong to PVID.The basic principle
is that,sets 4～8 VID recognition pin on the CPU,and through the high and low level values preset in
these recognition pin,to form a group of VID recognition signal,when its high level on VID recognition
pin,then is the 1 state of the binary,and when its the low level on the VID recognition pin,is the 0 state of
the binary.According to the combination of these 1 and 0,forms the group of the most basic machine
language signal,and is transmitted to the power management chip in the CPU power supply circuit by
CPU,according to the VID signal,the power management chip adjusts the duty cycle of the output pulse
113
signal,which forces the DC voltage output by CPU power supply circuit to be consistent with the value
represented by pre-set VID.
Intel company developed the corresponding voltage regulation module design specifications
for each CPU produced at different time,starts from the Prescott core microprocessor,the voltage
regulation specification used VRD(Voltage Regulation Down) to name,in the laptop,uses the
Voltage Mobile Positioning,the VID digit,the voltage regulation accuracy and the voltage
regulation range in the various version of the power supply design specification are not the same.
VID with this mode,can “cheat” the CPU to come out by loading the dummy load.After
loading the dummy load,connects one or more VID signal of VID0～VID7 to the ground,at this
time,VID0～VID7 pin of the power IC gets the new voltage combination,according to this
different combination,the power IC will control to send the corresponding voltage.That is to say,let
CPU power supply chip mistakenly assume that the true CPU is loading.
Starting from AM2+ CPU,CPU contains two parts of the voltage(AMD calls it to be Dual-
Plane),one is the core voltage of CPU,one is the voltage of the North bridge integrated in CPU.A
group of parallel VID control modules can not asynchronous control these two voltages at the
same time,unless provides a group of parallel VID again to control the voltage of the North bridge
in CPU,but this will be more complex.So AMD launched a new generation of voltage regulation
module specification,using serial VID(SVID) mode to solve this problem.Serial VID is a type of
bus protocol.From the hardware point of view,the required external interface is from the previous
VID0～VID5 a total of 6 becoming into SVC(serial clock),SVD(serial data),it’s very
simple.However,because the serial VID is the bus working mode,so it needs the cooperation of the
software,but it also means that the operability adjusted latter will be stronger.Most of the previous
AMD motherboard used PVI/SVI compatible of PWM controller in order to to compatible with
AM2/AM2+/AM3.
Intel integrated the display core in Core i3/i5/i7 matched with 5 series platform,in order to
control these two groups of power supply better,so provides two groups of PVID interface to
control respectively the core voltage of CPU and the display core voltage,these two groups of
voltages are accord with the specification of Intel VRD11.1,which is more complex.
Starting from 6 series platform,Intel imports VRD12 specification,that is the serial VID
mode,its exactly the same with AMD SVI mode.There are three lines of SVID of Intel
platform:SVD(serial VID data),(SVC serial VID clock),ALERT#(warning signal).
Analysis of MAX8770
MAX8770 is the control chip produced by MAXIM company,which is used for the CPU core
power supply,in accordance with the IMVP-6 specification,the main features are as follow.
Support two phase CPU power supply.
Support 7 bit VID,the output voltage is adjusted from 0V to 1.5000V.
Support for dynamic phase adjustment and sleep.
Integrated driver IC.
With power ready (PWRGD) output and clock enable(CLKEN#) output.
114
With the power monitoring and over-heat protection.

Support 4～26V input voltage range.
Output over-voltage protection.
The pin name of MAX8770 is shown in figure 9-52,the real object of MAX8770 is shown in
figure 9-53.
Figure 9-52 the pin name of MAX8770(the top view)
Figure 9-53 the real object of MAX8770

The pin definition of MAX8770 is shown in table 9-11.
Table 9-11 the pin definition of MAX8770
1.the output of the clock enable logic signal.When the output voltage detected from FB pin reaches
the specified value,this pin outputs the effective logic low level.
2.the power good signal of the open drain output.When the output voltage detected from FB pin
reaches the specified value,this pin open drain outputs the high level.
3.this low voltage logic signal and DPRSLPVR commonly set the power mode.If PSI# is low,then
enter the PWM mode of N-1 phase.When PSI# is high,then recovery the PWM mode of N phase.
4.power monitor output
5.the open drain output pin of the internal comparator.When the voltage of THRM terminal is less
than 1.5V(30%VCC),VRHOT# is pulled low.Its the high resistance at shutdown
6.the input terminal of the internal comparator.Connects one end of the thermistor(usually is NTC)
115
to the ground,and another end to THRM,and through a resistance to VCC at the same time.By
selecting the proper device,at the required temperature,the voltage of THRM end is reduced to less
than 1.5V.
7.the voltage slew rate(is the rate of voltage swing)control pin.TIME connects a resistance to the
ground,used to set the internal slew rate.The application of the voltage slew rate contains:the chip
enter or exit the pulse interval mode,the chip enter VID MODE from BOOTMODE.For the soft
start and shutdown process,the chip reduced automatically the slew rate to 1/8.
8.the switching frequency setting pin.The switching frequency is set by a resistance connecting to
the power supply end and the TON end.
9.the capacitor connection of the voltage integrator.
10.the current balance compensation
11.2.0V reference voltage output,through a maximum of 1μF capacitor bypass to the ground.REF
can provide 500µA current to the external loads.
12.the feedback input.The external resistance capacitance element is used for detecting the output
voltage.
13.the negative of the inductance input end of the feedback bypass.Connects to GND of the load
end in general.
14.the positive input end of the second phase output current detection.This pin must be connected
to the positive end of the output current sense resistor.Connects the PIN pin to VCC,the second
phase is closed.
15.the negative input end of the second phase output current detection.This pin must be connected
to the negative end of the output current sense resistor.Under the case of the DC inductance of the
output inductance being used as the output current detection resistance,this pin is connected to the
116
output filter capacitor
16.the negative input end of the first phase output current detection.This pin must be connected to
the negative end of the output current sense resistor.Under the case of the DC inductance of the
output inductance being used as the output current detection resistance,this pin is connected to the
output filter capacitor
17.the positive input end of the first phase output current detection.This pin must be connected to
the positive end of the output current sense resistor.Connects this PIN pin to VCC,the first phase is
closed
18.simulated ground
19.the controller power supply pin.Connects the voltage end of 4.5～5.5V,through a minimum of
1μF bypass capacitor to connect to the ground
20.the boost resistor connection end of the second phase.It can set up the open signal for the top
tube on the DH2 through this signal,when the down tube is turned on,the internal switch between
VDD and BST2 charges the boost capacitor
21.the output end of the top tube drive signal of the second phase.The voltage values is changed
between LX2 and BST2.Its low in shutdown.
22.the connection end of the output inductance of the second phase.It sets up the opening voltage
on the DH2 for the top tube,acts as the input end of the zero crossing comparator of the second
phase at the same time
23.the second phase power ground.Its the ground end of DL2.It acts as the input end of the zero
crossing comparator of the second phase at the same time.
24.the output end of the down tube drive signal of the second phase.The voltage values is changed
between VDD and GND.DL2 is high in the shutdown.When the output voltage is abnormal,it has
117
been forced to be high.It also is low in the small load mode,until detecting the inductance current
9PGND2-LX2) zero crossing
25.the power supply pin of the down tube drive of each phase.It acts as the charging source of the
boost capacitor of each phase at the same time.This pin connects to the voltage source of
4.5～5.5V
26.the output end of the down tube drive signal of the first phase.The voltage values is changed
between VDD and GND.DL1 is high in the shutdown.When the output voltage is abnormal,it has
been forced to be high.It also is low in the small load mode,until detecting the inductance current
(PGND1-LX1) zero crossing
27.the power ground of the first phase.Its the ground end of DL1.It acts as the input end of the zero
crossing comparator of the first phase at the same time.
28.the connection end of the output inductance of the first phase.It sets up the opening voltage on
DH1 for the top tube,acts as the input end of the zero crossing comparator of the first phase at the
same time
29.the output end of the top tube drive signal of the first phase.The voltage values is changed
between LX1 and BST1.Its low in shutdown
30.the connection end of the boost resistance of the first phase.It can set up the open signal on
DH1 for the top tube through this signal,when the down tube is opened,the internal switch between
VDD and BST1 charges the boost capacitor
31-37.the input end of the low voltage VID digital signal.D0～D6 does not pull up in IC.The
digital logic signal is directly connected to the relevant interface of CPU.The output voltage is
controlled by VID.When VID is high,its turned off.When VID changes from high to other
value,IC starts to start the timing sequence immediately
38.the voltage open signal.When it connects VCC,uses the default mode.When it connects
118
GND,the chip enters into the close mode.During starting,the output voltage ramp slowly to the
start voltage(the voltage slew rate is 1/8).When the voltage is closed,uses the same voltage slew
rate to decline.The voltage of SHDN# pin can't be more than 13V,at this time,OVP and UVP
protection of the chip internal are closed
39.the input end of the depth sleep control.This signal and PSI# signal set commonly the power
mode
40.the deep sleep awaken signal.When this signal is low,it means that CPU is in a deep sleep state
脚名
定义
位称
时钟使能逻辑信号的输出。当从 FB 脚检测到的输出电压达到规定值
1 CLKEN
时，该脚输出有效逻辑低电平
PWRG 漏极开路输出的电源好信号。当从FB 脚检测到的输出电压达到规定值时，
2
D 该脚开漏输出高电平
该低电压逻辑信号与 DPRSLPVR 共同设置电源模式。若 PSI#为低，
3 PSI
则进入 N-1 相位的 PWM 模式。当 PSI#为高时恢复 N 相位 PWM 模式
4 POUT 电源监控输出
内部比较器的漏极开路输出脚。当 THRM 端电压低于
5 VRHOT
1.5V（30%VCC）时，VRHOT#拉低。关机时为高阻
内部比较器输入端。将一个热敏电阻（通常是NTC）一端接地，另一端
6 THRM 接 THRM，同时通过一个电阻接到VCC。通过选择适当的器件，使得在需
要的温度以上，THRM 端的电压降至1.5V 以下
电压摆率（电压摆率就是电压摆动的速率）调节引脚。TIME 对地接
一只电阻，用于设置内部摆率。电压摆率的应用含：芯片进入或退出脉
7 TIME
冲间隔模式、芯片从 BOOT MODE 进入 VID MODE。对于软启动和关
断过程，芯片自动将摆率降至 1/8
8 TON 开关频率设置脚。由一个电阻连接电源端与 TON 端来设置开关频率
续表
脚名
定义
位称
9 CCV 电压积分器电容连接端
10 CCI 电流平衡补偿
2.0V 基准电压输出，通过一个最大 1μF 电容旁路至地。REF 可为外
11 REF
部负载提供 500µA 电流
12 FB 反馈输入。其外接阻容元件用于检测输出电压
13 GNDS 反馈旁路感应器输入端的负极。通常连接至负载端的 GND
119
第 2 相输出电流检测正极输入端。该引脚须连接至输出电流检测电阻
14 CSP2
的正极。将此 PIN 脚接 VCC，第 2 相关闭
第 2 相输出电流检测负极输入端。该引脚须连接至输出电流检测电阻
15 CSN2 的负极。在输出电感的直流感抗被用作输出电流检测电阻的情况下，该
引脚接至输出滤波电容
第 1 相输出电流检测负极输入端。该引脚须连接至输出电流检测电阻
16 CSN1 的负极。在输出电感的直流感抗被用作输出电流检测电阻的情况下，该
引脚接至输出滤波电容
第 1 相输出电流检测正极输入端。该引脚须连接至输出电流检测电阻
17 CSP1
的正极。将此 PIN 脚接 VCC，第 1 相关闭
18 GND 模拟地
控制器供电脚。连接 4.5～5.5V 的电压端，通过最小 1μF 的旁路电容
19 VCC
接地
第 2 相升压电阻连接端。通过该信号可在 DH2 上为上管建立开启信
20 BST2
号，当下管开启时，在 VDD 与 BST2 之间的内部开关为升压电容充电
第 2 相上管驱动信号输出端。其电压值在 LX2 与 BST2 之间切换。关
21 DH2
机时为低
第 2 相输出电感连接端。在 DH2 上为上管建立开启电压，同时也作
22 LX2
为第 2 相过零点比较器的输入端
第 2 相电源地。为 DL2 的地端。同时也作为第 2 相过零点比较器的
23 PGND2
输入端
第 2 相下管驱动信号输出端。其电压值在 VDD 与 GND 中切换。DL2
24 DL2 在关机时为高。在输出电压异常时一直强制为高。在小负载模式下也为
低，直到检测到电感电流（PGND2-LX2）过零点
各相位下管驱动的供电脚。同时也作为各相升压电容的充电电源。该
25 VDD
引脚接至 4.5～5.5V 的电压源
第 1 相下管驱动信号输出端。其电压值在 VDD 与 GND 中切换。DL1
26 DL1 在关机时为高。在输出电压异常时一直强制为高。在小负载模式下也为
低，直到检测到电感电流（PGND1-LX1）过零点
第 1 相电源地。为 DL1 的地端。同时也作为第 1 相过零点比较器的
27 PGND1
输入端
第 1 相输出电感连接端。在 DH1 上为上管建立开启电压，同时也作
28 LX1
为第 1 相过零点比较器的输入端
第 1 相上管驱动信号输出端。其电压值在 LX1 与 BST1 之间切换。关
29 DH1
机时为低。
第 1 相升压电阻连接端。通过该信号可在 DH1 上为上管建立开启信
30 BST1
号，当下管开启时，在 VDD 与 BST1 之间的内部开关为升压电容充电
低压 VID 数字信号输入端。D0～D6 在 IC 内部没有上拉。该数字逻
31～37 D0～D6 辑信号直接与 CPU 相应接口连接。输出电压由 VID 控制。VID 全高时
关机。当 VID 由全高变为其他值时，IC 随即开始启动时序
电压开启信号。接 VCC 时使用默认操作模式。接 GND 时芯片进入关
38 SHDN 闭模式。启动过程中，输出电压缓慢斜线上升至启动电压（电压摆率为
1/8）。电压关闭时，使用同样电压摆率下降。SHDN#脚电压不能大于
120
13V，此时芯片内部 OVP 及 UVP 保护均关闭

DPRSL
39 深度休眠控制输入端。该信号与 PSI#信号共同设置电源模式
PVR
40 DPRSTP 深度休眠唤醒信号。该信号为低时代表 CPU 处于深度休眠状态
In the MAX8770 chip,the combination of DPRSLPVR and PSI# sets the power mode,is
Figure 9-54 the screenshot of the original of the combination of DPRSLRVR and RSI# setting
in the information of MAX8770 chip

When DPRSLPVR is high,PSI# is low,the chip working mode is that the current is very
small,the 1 phase jump pulse.
When DPRSLPVR is high,PSI# is high,the chip works in the 3A small current mode,the 1
phase jump pulse.
When DPRSLPVR is low,PSI# is low,the chip works in the PWM mode of 1 phase,the
current is moderate.
When DPRSLPVR is low,PSI# is high,the chip works in the PWM mode of the full phase,the
maximum current output.
The over-voltage protection:IC will detect if the output voltage meets the OVP standard or
not in real.When the output voltage is higher than the value of the output voltage current VID
corresponding 300mV(the typical value,is shown in figure 9-55),or is higher than 1.8V in the pulse
interval mode,IC starts OVP protection.When OVP is low in the multiphase mode(DPRSLPVR is
low and PSI# is high),IC pulls DL1 and DL2 high immediately,and pulls DH1 and DH2 low.It
makes the down tube driving signal duty ratio is 100%,the down tube is emptying the output
capacitor rapidly,the using output voltage is pulled low.
threshold value in MAX8770 data manual

The over-voltage protection:when the output voltage is less than the output voltage value
400mV(the typical value,is shown in figure 9-56) that VID corresponding to,IC starts
SHUTDOWN timing sequence and sets the fault latch until the output voltage as low as 0V.At this
time,IC will be forced to pull high DL1 and DL2,and pull DH1 and DH2 low.Pull the SHDN#
121
voltage clamp or VCC voltage down to less than 0.5V to clear the fault latch,and re-activate IC.
protection threshold value in the MAX8770 data manual

The operating voltage range of VCC and VDD is shown in figure 9-57.
Figure 9-57 the screenshot of the description of the electrical features of VCC pin and VDD pin
threshold value in the MAX8770 data manual

如图 9-58 所示为 MAX8770 的关键信号阈值的电气特性描述截图，
SHDN 、DPRSLPVR 超过 2.3V 为高电平（最大值），VID0～VID6、 PSI 、 DPRSTP As
shown in figure 9-58,is the screenshot of the description of the electrical features of the key signal
threshold value of MAX8770, SHDN and DPRSLPVR are the high level(the maximum value)
when its higher than 2.3V,VID0～VID6, PSI and DPRSTP are the high level(the minimum value)
when its higher than 0.67V,are the low level (the maximum value) when its less than 0.33V.
Figure 9-58 the screenshot of the description of the electrical features of the key signal
threshold value in the MAX8770 data manual

VID voltage corresponding of IMVP-6 specification is shown in table 9-12.
For example:when D6～D0 are the low level,the output voltage is 1.5000V;when D6 is the
low level,D5～D0 are the high level,the output voltage is 0.7125V;when D6～D0 are the high
level,the output voltage is 0V.
Table 9-12 the table 1 of VID corresponding of IMVP-6

输出输出
电压电压
D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0
（V （V
））
1.500 0.700
0 0 0 0 0 0 0 1 0 0 0 0 0 0
0 0
1.487 0.687
0 0 0 0 0 0 1 1 0 0 0 0 0 1
5 5
0 0 0 0 0 1 0 1.475 1 0 0 0 0 1 0 0.675
122
0 0
1.462 0.662
0 0 0 0 0 1 1 1 0 0 0 0 1 1
5 5
1.450 0.650
0 0 0 0 1 0 0 1 0 0 0 1 0 0
0 0
1.437 0.637
0 0 0 0 1 0 1 1 0 0 0 1 0 1
5 5
1.425 0.625
0 0 0 0 1 1 0 1 0 0 0 1 1 0
0 0
1.412 0.612
0 0 0 0 1 1 1 1 0 0 0 1 1 1
5 5
1.400 0.600
0 0 0 1 0 0 0 1 0 0 1 0 0 0
0 0
1.387 0.587
0 0 0 1 0 0 1 1 0 0 1 0 0 1
5 5
1.375 0.575
0 0 0 1 0 1 0 1 0 0 1 0 1 0
0 0
1.362 0.562
0 0 0 1 0 1 1 1 0 0 1 0 1 1
5 5
1.350 0.550
0 0 0 1 1 0 0 1 0 0 1 1 0 0
0 0
1.337 0.537
0 0 0 1 1 0 1 1 0 0 1 1 0 1
5 5
1.325 0.525
0 0 0 1 1 1 0 1 0 0 1 1 1 0
0 0
1.312 0.512
0 0 0 1 1 1 1 1 0 0 1 1 1 1
5 5
1.300 0.500
0 0 1 0 0 0 0 1 0 1 0 0 0 0
0 0
1.287 0.487
0 0 1 0 0 0 1 1 0 1 0 0 0 1
5 5
1.275 0.475
0 0 1 0 0 1 0 1 0 1 0 0 1 0
0 0
1.262 0.462
0 0 1 0 0 1 1 1 0 1 0 0 1 1
5 5
1.250 0.450
0 0 1 0 1 0 0 1 0 1 0 1 0 0
0 0
1.237 0.437
0 0 1 0 1 0 1 1 0 1 0 1 0 1
5 5
1.225 0.425
0 0 1 0 1 1 0 1 0 1 0 1 1 0
0 0
1.212 0.412
0 0 1 0 1 1 1 1 0 1 0 1 1 1
5 5
1.200 0.400
0 0 1 1 0 0 0 1 0 1 1 0 0 0
0 0
1.187 0.387
0 0 1 1 0 0 1 1 0 1 1 0 0 1
5 5
1.175 0.375
0 0 1 1 0 1 0 1 0 1 1 0 1 0
0 0
123
1.162 0.362
0 0 1 1 0 1 1 1 0 1 1 0 1 1
5 5
1.150 0.350
0 0 1 1 1 0 0 1 0 1 1 1 0 0
0 0
1.137 0.337
0 0 1 1 1 0 1 1 0 1 1 1 0 1
5 5
1.125 0.325
0 0 1 1 1 1 0 1 0 1 1 1 1 0
0 0
1.112 0.312
0 0 1 1 1 1 1 1 0 1 1 1 1 1
5 5
1.100 0.300
0 1 0 0 0 0 0 1 1 0 0 0 0 0
0 0
1.087 0.287
0 1 0 0 0 0 1 1 1 0 0 0 0 1
5 5
1.075 0.275
0 1 0 0 0 1 0 1 1 0 0 0 1 0
0 0
1.062 0.262
0 1 0 0 0 1 1 1 1 0 0 0 1 1
5 5
1.050 0.250
0 1 0 0 1 0 0 1 1 0 0 1 0 0
0 0
1.037 0.237
0 1 0 0 1 0 1 1 1 0 0 1 0 1
5 5
1.025 0.225
0 1 0 0 1 1 0 1 1 0 0 1 1 0
0 0
1.012 0.212
0 1 0 0 1 1 1 1 1 0 0 1 1 1
5 5
1.000 0.200
0 1 0 1 0 0 0 1 1 0 1 0 0 0
0 0
0.987 0.187
0 1 0 1 0 0 1 1 1 0 1 0 0 1
5 5
0.975 0.175
0 1 0 1 0 1 0 1 1 0 1 0 1 0
0 0
0.962 0.162
0 1 0 1 0 1 1 1 1 0 1 0 1 1
5 5
0.950 0.150
0 1 0 1 1 0 0 1 1 0 1 1 0 0
0 0
0.937 0.137
0 1 0 1 1 0 1 1 1 0 1 1 0 1
5 5
0.925 0.125
0 1 0 1 1 1 0 1 1 0 1 1 1 0
0 0
0.912 0.112
0 1 0 1 1 1 1 1 1 0 1 1 1 1
5 5
0.900 0.100
0 1 1 0 0 0 0 1 1 1 0 0 0 0
0 0
0.887 0.087
0 1 1 0 0 0 1 1 1 1 0 0 0 1
5 5
0.875 0.075
0 1 1 0 0 1 0 1 1 1 0 0 1 0
0 0
0 1 1 0 0 1 1 0.862 1 1 1 0 0 1 1 0.062
124
5 5
0.850 0.050
0 1 1 0 1 0 0 1 1 1 0 1 0 0
0 0
0.837 0.037
0 1 1 0 1 0 1 1 1 1 0 1 0 1
5 5
续表
输出输出
电压电压
D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0
（V （V
））
0.825 0.025
0 1 1 0 1 1 0 1 1 1 0 1 1 0
0 0
0.812 0.012
0 1 1 0 1 1 1 1 1 1 0 1 1 1
5 5
0.800
0 1 1 1 0 0 0 1 1 1 1 0 0 0 0
0
0.787
0 1 1 1 0 0 1 1 1 1 1 0 0 1 0
5
0.775
0 1 1 1 0 1 0 1 1 1 1 0 1 0 0
0
0.762
0 1 1 1 0 1 1 1 1 1 1 0 1 1 0
5
0.750
0 1 1 1 1 0 0 1 1 1 1 1 0 0 0
0
0.737
0 1 1 1 1 0 1 1 1 1 1 1 0 1 0
5
0.725
0 1 1 1 1 1 0 1 1 1 1 1 1 0 0
0
0.712
0 1 1 1 1 1 1 1 1 1 1 1 1 1 0
5
The application circuit of MAX8770 is shown in figure 9-59,several key working conditions
are indicated in the figure:
125
Figure 9-59 the typical application figure of MAX8770

The timing sequence of MAX8770 starting and closing is shown in figure 9-60.
126
Figure 9-60 the timing sequence of MAX8770 starting and closing
First,the chip gets the power supply,the internal will pull up CLKEN# to be high level.
Then,the external sends the high level of the open signal SHDN#.
VCORE soft starts to a certain voltage range first(the starting speed is 1/8 of the TIME pin
resistance setting the slew rate),forced PWM mode.
The chip starts to decode VID signal sent by CPU.
VCORE starts to the corresponding voltage set by VID.
After CPU soft start being normal,delays 60μs to set CLKEN# low.
After CPU power supply achieving the voltage set by VID,delays 5ms to set PWRGD
high(MAX8770 has not the PHASEGD signal).
SHDN# changes to be low level.
VCORE,CLKEN# and PWRGD are turned into the invalid state,PWM restores the forced
PWM mode,VID stops decoding.
When there is not VCC,CLKEN# also changes to be low level,the chip is outage.
Analysis of ISL6260
ISL6260 is the CPU power supply chip conformed the IMVP-6 specification,its main features
are as follows.
Precise multi phase kernel voltage regulator,supports for three-phase power supply,is
programmable;
7 bit of VID input recognition;
Support a variety of methods of the current detection;
Support PSI#;
Temperature monitoring;
Not integrated driver chip.
127
The pin name of ISL6260 is shown in figure 9-61.
Figure 9-61 the pin name of ISL6260(the top view)
The pin definition of ISL6260 is shown in table 9-13.
Table 9-13 the pin definition of ISL6260
1.low load current input indication,is effective in the low level.ISL6260 can be used to close the
PWM2
2.the high level input means that VCCP and VCC_MCH has been normal,this signal is the
precondition of CLK_EN# and PGOOD sent by ISL6260
3.through 147kΩbias resistance connect the ground,set the internal reference current
4.over-heat indication output,is effective in the low level
5.connecting to the negative temperature conefficient thermistor,as the part of the VR_TT# circuit
6.through a single capacitor set the maximum voltage conversion rate (the slew rate,the range of
the voltage increasing within 1s,its the time that the square-wave voltage rising from the trough
to the crest needs.the units are usually V/s,V/ms and V/μs)
7.the over-current setting input pin
8.through the resistance connect COMP to set the switch frequency
128
9.the error compensation,which is connected to the output end of the internal error amplifier
10.the feedback pin,which is connected to the inverting input end of the internal error amplifier
11.the output of the differential amplifier
12.the voltage detection,the plus end
13.the voltage detection,the negative end
14.the output end of the internal attenuation amplifier
15.the inverting input end of the internal attenuation amplifier
16.the input end of the output voltage detection
17.the total current detection
18.the power supply input
19.grounding
20.5V power supply input
21.the third phase current detection
22.the second phase current detection
23.the first phase current detection
24.the forced continuous conduction mode enable pin(forced PWM mode) of the driver chip
25.the third phase PWM output
26.the second phase PWM output
27.the first phase PWM output
28-34.the voltage recognition input pin
35.the opening signal,is effective in the high level
129
36.the high level means that its in the deep sleep mode
37.the low level means that its in the deep sleep mode
38.the opening signal of the clock chip,is effective in the low level.After PGD_IN and VCORE
being normal,then it will output
39.3.3V power supply of CLK_EN# circuit
40.the power good.open drain output,it needs to be pulled up by the external
脚
名称定义
位
低负载电流输入指示，低电平有效。ISL6260B 可用于关闭
1 PSI#
PWM2
高电平输入表示 VCCP 和 VCC_MCH 已经正常，此信号是
2 PGD_IN
ISL6260 发出 CLK_EN#和 PGOOD 的前提条件
3 RBIAS 通过 147kΩ偏置电阻接地，设定内部基准电流
4 VR_TT# 过热指示输出，低电平有效
5 NTC 连接负温度系数热敏电阻，作为 VR_TT#电路一部分
通过一颗电容设定最大的电压转换速率（压摆率，1µs 时间里
6 SOFT 电压升高的幅度，就是方波电压由波谷升到波峰所需时间，单位
通常有 V/s、V/ms 和 V/μs 三种）
7 OCSET 过流设定输入脚
8 VW 通过电阻连接 COMP 设定开关频率
9 COMP 误差补偿，连接内部误差放大器的输出端
10 FB 反馈脚，连接内部误差放大器的反相输入端
11 VDIFF 微分放大器的输出端
12 VSEN 电压检测，正端
13 RTN 电压检测，负端
14 DROOP 内部衰减放大器输出端
15 DFB 内部衰减放大器反相输入端
16 VO 输出电压检测输入端
17 VSUM 总电流检测
续表
脚
名称定义
位
18 VIN 供电输入
130
19 VSS 接地
20 VDD 5V 供电输入
21 ISEN3 第三相电流检测
22 ISEN2 第二相电流检测
23 ISEN1 第一相电流检测
24 FCCM 驱动芯片的强制连续传导模式使能引脚（强制 PWM 模式）
25 PWM3 第三相 PWM 输出
26 PWM2 第二相 PWM 输出
27 PWM1 第一相 PWM 输出
28～3 VID0～VI
电压识别输入脚
4 D6
35 VR_ON 开启信号，高电平有效
DPRSLPV
36 高电平表示处于深度睡眠模式
R
37 DPRSTP# 低电平指示处于深度睡眠模式
时钟芯片开启信号，低电平有效。它需要 PGD_IN 和 VCORE
38 CLK_EN#
都正常后才输出
39 3V3 CLK_EN#电路的 3.3V 供电
40 PGOOD 电源好。开漏输出，需要外部上拉
The original screenshot of the description of the electrical features of several key signals
threshold value of ISL6260 is shown in figure 9-62,the minimum of the rising edge threshold
value of VR_ON,DPRSLPVR and PGD_IN is 2.3V,the maximum of the falling edge threshold
value is 1V;the minimum of the rising edge threshold value of VID0-VID6,PSI# and DPRSTP# is
0.7V,the maximum of the falling edge threshold value is 0.3V.
Figure 9-62 the original screenshot of the description of the electrical features of VR_ON and
other key signals threshold value of ISL6260

As shown in figure 9-63,when all VID of ISL6260 are 0V,the maximum of the output voltage
of VCC_CORE is 1.5B;when VID is 1100000,the output voltage of VCC_CORE is 0.3V,when all
VID are 1V,VCC_CORE outputs 0V.
Figure 9-63 the original screenshot of the decoding range of ISL6260VID
PGD_IN mainly controls PGOOD logic circuit,is shown in
131
figure 9-64,after CPU power supply being normal,the logic circuit of PGOOD needs to receive
PGD_IN,then it will send PGOOD,and sends to the logic circuit of CLK_EN# at the same time,the
circuit of CLK_EN# must receive the power supply of 3V3,then it will send CLK_EN#.So,no
PGD_IN will not cause no CPU power supply,it will only cause no output of PGOOD,no 3V3 will
not cause PGOOD does not output,it will only cause CLK_EN# does not output low level.
The simplified application diagram and the key pin of ISL6260 are shown in figure 9-65.
Figure 9-64 the internal logic figure of PGOOD and CLK_EN# of ISL6260
VIDs
开启
Figure 9-65 the simplified application diagram and the key pin of ISL6260
132
The start timing sequence of ISL6260 is shown in

figure 9-66.
The chip gets the power supply first,including
VDD and VIN.
The high level of VR_ON sent from the external.
After delaying 100μs,the chip starts soft start
VCORE to 1.2V,the starting speed is 2mV/μs.
After VCORE starting to 1.2V,and PGD_IN
is high,the chip will send low level of CLK_EN#.
The chip decodes VID,drives VCORE to the
voltage set by VID according to IMVP-6 standard,the
starting speed is 10mV/μs.
7ms later,the chip outputs PGOOD.
Figure 9-66 the starting timing sequence figure of ISL6260
The set voltage
Analysis of commonly used chip ISL95831 by HM65 motherboard
ISL95831 is the controller supported three phase CPU core power supply and 1 phase
integrated graphics power supply,is mainly used for HM6x and above platform of Intel,in
compliance with the IMVP-7/VR12 specification,is TQFN packaged,48 pin.The main
features are as follow.
Support dual output:the first path of the voltage regulator can be configured as 3 phase,2
phase and single phase;the second path of the voltage regulator supports a single phase
output.
Two path of output shared SVID control.
Integrated three driver chips(the first path has two,the second path has one).
Support a kinds of methods of current measurement.
Support the over-heat and over-current protection.
133
Figure 9-67 the pin name of ISL95831(the top view)

1.this pin is connected to the COMPG by a resistance to set the switching frequency of the voltage
regulator 2(8kΩ resistance is about 300kHz)
2.the analog output.The output current and the current of the voltage regulator 2 forms a certain
proportion
3.the open drain output pin of the power good.Indicates that the voltage regulator 2 has
normal.The external needs to be pulled up by the resistance
4,5,6.the communication bus between CPU and the power management chip,serial VID bus
7.the enable pin of the controller.The high level is turned on.
8.the open drain output of the power good.Indicates that the voltage regulator 1 has normal.The
external needs to be pulled up by the resistance
9.the analog output.The output current and the current of the voltage regulator 1 forms a certain
proportion
134
10.over-heat indication signal
11.connects the ground through a negative temperature coefficient thermistor,used to monitor the
temperature of the voltage regulator 1
12.connects this pin to COMP through a resistance to set the switching frequency of the voltage
regulator 1(8kΩ resistance is about 300kHz)
13.the output end of the error amplifier of the first path of the voltage regulation
14.the inverting input end of the error amplifier of the voltage regulator 1
15.when the voltage regulator 1 is configured as a 3 phase,is used to detect the current of the third
phase.When its configured as 2 phase,the internal connects the switch of FB2 and FB,is used to
adjust the precision of the compensation voltage regulator 1.When its configured as 1 phase,the
switch is invalid
16.the second phase current detection of the voltage regulator 1
17.the first phase current detection of the voltage regulator 1
18.the input end of the voltage detection of the voltage regulator 1
19.the loop end of the voltage detection of the voltage regulator 1
20,21.the input pin of the droop current detection of the first path of regulator
22.5V power supply
23.the power supply
24.the maximum output current of the voltage regulator 1 and VBOOT voltage of the two path of
regulator are configured by the resistance connecting to the ground
25.the first phase boot-strap pin of the voltage regulator 1.Through a resistance connects the
PHASE pin of the first phase
135
26.the first phase of the top tube drive signal of the voltage regulator 1
27.the first phase of the top tube driver loop of the voltage regulator 1,connects the S pole of the
top tube,the D pole of the down tube and the output inductance
28.the first phase of the down tube driver loop of the voltage regulator 1,connects to the S pole of
the down tube
29.the first phase of the down tube drive signal of the voltage regulator 1
30.the third phase of the square wave output of the voltage regulator 1.When it connects to
5V,disable the third phase
31.the power supply of the internal driver chip,connects to +5V,at least is 1μF decoupling
capacitors
32.the second phase of the down tube drive signal of the voltage regulator 1
33.the second phase of the down tube driver loop of the voltage regulator 1,connects to the S pole
of the down tube
34.the second phase of the top tube driver loop of the voltage regulator 1,connects the S pole of the
top tube,the D pole of the down tube and the output inductance
35.the second phase of the top tube drive signal of the voltage regulator 1
36.the second phase of the boot-strap pin of the voltage regulator 1.Connects the PAHSE pin of
the second phase through a capacitor
37.the down tube drive signal of the voltage regulator 2
38.the top tube driver loop of the voltage regulator 2,connects the S pole of the top tube,the D pole
of the down tube and the output inductance
39.the top tube drive signal of the voltage regulator 2
136
40.the boot-strap pin of the voltage regulator 2.Connects the PHASEG pin through a capacitor
41.the maximum output current and the maximum limit temperature of the two regulators are
configured by a resistance connecting the ground
42.through a negative temperature coefficient thermistor,used to monitor the temperature of the
voltage regulator 2
43,44.the input pin of the droop current detection of the second path of the regulator,when
ISUMNG is connected to 5V,it will disable the second path of the voltage regulator
45.the loop end of the voltage detection of the voltage regulator 2
46.the input end of the voltage detection of the voltage regulator 2
47.the inverting input end of the error amplifier of the voltage regulator 2
48.the output end of the error amplifier of the second path of the voltage regulation
脚名
定义
位称
通过一个电阻把这个脚连接到 COMPG 用于设置电压调节器 2 的开关
1 VWG
频率（8kΩ 电阻大概 300kHz）
IMON
2 模拟输出。输出的电流与电压调节器 2 的电流成一定比例
G
PGOO
3 电源好开漏输出脚。指示电压调节器 2 已经正常。外部需电阻上拉
DG
4 SDA
ALERT
5 CPU 和电源管理芯片之间的通信总线，串行 VID 总线
#
6 SCLK
7 VR_ON 控制器的使能脚。高电平开启
PGOO
8 电源好开漏输出脚。指示电压调节器 1 已经正常。外部需电阻上拉
D
续表
脚名
定义
位称
9 IMON 模拟输出。输出的电流与电压调节器 1 的电流成一定比例
VR_HO
10 过热指示信号
T#
11 NTC 通过一个负温度系数热敏电阻接地，用于监控电压调节器 1 的温度
12 VW 通过一个电阻把这个脚连接到 COMP 用于设置电压调节器 1 的开关
137
频率（8kΩ 电阻大概 300kHz）

13 COMP 第一路电压调节的误差放大器输出端
14 FB 电压调节器 1 的误差放大器反相输入端
当电压调节器 1 配置为 3 相时用于检测第三相的电流。当配置为 2
ISEN3/F
15 相时，内部连接 FB2 和 FB 脚的开关用于调节补偿电压调节器 1 的精
B2
度。当配置为 1 相时，开关无效
16 ISEN2 电压调节器 1 的第二相电流检测
17 ISEN1 电压调节器 1 的第一相电流检测
18 VSEN 电压调节器 1 的电压检测输入端
19 RTN 电压调节器 1 的电压检测回路端
20 ISUMN
第一路调节器下垂电流检测输入脚
21 ISUMP
22 VDD 5V 供电
23 VIN 供电
通过一个电阻连接到地配置电压调节器 1 的最大输出电流，以及两
24 PROG1
路调节器的 VBOOT 电压
电压调节器 1 的第一相自举升压脚。通过一个电容连接第一相的
25 BOOT1
PHASE 脚
UGATE
26 电压调节器 1 的第一相上管驱动信号
1
电压调节器 1 的第一相上管驱动器回路，连接上管 S 极、下管 D 极
27 PHASE1
和输出电感
28 VSSP1 电压调节器 1 的第一相下管驱动器回路，连接到下管的 S 极
29 LGATE1 电压调节器 1 的第一相下管驱动信号
30 PWM3 电压调节器 1 的第三相方波输出。当连接到 5V 时，禁用第三相
31 VCCP 内部驱动芯片的供电，连接到+5V，至少要有 1μF 去耦电容
32 LGATE2 电压调节器 1 的第二相下管驱动信号
33 VSSP2 电压调节器 1 的第二相下管驱动器回路，连接到下管的 S 极
电压调节器 1 的第二相上管驱动器回路，连接上管 S 极、下管 D 极
34 PHASE2
和输出电感
UGATE
35 电压调节器 1 的第二相上管驱动信号
2
电压调节器 1 的第二相自举升压脚。通过一个电容连接第二相的
36 BOOT2
PHASE 脚
LGATE
37 电压调节器 2 的下管驱动信号
G
PHASE 电压调节器 2 的上管驱动器回路，连接上管 S 极、下管 D 极和输出
38
G 电感
UGATE
39 电压调节器 2 的上管驱动信号
G
40 BOOTG 电压调节器 2 的自举升压脚。通过一个电容连接 PHASEG 脚
通过一个电阻接地配置电压调节器 2 的最大输出电流，以及两个调
41 PROG2
节器的最高限定温度
42 NTCG 通过一个负温度系数热敏电阻接地，用于监控电压调节器 2 的温度
138
ISUMN
43 第二路调节器下垂电流检测输入脚，当把 ISUMNG 接到 5V，将禁
G
用第 2 路电压调节器
44 ISUMPG
45 RTNG 电压调节器 2 的电压检测回路端
46 VSENG 电压调节器 2 的电压检测输入端
47 FBG 电压调节器 2 的误差放大器反相输入端
48 COMPG 第二路电压调节的误差放大器输出端
In the ISL95831 data manual,the screenshot of the description of the input level threshold
value of VR_ON is shown in figure 9-68,the maximum value of VR_ON in the low level is
0.3V,in the ISL95831HRTZ,the minimum value of VR_ON in the high level is 0.7V,in the
ISL95831IRTZ,the minimum value of VR_ON in the high level is 0.75V.
Figure 9-68 the screenshot of the description of the electrical features of VR_ON threshold
value in the ISL95831 data manual

The simplified application circuit of ISL95831 is shown in figure 9-69.
139
开启
Figure 9-69 the simplified application figure of ISL95831
Three power supplies
SVID waveform
starting
140
The configuration of PROG1 pin of ISL95831 is shown in table 9-15.
Table 9-15 the configuration of PROG1 in the ISL95831 data manual(the original in English)
Give some examples to explain:

When PROG1 pin connects the ground through 0Ωresistance,the voltage of VBOOT is
0V,when CPU power supply outputs three-phase,two-phase and one-phase,the maximum current
are respectively 99A,66A and 33A.
When PROG1 connects the ground through 24.15kΩ or infinitely-great resistance,the voltage
of VBOOT is 1.1V,when CPU power supply outputs three-phase,two-phase and one-phase,the
maximum are respectively 99A,66A and 33A.
The configuration of PROG2 of ISL95831 is shown in table 9-16.
Give some examples to explain:
When PROG2 connects the ground through 0Ω resistance,the value of the over-temperature
protection of the chip is 120℃,the maximum of the output current of the second path of the
voltage regulator is 33A.
When PROG2 pin connects the ground through 24.15kΩor infinitely-great resistance,the
value of the over-temperature protection of the chip is 95℃,the maximum value of the output
current of the second path of the voltage regulator is 33A.
141
The waveform of SVID is shown in figure 9-70,the channel 1 is SCK,the channel 2 is SVD.
Table 9-16 the configuration of PROG2 pin in the ISL95831 data manual
The starting timing sequence of ISL95831 is shown in figure 9-71.
Figure 9-70 the waveform of SVID
Figure 9-71 the starting timing sequence of ISL95831

The starting procedure of ISL95831:
ISL95831 gets VDD and VIN,the chip power on reset(POR),to enter the standby state.the
threshold value of VDD is 4.5V(the maximum value),the threshold value of VIN is 4.35V(the
maximum value).
ISL95831 get the opening signal VR_ON,when the voltage value of this pin reaches to
0.7V(the minimum value of ISL95831HRTZ),starts soft start.
The internal DAC voltage starts to rise as the slope of 2.5mV/µs.
142
When DAC voltage rises to the value set by the RPROG1 resistance,the soft start is over.
ISL95831 open drain outputs PGOOD,and pulls ALERT# low to send to CPU.
CPU sends a serial VID signal to ISL95831.
According to the serial VID signal setting,ISL95831 adjusts and outputs the CPU core power
supply to the corresponding value(VID setting is shown in table 9-17).
After the core voltage being normal,ISL95831 again pulls ALERT# low,means that the
voltage has been normal.
When the chip again received the corresponding SVID signal of control second of power supply
output,the chip outputs a integrated graphics power supply.
Table 9-17 the standard table of serial VIN decoding of ISL95831(the original in English)
143
145
Analysis of commonly used chip ISL6265 by AMD platform

ISL6265 is commonly used in the motherboard of AMD CPU,as the output control of the
CPU core power supply and VDDNB power supply.The size of chip is 6mm*6mm,QFN48
packaged.
146
Figure 9-72 the pin name of ISL6265 (the top view)
1.the external connects the resistance to the ground programming DC current source.If this pin is
1.2V,VFIX mode is closed;if this pin is pulled up to be 3.3V,VFIX mode is opened,DAC decoder
analyzes the input information of SVC and SVD,OFS function is closed;if this pin is pulled up to
be 5V,OFS and VFIX are closed
2.the power good signal,open drain output,it needs to be pulled up by the external,then it will be
high level
3.the system power good signal input.When this pin is high,SVID interface is active,I²C protocol
is running.When this pin is low,the input state of SVC,SVD and VFIXEN decides PRE-PWROK
METAL VID or VFIX mode voltage.Before ISL6265 sent the high level of PGOOD,this pin must
be low
4.serial VID identification pin data signal,connects with AMD processor
5.serial VID identification pin clock pin,connects with AMD processor
147
6.the enable signal input,when its high level,ISL6265 is opened
7.connects the 117kΩ resistance to the ground,sets the internal reference current
8.the over-current of CORE_0 and CORE_1 setting signal input
9.CORE_0 differential amplification output
10.CORE_0 feedback input,to the input end of the internal CORE_0 error amplifier
11.CORE_0 controller error amplifier output
12.from this pin connecting the resistance to COMP0 to set the switch frequency,for
example,6.81kΩis 300kHz
13.the positive input of CORE_0 current detection
14.the negative input of CORE_0 current detection
15.CORE_0 voltage detection input
16.the input loop of CORE_0 voltage detection
17.the input loop of CORE_1 voltage detection
18.CIRE_1 voltage detection input
19.CORE_1 differential amplification output
20.CORE_1 feedback input,to the input end of the internal CORE_1 error amplifier
21.CORE_1 controller error amplifier output
22.from this pin connecting the resistance to COMP1 to set the switch frequency of the chip,for
example,6.81kΩ is 300kHz
23.the positive input of CORE_1 current detection
24.the negative input of CORE_1 current detection
148
25.CORE_1 boot-strap end
26.CORE_1 high-end MOSFET driver signal output
27.CORE_1 phase pin,connects the output inductance.This pin is the loop of the high-end tube
drive signal
28.the ground terminal
29.CORE_1 low-end MOSFET driver signal output
30.the internal MOSFET driver power supply,connects the external 5V power supply voltage input
31.CORE_0 low-end MOSFET driver signal output
33.CORE_0 phase pin,connects the output inductance.This pin is the loop of the high-end tube
drive signal
34.CORE_0 high-end MOSFET driver signal output
35.CORE_0 boot-strap end
36.the boot-strap end of NB power supply
37.the high-end MOSFET driver signal output of NB power supply
38.the phase pin of NB power supply,connects the output inductance.This pin is the loop of the
high-end tube drive signal
39.the low-end MOSFET driver signal output of NB power supply
41.the over-current protection setting of NB power supply
42.the voltage feedback of NB power supply
149
43.the voltage feedback input of NB power supply
44.the switch frequency setting end of NB power supply,for example,22.1kΩis set to be 260kHz
45.the error amplification input of NB power supply
46.the feedback input of NB power supply
47.5V power supply input,external connection of a decoupling capacitor with 0.1μF
48.the chip power supply input pin,is used to improve the transient performance
引
名称定义
脚
外部连接电阻到地编程 DC 电流源。如果此脚为
OFS/VFIXE 1.2V，VFIX 模式被关闭；如果此脚被上拉为 3.3V，VFIX 模
1
N 式开启，DAC 解码器解析 SVC、SVD 的输入信息，OFS 功
能关闭；如果此脚被上拉为 5V，OFS 和 VFIX 都被关闭
2 PGOOD 电源好信号，开漏输出，需要外部上拉才为高电平
系统电源好信号输入。当此引脚为高，SVID 界面是活动的，
I²C 协议运行。当这脚为低，SVC、SVD 和 VFIXEN 的输入
3 PWROK
状态决定 PRE-PWROK METAL VID 或 VFIX 模式电压。在
ISL6265 发出高电平的 PGOOD 之前，该引脚必须是低
4 SVD 串行 VID 识别引脚数据信号，与 AMD 处理器连接
5 SVC 串行 VID 识别引脚时钟引脚，与 AMD 处理器连接
6 ENABLE 使能信号输入，高电平时，ISL6265 开启
7 RBIAS 连接 117kΩ 电阻到地，设定内部基准电流
8 OCSET CORE_0 和 CORE_1 过流保护设置信号输入
9 VDIFF_0 CORE_0 差分放大输出
10 FB_0 CORE_0 反馈输入，到内部 CORE_0 误差放大器的输入端
11 COMP_0 CORE_0 控制器误差放大输出
从这个针脚连接电阻到 COMP0 用来设置开关频率，如
12 VW0
6.81kΩ为 300kHz
13 ISP0 CORE_0 电流检测正输入
14 ISN0 CORE_0 电流检测负输入
15 VSEN0 CORE_0 电压检测输入
16 RTN0 CORE_0 电压检测输入回路
17 RTN1 CORE_1 电压检测输入回路
续表
引
名称定义
脚
18 VSEN1 CORE_1 电压检测输入
150
19 VDIFF_1 CORE_1 差分放大输出

20 FB_1 CORE_1 反馈输入，到内部 CORE_1 误差放大器的输入端
21 COMP_1 CORE_1 控制器误差放大输出
从这个针脚连接电阻到 COMP1 用来设置芯片开关频率，
22 VW1
如 6.81kΩ为 300kHz
23 ISP_1 CORE_1 电流检测正输入
24 ISN_1 CORE_1 电流检测负输入
25 BOOT_1 CORE_1 自举升压端
26 UGATE_1 CORE_1 高端 MOSFET 驱动信号输出
CORE_1 相位脚，连接输出电感。此脚是高端管驱动信号
27 PHASE_1
的回路
28 PGND_1 接地端
29 LGATE_1 CORE_1 低端 MOSFET 驱动信号输出
30 PVCC 内部 MOSFET 驱动器供电，连接外部 5V 供电电压输入
31 LGATE_0 CORE_0 低端 MOSFET 驱动信号输出
32 PGND_0 接地端
CORE_0 相位脚，连接输出电感。此脚是高端管驱动信号
33 PHASE_0
的回路
34 UGATE_0 CORE_0 高端 MOSFET 驱动信号输出
35 BOOT_0 CORE_0 自举升压端
36 BOOT_NB NB 供电自举升压端
37 UGATE_NB NB 供电高端 MOSFET 驱动信号输出
NB 供电相位脚，连接输出电感。此脚是高端管驱动信号的
38 PHASE_NB
回路
39 LGATE_NB NB 供电低端 MOSFET 驱动信号输出
40 PGND_NB 接地端
41 OCSET_NB NB 供电过流保护设置
42 RTN_NB NB 供电电压反馈
43 VSEN_NB NB 供电电压反馈输入
44 FSET_NB NB 供电开关频率设置端，如 22.1kΩ设定为 260kHz
45 COMP_NB NB 供电误差放大输入
46 FB_NB NB 供电反馈输入
47 VCC 5V 供电输入，外接一个 0.1μF 的去耦电容
48 VIN 芯片供电输入脚，用于提升瞬态性能
The important pin threshold voltage of ISL6265:

When VCC input voltage is higher than 4.35V(the typical value),is shown in figure 9-73,the
chip implements POR(Power-On Reset).When VCC input voltage is less than 4.1V(typical
value),the chip stops working.
151
Figure 9-73 the screenshot of the description of the electrical features of VCC threshold value
in ISL6265 data manual
The typical value of the low level of threshold value of EN pin of ISL6265 is 1.35V,the high
level of threshold value is 2V(typical value),is shown in figure 9-74.
Figure 9-74 the screenshot of the description of the electrical features of EN threshold value in
ISL6265 data manual

The input low level of threshold value of PWROK pin of ISL6265 is usually 0.65V,the
high level of threshold value is usually 0.9V,is shown in figure 9-75.
Figure 9-75 the screenshot of the description of the electrical features of PWROK threshold
value in ISL6265 data manual

When PWROK is low level,ISL6265 chip does not implement SVID instruction,but
implement the corresponding voltage according to the state set by VFIXEN:when VFIXEN
connects to 1.2V below or about 5V,implements PRE-PWROK METAL VID mode,the voltage
configured by VID is shown in table 9-19,in this working mode,when SVC and SVD are low
level,the output voltage is 1.1V;when SVC and SVD are high level,the output is 0.8V.
METAL VID 模式解码表 9-20 VFIX 模式解码表

SVC SVD 输出电压 SVC SVD 输出电压
0 0 1.1 0 0 1.4
0 1 1.0 0 1 1.2
1 0 0.9 1 0 1.0
1 1 0.8 1 1 0.8
When VFIXEN of ISL6265 connects to 3.3V,implements VFIX mode,the voltage configured

by VID is shown in table 9-20,in this mode,when SVC and SVD are low level,the output voltage is
1.4V;when SVC and SVD are high level,the output voltage is 0.8V.
Table 9-19 PRE-PWROK METAL VID mode decoding of ISL6265
Table 9-20 VFIX mode decoding
152
Figure 9-76 is the typical application figure of ISL6265.

The working process of ISL6265 is shown in figure 9-77.
The transverse digital means the time,the vertical signal will change with time.As follows:
Time 1-2:VCC input,and crossed POR(4.3V),to complete the chip self reset.
Time 2-3:SVC and SVD are pulled up or pulled low by the external,sets pre_Metal VID code
Time 3-4:after EN changing to be the high level,VDD and VDDNB starts up,rises to the
value set by pre_Metal VID mode.
Time 4-5:VDDPWRGF changes to be the high level,indicates that CPU power supply has
been normal.
Time 5-6:PWROK inputs the high level,indicates that the chip ready to receive SVI code.
Time 6-7:CPU drives SVD and SVC to start to transmit SVI instructions.
Time 7-8:ISL6265 responds to SVI code instructions.
Time 8-9:if PWROK changes to be low,the chip stops SVI decoding immediately,and drives
CPU voltage to the value set by Pre_PWROK Metal VID.
153
Figure 9-76 the typical application figure of ISL6265
Figure 9-77 the working timing sequence figure of ISL6265
Time 9-10:PWROK changes to be high,indicates that the chip readies to receive SVI
instructions again.
Time 10-11:SVC and SVD transmits new VID code.
Time 11-12:ISL6265 drives CPU power supply voltage to the new value set by SVI.
133

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Chapter Three

The architecture of laptop

The architecture of Intel double bridge(GM/PM45 and

The architecture of Intel single bridge(above HM55)

The architecture of AMD double bridge(RS780)

The architecture of AMD single bridge(A70)

The architecture of nVIDIA double bridge(C51M)

The architecture of nVIDIA single bridge(MCP67)

4.1 Power supply and signal

voltage,we called signal,then what’s the difference between them?

The power supply is providing the power to the device,it’s name is

The circuit symbol of power supply is shown in figure 4-1.

Figure 4-2 The power supply symbol of Apple products

The circuit diagram of signal is shown in figure 4-4.

4.2 High level and low level

4.3 Jump and pulse

Figure 4-5 The falling edge waveform

Figure 4-6 The rising edge waveform

Figure 4-7 The high-low-high pulse waveform

4.4 The clock signal

oscilloscope or multimeter to measure the clock signal.

The clock signal of clock chip benchmark-14MHz is shown in figure 4-8.

4.5 Reset signal

signal is generally expressed as ***RST#,such as PCIRST#、CPURST#、IDERST# and so on.

Figure 4-9 the circuit of the CPU reset.

4.6 The power good signal

abbreviations of PG signal are PD、PWRGD、POK、PWRG、VTTPWRGD,CPUPWRGD,etc.

After RT8205 working normally,then send SPOK,is shown in figure 4-10.

Figure 4-10 PG signal diagram.

4.7 The open signal

4.8 Chip select signal

Figure 4-13 the chart of SPI BIOS pin

4.9 Explanation of common signal name about

AD+ the first voltage that the adapter converts

DCBATOUT common point

+3VL 3.3V linear power supply,to supply power to EC

DCIN power supply input for charging chip

ACIN adapter detection input for charging chip

ACAV-IN adapter detection output for charging chip

PWR-S5-EN a control signal used to open standby voltage of South Bridge

+5VALM、+3VALM the standby power supply of South Bridge

KBC-PWR-BTN# press the switch to produce the trigger signal to EC

LID-CLOSE# close cover switch

信 号 名 称 Signal Name 解 释 Explanation

Some of common signal names about Quanta shown in table 4-2

VIN the common point voltage

ACIN、ACOK adapter detection

3V-AL、5V-AL、VL 3V、5V linear power supply

+3VPCU、+5VPCU EC standby power supply

VR-ON the CPU core voltage opening signal sent by EC.

DELAY-VR-PWG CPU core voltage power-good signal

from an initial state.

BL/C# represents high level,low battery (only for battery model)

信 号 名 称 Signal Name 解 释 Explanation

Some of common signal names about ASUS shown in figure 4-3

AC-BAT-SYS the common point voltage

ACIN adapter detection

信号名称 Signal Name 解释 Explanation

信号名称 Signal Name 解释 Explanation

信号名称 Signal Name 解释 Explanation

信号名称 Signal Name 解释 Explanation

信号名称 Signal Name 解释 Explanation