Sequential Logic

References:
Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey © UCB
Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed.,
N. H. E. Weste and K. Eshraghian

Prof. Kaushik Roy

@ Purdue Univ.
 Clocked Systems: Finite State Machines

Inputs Outputs
Combinational Out = f(In, State)
Logic

Current state bits Next state bits

Q D

Clock or clocks
Registers

Registers serve as storage element to store past history

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 Clocked Systems: Pipelined Systems

Inputs Outputs
D Q D Q D Q
Logic Logic

Registers

Clock

Registers serve as storage element to capture the output

of each processing stage

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@ Purdue Univ.
 Storage Mechanisms

• Positive feedback
– Connect one or more output signals back to the input
– Regenerative, signal can be held indefinitely, static
• Charge-based
– Use charge storage to store signal value
– Need refreshing to overcome charge leakage, dynamic

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@ Purdue Univ.
 Positive Feedback: Two Cascaded Inverters

Vi1 Vo1= Vi2 Vo2

Vi2= Vo1

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 Bi-Stability and Meta-Stability

Vi2=Vo1

Vi2=Vo1
A A

C C

B B

d Vi1=Vo2 d Vi1=Vo2

Gain larger than 1 amplifies Gain less than 1 reduces

the deviation from C the deviation from A

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@ Purdue Univ.
 SR-Flip Flop
• NOR-based SR flip-flop, positive logic

Schematic Logic Symbol Characteristic table

• NAND-based SR flip-flop, negative logic Forbidden state

Schematic Logic Symbol Characteristic table

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@ Purdue Univ.
 JK- Flip Flop

Schematic Logic Symbol Characteristic table

• Clock input f to synchronize changes in the output

logic states of flip-flops
• Forbidden state is eliminated,
• But repeated toggling when J = K = 1, need to keep
clock pulse small < propagation delay of FF
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@ Purdue Univ.
 Other Flip-Flops

Toggle or T flip-flop Delay or D flip-flop

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 Race Problem

• A flip-flop is a latch if the gate is transparent while the

clock is high (low)

• Signal can raise around when f is high

• Solutions:
– Reduce the pulse width of f
– Master-slave and edge-triggered FFs

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@ Purdue Univ.
 Master-Slave Flip-Flop

• Either master or slave FF is in the hold mode

• Pulse lengths of clock must be longer than
propagation delay of latches
• Asynchronous or synchronous inputs to initialize the
flip-flop states

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One-Catching or Level-Sensitive

QM

QS

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 Propagation Delay Based Edge-Triggered

• Depend only on the value of

In just before the clock
transition

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Edge Triggered Flip-Flop

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Flip-Flop: Timing Definitions

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Maximum Clock Frequency

t pFF  t p ,comb  t setup  T

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 CMOS Clocked SR Flip-Flop

VDD

S M2 M4
Q
Q
Q

Q f M6 M8 f
M1 M3
R
S M5 M7 R
f

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@ Purdue Univ.
 Transistor Sizing of SR Flip-Flop

• Assume transistors of inverters are sized so that VM

is VDD/2, mobility ratio mn/mp = 3
– (W/L)M1 = (W/L)M3 = 1.8/1.2
– (W/L)M2 = (W/L)M4 = 5.4/1.2
• To bring Q from 1 to 0, need to properly ratio the
sizes of pseudo-NMOS inverter (M7-M8)-M4
– VOL must be lower than VDD/2

   
  k p ,M 4  VDD  | Vtp |
2 2
kn, M 78  VDD  Vtn 
VDD VDD VDD VDD
  
 2 8   2 8 
mp
(W / L) M 78  (W / L) M 4  (W / L) M 3
mn
(W / L) M 7  2(W / L) M 78  2(W / L) M 3  (3.6 / 1.2)
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Flip-Flop: Transistor Sizing

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 Propagation Delay

Pseudo-
NMOS Inverter
inverter M3-M4
(M5-M6)-M2
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@ Purdue Univ.
Complementary CMOS SR Flip-Flop
VDD

S f M10 M12 f R
M9 M11

M2 M4
Q
Q

f M6 M8 f
M1 M3

S M5 M7 R

Eliminates pseudo-NMOS inverters

 Faster switching and smaller transient current
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@ Purdue Univ.
 6-Transistor SR Flip-Flop
VDD

M2 M4 f
f
Q
Q S
R

M1 M3

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@ Purdue Univ.
 CMOS D Flip-Flop

VDD

D
Q
Q
Q

Q f
f

f D D

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 Master-Slave D Flip-Flop

VDD

Q
Q

D D

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 CVSL-Style Master-Slave D-FF

VDD VDD

Q Q
f

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 Charge-Based Storage

D
f f
In D

Pseudo-static Latch

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 Layout of a D Flip-Flop

In In Q
f Q
f

f
f f Q

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 Master-Slave Flip-Flop

D
f f
A
In
B

f f

f
• Overlapping clocks can cause
– race conditions
– undefined signals
f
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@ Purdue Univ.
 2 Phase Non-Overlapping Clocks

D
f1 f2
A
In

f2 f1

f1

t p12

f2
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 Asynchronous Setting

D
f1 f2
A
In

-Set
f2 f1

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 2-phase Dynamic Flip-Flop

f1 f2
A
In D

Input Output
sampled Enabled

f1

f2

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Flip-flop Insensitive to Clock Overlap

VDD VDD

M2 M6

f M4 f M8
X D
In
f M3 CL1 f M7 CL2

M1 M5

f-section f-section

C2MOS Latch or Clocked CMOS Latch

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 C2MOS Latch Avoids Race Conditions
VDD VDD

M2 M6

X D
In
1 M3 CL1 1 M7 CL2

M1 M5

• Cascaded inverters: needs one pull-up followed by one pull-

down, or vice versa to propagate signal
• (1-1) overlap: Only the pull-down networks are active, input
signal cannot propagate to the output
• (0-0) overlap: only the pull-up networks are active
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@ Purdue Univ.
 Clocked CMOS Logic
• Replace the inverter in a C2MOS latch with a
complementary CMOS logic
In1-3 VDD VDD

PUN PUN

f M4 f M8
X

f M3 CL1 f M7 CL2
In1-3

PDN PDN

• Divide the computation into stages: Pipelining

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 Pipelining

REG
a REG Non-pipelined a Pipelined

REG
REG

REG
REG
f  log f  log

REG
REG

b f b f f f

f f
Tmin  t p,reg  t p,logic  tsetup,reg Tmin, pipe  t p,reg  max( t p,adder, t p,abs, t p,log )  t setup,reg

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 Pipelined Logic using C2MOS

VDD VDD VDD

f f f out
In F G
f C1 f C2 f C3

NORA CMOS (NO-RAce logic)

Race free as long as all the logic functions F and G

between the latches are non-inverting

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@ Purdue Univ.
 Example

VDD VDD

VDD

f f
In
f f

Number of static inversion should be even

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NORA CMOS f-module

Logic Latch
f=0 Precharge Hold
f=1 Evaluate Evaluate

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NORA CMOS f-module

Logic Latch
f=0 Evaluate Evaluate
f=1 Precharge Hold

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@ Purdue Univ.
 NORA Logic

• NORA data path consists of a chain of alternating f

and f modules
• Dynamic-logic rule: single 0  1 (1  0) transition for
dynamic fn-block (fp-block)
• C2MOS rule:
– If dynamic blocks are present, even number of static
inversions between a latch and a dynamic block
– Otherwise, even number of static inversions between latches
• Static logic may glitch, best to keep all of them after
dynamic blocks

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@ Purdue Univ.
 Doubled C2MOS Latches

Doubled n-C2MOS latch Doubled p-C2MOS latch

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 TSPC - True Single Phase Clock Logic

Including logic into Inserting logic between

the latch the latches

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 Simplified TSPC Latches

A and A’ do not have full logic swing

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Master-Slave Simplified TSPC Flip-Flops

• Positive edge-triggered D flip-flops

• Reduces clock load

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Further Simplication

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 Schmitt Trigger

• VTC with hysteresis

• Restores signal slopes

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Noise Suppression using Schmitt Trigger

Sharp low-to-high transition

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CMOS Schmitt Trigger

Moves switching threshold

of first inverter

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@ Purdue Univ.
 Sizing of M3 and M4

• VM+ = 3.5V
– M1 and M2 are in saturation; M4 is in triode region
k1
VM   Vtn 2 
2
k2 2 
VDD  VM   | Vtp |  k4  VDD  | Vtp |VDD  VM   

VDD  VM 2



2  2 

• VM- = 1.5V
– M1 and M2 are in saturation; M3 is in triode region

Prof. Kaushik Roy

@ Purdue Univ.
Schmitt Trigger: Simulated VTC

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CMOS Schmitt Trigger

• In = 0, at steady state, VOut = VDD, VX =

VDD - Vtn
• In makes a 01 transition
– Saturated load inverter M1-M5 discharges
X
– M2 inactive until VX = Vin - Vtn
– Use Vin to approximate VM-
– M1-M5 in saturation
k1
VM   Vtn 2  k5 VDD  VM  2
2 2

Prof. Kaushik Roy

@ Purdue Univ.