COA PUE 2022-23 SOLUTION

Section A

Define the functions of different functional units of a computer system

Input unit
 Input units are used by the computer to read the data.
 The output unit is used to send the processed results to the user.
 Central processing unit carries out the instructions given by a computer program by performing the basic arithmetic, logical,
control and input/output (I/O) operations specified by the instructions.
 Arithmetic and Logical Unit performs arithmetic operations and the logical operations.
 The control unit is a component of a computer's central processing unit that coordinates the operation of the processor.
 The Memory unit can be referred to as the storage area in which programs are kept which are running, and that contains data
needed by the running programs.

Define computer organization and computer architecture.

Computer Architecture:

Computer architecture refers to those attributes of a system visible to a programmer or those

attributes that have a direct impact on the logical execution of a program. Examples of architectural attributes include the instruction
set, the number of bits used to represent various data types (e.g., numbers, characters), I/O mechanisms, and techniques for addressing
memory.

Computer Organization:

Computer organization refers to the operational units and their interconnections that realize the architectural specifications.
Organizational attributes include those hardware details transparent to the programmer, such as control signals; interfaces between the
computer and peripherals; and the memory technology used.

Calculate arithmetic right shift and arithmetic left shift of 10010100.

Ans:

ARS: 11001010

ALS: 10101000
Explain the need of biasing in IEEE representation of floating pint numbers.
 Biasing is done to make signed exponent unsigned.
 Biasing is done because exponents have to be signed values in order to be able to represent both tiny and huge values, but
two's complement, the usual representation for signed values, would make comparison harder. To solve this problem, the
exponent is biased before being stored.

Differentiate between RISC and CISC.

Explain microinstruction format for vertical microprogram control unit.

In a Vertical micro-programmed control unit, the control signals are represented in the encoded binary format.
Here ‘n’ control signals require (log n base 2) bit encoding. It contains next microinstruction address and bits for
different conditions. Format:

Define the term locality of reference.

Define the term Hit Ratio.
Hit ratio is fraction of cache memory accesses which are a hit. Hit ration is calculated as

Differentiate between maskable and non-maskable interrupts.

Differentiate between memory mapped I/O and isolated I/O.

 Section B
Compare different the bus arbitration techniques.
Types of Bus Arbitration:
There are two approaches to Bus Arbitration
A. Centralized Bus Arbitration: in centralized, a single hardware device, referred to as a
bus arbiter, is responsible for allocating the time on bus.
B. Distributed Bus Arbitration: Devices participate in the selection of the next master. In
distributed scheme, there is no central controller logic. Rather, each module contains the
access control logic and the modules act together to share the bus.
Centralized Bus Arbitration Techniques:
 Daisy Chaining Method
 Polling Method
 Independent Request Method
Daisy Chaining Method
 All bus masters use the same line for Bus Request.
 If the Bus Busy line is inactive, the Bus Controller gives the Bus Grant signal.
 Bus Grant signal is propagated serially through all masters starting from the nearest
 one.
 The bus master, which requires the system bus, stops this signal, activates the Bus
 Busy line, and takes control of the system bus.

B) Polling Method
 Here also all bus masters use the same line for Bus Requests.
  Here the controller generates a binary address for the master. E.g: To connect 8 bus masters we need 3
address lines (23 = 8).
 In response to a Bus Request, the controller "polls" the bus masters by sending a
 sequence of bus master addresses on the address lines. Eg: 000, 010, 100, 011 etc.
 The selected master activates the Bus Busy line and takes control of the bus.

C) Independent Request Method

 Here, all bus masters have their individual Bus Request and Bus Grant lines.
 The controller thus knows which master has requested, so the bus is granted to that
 master.
 Priorities of the masters are predefined so on simultaneous Bus Requests, the bus is granted based on the
priority, provided the Bus Busy line is not active.
 The Controller consists of encoder and decoder logic for the priorities.
OR
Calculate the effective address if the addressing mode is-
(i) Immediate
(ii) Direct
(iii) Register Indirect
(iv) Auto-decrement mode
(vi) Relative
(vii) Base register, consider R1 as base register
By Analyzing the given: An Instruction is stored at location 200
with its address field at 201. The address field has value 500. The
processor register R1 contains the number 200 and Register R2 contains
the number 100.
Draw and explain the 3-bit CLA.
Carry look-ahead adder utilizes the logic gates to look at the lower order bits of augmend and
addend to see if a higher order carry is to be generated or not.
Carry look-ahead uses the two concepts of carry propagate and carry generate functions.
This adder uses the following equations for ith stage:
The circuit diagram of 3-bit Carry Look-Ahead Adder is shown in the
following figure:

OR

Draw and explain the 2-bit ALU.

ALU (Arithmetic Logical Unit is digital circuit that performs arithmetic like addition, subtraction etc and
logical operations AND, OR, XOR etc..
Describe the working of Hardwired control unit with a suitable diagram.
 The Hardwired Control organization involves the control logic to be implemented with gates, flip-flops,
decoders, and other digital circuits. The following image shows the block diagram of a Hardwired
Control organization.
  A Hard-wired Control consists of two decoders, a sequence counter, and a number of
 logic gates.
 An instruction fetched from the memory unit is placed in the instruction register (IR).
 The component of an instruction register includes; I bit, the operation code, and address bits of operand
0 through 11.
 The operation code in bits 12 through 14. These bits are decoded with a 3 x 8 decoder.
 The outputs of the decoder are designated by the symbols D0 through D7.
 The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.
 The operation codes from Bits 0 through 11 are applied to the control logic gates.
 The Sequence counter (SC) can count in binary from 0 through 15.

OR

Describe the working of micro-programmed control unit with a suitable diagram.

A control unit whose binary control variables are stored in memory is known as a microprogrammed control
unit. In Microprogrammed Control, the control information is stored in the control memory and is programmed
to initiate the required sequence of micro-operations.
Each bit in the microinstruction is connected to a single control signal. The control signal is active when its bit
is set. The control signal becomes inactive when it is cleared. The internal control memory can store a sequence
of these microinstructions.

The block diagram of a Microprogrammed Control Organization is shown below.

Illustrate “how logical address is mapped to physical address”.

 A logical address or virtual address is generated by CPU while a program is running. Since a logical
address does not physically exist.
 This address is used as a reference by the CPU to access the actual physical memory location.
 There is a hardware device called Memory-Management Unit is used for mapping logical address to its
corresponding physical address.
 A physical address identifies the physical location of a specific data element in memory.
 The user never directly deals with the physical address but can determine the physical address by its
corresponding logical address.
Every logical address generated by the CPU is first checked against the value in limit register. If the logical
address is less than the value in limit register, the base address (value in Base Register is added to the logical
address to get the corresponding physical address of the memory location to be referenced. If the value is more,
it is an invalid memory access. In this case, CPU traps to the operating system, and the OS terminates the program
along with a process core dump indicating the fatal error.

OR
Calculate number of page fault using LRU Page Replacement Algorithm: 2,5,4,3,2,5,1,6,4,3,6,1,3 if the
number of frames in the memory is 3.
Draw and explain the flowchart for Programmed I/O data transfer technique.

 Processor executes an I/O instruction by issuing command to appropriate I/O module

 I/O module performs the requested action and then sets the appropriate bits in the I/O status register –
I/O module takes no further action to alert the processor – it does not interrupt the processor
 The processor periodically checks the status of the I/O module until it determines that the operation is
complete

OR
Draw the block diagram of DMA Controller and also compare the various DMA modes.
DMA Controller is a hardware device that allows I/O devices to directly access memory with less
participation of the processor. The DMA controller takes over the buses to manage the transfer directly
between the I/O devices and the memory unit.
Block diagram of DMA Controller:

The DMA controller includes several registers and control signals: -

Address Register: The DMA Address Register contains the memory address to be used in the data transfer.
Word Count Register: contains the no. of bytes of data to be transferred. L
Control Register: The DMA Control Register accepts commands from the CPU.
Bus request, register select, and DMA select: To select the device the DMA select control is used, the register
select control is used to select the registers. The DMA send bus request to the CPU using Bus request.
Bus Grant: The content in the bus grant is sent by the CPU, stating that permission is granted to access the bus.
So, after the permission is granted the control signal will send by the CPU to the direct memory access unit. If
the bus grant is high that means input/output device content can be transferred to the memory.
DMA Modes of transfer:
(a)Block Transfer Mode or Burst Mode:
 In this mode, a block of data of arbitrary length can be transferred in a single burst.
 DMA handover the buses to CPU only after completion of whole data transfer. Meanwhile, if the CPU
requires the bus it has to stay ideal and wait for data transfer.
 This DMA mode is needed for secondary memories where data transmission cannot be stopped or slowed
and transferred is done without loss of data.
b) Cycle Stealing Mode:
  In cycle stealing mode, the DMA controller is allowed to transfer one byte at a time, after which it must
return the control of the bus to the CPU.
 It continuously issues a request for bus control, makes the transfer of one byte and returns the bus.
 By this CPU doesn’t have to wait for a long time if it needs a bus for higher priority task.
c) Transparent Mode:
 In transparent, DMA is allowed to steal only those cycles when the CPU is not using the system bus.
 CPU does not require to have control of system bus during Decode instruction and execute instruction
phase
 DMA transferring data during transparent DMA does not have any adverse effect on CPU performance
 Section C
Illustrate the process of binary multiplication through booth’s algorithm and show the step by step
multiplication of (+15) and (-13) using booth’s multiplication algorithm.
OR
Illustrate the process of restoring method of division for dividing (15) by (5). Describe all steps of the
algorithm.
Diagram and explain the microprogram sequencer with suitable diagram and function tables.
Diagram and explain instruction pipelining and arithmetic with suitable examples.
 Arithmetic Pipeline is an implementation technique that allows the overlapping of arithmetic suboperations.
 used to implement floating-point operations, multiplication of fixed-point numbers
 used in high-speed computers

Example:
The inputs to the floating-point adder pipeline are two normalized floating-point binary numbers defined as:

Where
A, B  fractions or mantissa
a, b  exponents

The combined operation of floating-point addition and subtraction is divided into four segments. The sub-operations that
are shown in the four segments are:

1. Compare the exponents by subtraction.

 2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.

Compare exponents by subtraction:

The exponents are compared by subtracting them to determine their difference. The larger exponent is chosen as the
exponent of the result.
The difference of the exponents, i.e., 3 - 2 = 1 determines how many times the mantissa associated with the smaller
exponent must be shifted to the right.
Align the mantissa:
The mantissa associated with the smaller exponent is shifted according to the difference of exponents determined in
segment one.

Add mantissas:
The two mantissas are added in segment three.

Normalize the result:

After normalization, the result is written as:

Describe virtual memory technique using paging and segmentation with example of each.
Virtual Memory is a storage scheme that provides user an illusion of having a very big main memory. This is
done by treating a part of secondary memory as the main memory.
Virtual Memory can be implemented using two methods:
 Paging
 Segmentation
Paging is a memory-management scheme that permits the physical-address space of a process to be non-
contiguous. Physical memory is broken into fixed-sized blocks called frames. Logical memory is also broken
into blocks of the same size called pages.
When a process is to be executed, its pages are loaded into any available memory frames from the backing
store. The backing store is divided into fixed-sized blocks that are of the same size as the memory frames.
The hardware support for paging is given in the following image:

Every logical address generated by the CPU is divided into two parts: a page number (p) and a page offset (d).

Segmentation
Like Paging, Segmentation is another non-contiguous memory allocation technique.
Segmentation is a memory-management scheme that supports the user view of memory. A logical-address
space is a collection of segments. Each segment has a name and a length.
Segmentation is a variable size partitioning scheme.
In segmentation, secondary memory and main memory are divided into partitions of unequal size.
The size of partitions depends on the length of modules.
The partitions of secondary memory are called as segments.
Segment table is a table that stores the information (limit and the base address) about each segment of the
process.
Limit indicates the length or size of the segment.
Base indicates the base address or starting address of the segment in the main memory. The logical address
generated by the CPU is divided into two parts: Segment Number and Segment Offset.
The hardware support for segmentation is given in the following image:
OR
Describe Cache mapping techniques with suitable example of each.
Calculate the following:
 Calculate the number of pins in a RAM chip of 16KB capacity
 Calculate the number of chips are needed and how their address lines will be connected to provide
a memory capacity of 1024x4 using RAM chip of 1024x1 capacity.
OR

Calculate the following:

Number of address bits.
Number of Blocks in main memory.
Number of lines in the cache memory.
Number of sets in cache memory.
The size of cache memory.
Number of tag bits.
With a 4-way set associative cache memory that uses blocks of four words. The cache can accommodate a
total of 4096 words from the main memory. The main memory size is 256K x 16.
Describe the interrupt Processing with suitable diagram. Differentiate between
Software and hardware interrupts
Vectored and non-vectored interrupts

Hardware and Software Interrupts –

When microprocessors receive interrupt signals through pins (hardware) of microprocessor, they are known as Hardware
Interrupts. There are 5 Hardware Interrupts in 8085 microprocessor. They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
Software Interrupts are those which are inserted in between the program which means these are mnemonics of
microprocessor. There are 8 software interrupts in 8085 microprocessor. They are – RST 0, RST 1, RST 2, RST 3, RST 4,
RST 5, RST 6, RST 7.

Vectored and Non-Vectored Interrupts –

Vectored Interrupts are those which have fixed vector address (starting address of sub-routine) and after executing these,
program control is transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE

Non-Vectored Interrupts are those in which vector address is not predefined. The interrupting device gives the address of
sub-routine for these interrupts. INTR is the only non-vectored interrupt in 8085 microprocessor.

OR

Describe the types of asynchronous data transfer with suitable diagram of each.
Asynchronous data transfer
Asynchronous data transfer between two independent units requires that control signals be transmitted between
the communicating units to indicate the time at which data is being transmitted.
Two methods of asynchronous data transfer:
 Strobe control method
 Handshaking Method
Both the methods can be source initiated or destination initiated depending on which initiate the transfer.
1. Strobe Control Method

 The Strobe Control method of asynchronous data transfer employs a single control line to time each
transfer. This control line is also known as a strobe.
 The strobe method can be either by source or destination, depending on which initiate the transfer.

a. Source initiated Strobe Method: In this method, strobe is initiated by source,

 The source unit first places the data on the data bus.
 After a delay, the source activates a strobe pulse.
 The information on the data bus and strobe control signal remains in the active state for a sufficient time
to allow the destination unit to receive the data.
The destination unit uses a falling edge of strobe control to transfer the contents of a data bus to one of its
internal registers.
 The source removes the data from the data bus after it disables its strobe pulse.

b. Destination initiated strobe: In this method, the strobe initiated by destination.

 The destination unit first activates the strobe pulse, informing the source to provide the data.
 The source unit responds by placing the requested binary information on the data bus. The data must be
valid and remain on the bus long enough for the destination unit to accept it.
 The falling edge of the strobe pulse can use again to trigger a destination register. The destination unit
then disables the strobe. Finally, and source removes the data from the data bus after a determined time
interval.
2. Handshaking Method:
 This method is also known as two-wire control method
 can be either by source or destination, depending on which initiate the transfer.

Source initiated Handshaking Method

The two handshaking lines are data valid, which is generated by the source unit, and data accepted, generated
by the destination unit.

 The source unit initiates the transfer by placing the data on the bus and enabling its data valid signal.
 The data accepted signal is activated by the destination unit after it accepts the data from the bus.
 The source unit then disables its data valid signal, which invalidates the data on the bus.
 The destination unit then disables its data accepted signal and the system goes into its initial state.

Destination initiated Handshaking Method

The two handshaking lines are ready for data, generated by the destination unit and data valid, which is
generated by the source unit.
 The destination unit initiates the data transfer by enabling “ready for data”.
 The source unit places the data on the bus and enables its data valid signal.
 The data is accepted by the destination unit and disables “ready for data”.
 The source unit disables the data valid signal which invalidates the data on the bus. And the system goes
into its initial state.