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DIGITAL ELECTRONICS [17ECL38]

R.N.SHETTY INSTITUTE OF TECHNOLOGY

Channasandra, Bangalore-560098

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING

DIGITAL ELECTRONICS [17ECL38]

LABORATORY MANUAL
2018-2019
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DIGITAL ELECTRONICS [17ECL38]

RNS INSTITUTE OF TECHNOLOGY

Dr. VISHNUVARDHAN ROAD, CHANNASANDRA, BENGALURU -560 098

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

VISION of the College

Building RNSIT into a World - Class Institution

MISSION of the College

To impart high quality education in Engineering, Technology and Management with a difference,
enabling students to excel in their career by

1. Attracting quality Students and preparing them with a strong foundation in fundamentals so as to
achieve distinctions in various walks of life leading to outstanding contributions.
2. Imparting value based, need based, and choice based and skill based professional education to the
aspiring youth and carving them into disciplined, World class Professionals with social
responsibility.
3. Promoting excellence in Teaching, Research and Consultancy that galvanizes academic
consciousness among Faculty and Students.
4. Exposing Students to emerging frontiers of knowledge in various domains and make them
suitable for Industry, Entrepreneurship, Higher studies, and Research & Development.
5. Providing freedom of action and choice for all the Stake holders with better visibility.

VISION of the Department

Conquering technical frontiers in the field of Electronics and Communications

MISSION of the Department

1. To achieve and foster excellence in core Electronics and Communication engineering with focus
on the hardware, simulation and design.

2. To pursue Research, development and consultancy to achieve self sustenance.

3. To create benchmark standards in electronics and communication engineering by active

involvement of all stakeholders.
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DIGITAL ELECTRONICS [17ECL38]

B.E: Electronics & Communication Engineering

Program Outcomes (POs)

At the end of the B.E program, students are expected to have developed the following outcomes.

1. Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialisation to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, research literature, and analyse complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modelling to complex
engineering activities with an understanding of the limitations.
6. The Engineer and Society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal, and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
7. Environment and Sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of need for
sustainable development.
8. Ethics : Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
9. Individual and Team Work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project Management and Finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one‘s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognise the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change
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DIGITAL ELECTRONICS [17ECL38]

Program Specific Outcomes (PSOs)

At the end of the B.E Electronics & Communication Engineering program, students are expected to
have developed the following program specific outcomes.

PSO1: Apply fundamental knowledge of Electronics, Communications, Signal processing, VLSI,

Embedded and Control systems etc., in the analysis, design, and development of various types of
real-time integrated electronic systems and to synthesize and interpret the experimental data
leading to valid conclusions.
PSO2: Demonstrate competence in using Modern hardware languages and IT tools for the design and
analysis of complex electronic systems as per industry standards along with analytical and
managerial skills to arrive at appropriate solutions, either independently or in team.

Course objectives:

This laboratory course enables students to get practical

experience in design, realisation and verification of Demorgan‘s Theorem, SOP, POS forms
Full/Parallel Adders, Subtractors and Magnitude Comparator ,
Demultiplexers and Decoders applications Flip-Flops, Shift
registers and Counters

Course Outcomes
After studying this course, students will be able to:
Demonstrate the truth table of various expressions and combinational circuits using logic
CO1
gates.
Design and test various combinational circuit such as adders, subtractors, comparators,
CO2
multiplexers.
CO3 Realize Boolean expression using decoders.
CO4 Construct and test flips-flops, counters and shift registers.
CO5 Simulate full adder and up/down counters.

CO mapping to PO/PSOs

CO /
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
PO & PSO

CO1 3 2 2 3 2 3 3
CO2 3 2 3 3 2 3 3
CO3 3 2 3 3 2 3 3
CO4 3 2 3 3 2 3 3
CO5 3 2 3 3 2 3 3
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Note
1. The Course Outcomes and RBT levels indicated for each course in the syllabus are
indicative/suggestive. The faculty can set them appropriately according to their lesson plan.

2. The Question Paper format for the theory courses is as follows:

Question Paper Pattern for Theory Courses (2017 Scheme):

The question paper will have TEN questions.

Each full question carries 20 marks.

There will be two full questions (with a maximum of Four sub questions) from each module.

Each full question will have sub questions covering all the topics under a module.

Students will have to answer 5 full questions, selecting one full question from each module.
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DIGITAL ELECTRONICS LAB SEMESTER – III

(EC/TC)
[As per Choice Based Credit System (CBCS) Scheme]
Laboratory Code 17ECL38 CIE Marks 40

Number of Lecture 01Hr Tutorial (Instructions) SEE Marks 60

Hours/Week + 02 Hours Laboratory
RBT Level L1, L2, L3 Exam Hours 03

CREDITS – 02

NOTE:
1. Use discrete components to test and verify the logic gates. The IC umbers given are
suggestive. Any equivalent IC can be used.
2. For experiment No. 11 and 12 any open source or licensed simulation tool may be used.

Laboratory Experiments:
1. Verify
(a) Demorgan‘s Theorem for 2 variables.
(b) The sum-of product and product-of-sum expressions using universal gates.

2. Design and implement

(a) Full Adder using (i) basic logic gates and (ii) NAND gates.
(b) Full subtractor using (i) basic logic gates and (ii) NAND gates.
3. Design and implement 4-bit Parallel Adder/ Subtractor using IC 7483.

4. Design and Implementation of 5-bit Magnitude Comparator using IC 7485.

5. Realize
(a) Adder & Subtractor using IC 74153.
(b) 3-variable function using IC 74151(8:1MUX).
6. Realize a Boolean expression using decoder IC74139.
7. Realize Master-Slave JK, D & T Flip-Flops using NAND Gates.
8. Realize the following shift registers using IC7474/IC 7495
(a) SISO (b) SIPO (c) PISO (d) PIPO (e) Ring and (f) Johnson counter.
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9. Realize (i) Mod-N Asynchronous Counter using IC7490 and (

ii) Mod-N Synchronous counter using IC74192
10. Design Pseudo Random Sequence generator using 7495.
11. Simulate Full- Adder using simulation tool.
12. Simulate Mod-8 Synchronous UP/DOWN Counter using simulation tool.

Course Outcomes: On the completion of this laboratory course, the students will be able to:
Demonstrate the truth table of various expressions and combinational circuits
using logic gates.
Design and test various combinational circuit such as adders, subtractors,
comparators, multiplexers.
Realize Boolean expression using decoders.
Construct and test flips-flops, counters and shift registers.
Simulate full adder and up/down counters.

Conduct of Practical Examination:

● All laboratory experiments are to be included for practical
examination.
● Students are allowed to pick one experiment from the lot.
● Strictly follow the instructions as printed on the cover page of answer script
for breakup of marks.
● Change of experiment is allowed only once and Marks allotted to the
procedure part to be made zero.
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INDEX
Sl.no Laboratory Experiments Page no.
1 Verify
(a) Demorgan‘s Theorem for 2 variables.
20
(b)The sum-of product and product-of-sum expressions using
universal gates.
2 Design and implement
(a) Full Adder using (i) basic logic gates and (ii) NAND gates. 24
(b) Full subtractor using (i) basic logic gates and (ii) NAND
gates
3 Design and implement 4-bit Parallel Adder/ Subtractor using IC 27
7483
4 Design and Implementation of 5-bit Magnitude Comparator using 31
IC 7485.
5 Realize
(a) Adder & Subtractor using IC 74153. 34
(b) 3-variable function using IC 74151(8:1MUX).
6 Realize a Boolean expression using decoder IC74139. 39
7 Realize Master-Slave JK, D & T Flip-Flops using NAND Gates. 43
8 Realize the following shift registers using IC7474/IC 7495 50
(a)SISO (b) SIPO (c) PISO (d) PIPO (e) Ring and (f) Johnson
counter.
9 Realize 56
(i) Mod-N Asynchronous Counter using IC7490 and
(ii) Mod-N Synchronous counter using IC74192
10 Design Pseudo Random Sequence generator using 7495. 61
11 Simulate Full- Adder using simulation tool. 68
12 Simulate Mod-8 Synchronous UP/DOWN Counter using 70
simulation tool.

.
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INTRODUCTION TO IC’S
An Integrated Circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a
microchip) is a set of electronic circuits on one small plate ("chip") of semiconductor material
(normally silicon). This can be made much smaller than a discrete circuit made from independent
electronic components. ICs can be made very compact, having up to several billion transistors and
other electronic components in an area of the size of a human finger nail. The width of each
conducting line in a circuit can be made smaller, as the technology advances. According to the survey
the size was reduced to 100 nanometers in 2008 and 14 nanometers in 2014.

Integrated circuits (ICs) are key building blocks in modern electronics. They are the heart and brain
of most circuits. They are the ubiquitous little black “chips” that are found on almost every circuit
board. Figure 1 indicates inside view of digital IC.

Figure 1: Digital IC (Inside View)

An IC is a collection of electronic components – resistors, transistors, capacitors, etc. – all stuffed

into a tiny chip, and connected together to achieve a common goal. They come in all sorts of flavors:
single-circuit logic gates, op amps, 555 timers, voltage regulators, motor controllers,
microcontrollers, microprocessors, FPGAs.

Invention:

Early developments of the integrated circuit go back to 1949, when German engineer Werner Jacobi
(Siemens AG) filed a patent for an integrated-circuit-like semiconductor amplifying device showing
five transistors on a common substrate in a 3-stage amplifier arrangement. Jacobi disclosed small and
cheap hearing aids as typical industrial applications of his patent.

The idea of the integrated circuit was conceived by Geoffrey W.A. Dummer (1909–2002), a radar
scientist working for the Royal Radar Establishment of the British Ministry of Defence. A precursor
idea to the IC was to create small ceramic squares (wafers), each containing a single miniaturized
component. Components could then be integrated and wired into a bi-dimensional or tri-dimensional
compact grid. This idea, which seemed very promising in 1957, was proposed to the US Army by
Jack Kilby and led to the short-lived Micro module Program (similar to 1951's Project Tinkertoy).
However, as the project was gaining momentum, Kilby came up with a new, revolutionary design,
the IC that is as shown in Figure 2.
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Figure 2: Jack Kilby’s Original integrated circuit

Kilby recorded his initial ideas concerning the integrated circuit in July 1958, successfully
demonstrated the first working integrated example on 12 September 1958 and filed a patent in 1959.
He described his new device as "a body of semiconductor material, wherein all the components of the
electronic circuit are completely integrated." Kilby won the Nobel Prize in Physics in 2000. His work
was named as an IEEE Milestone in 2009.

Later, Robert Noyce at Fairchild Semiconductor developed his own idea of an integrated circuit that
solved many practical problems. Noyce's design was made of silicon, whereas Kilby's chip was made
of germanium. Noyce credited Kurt Lehovec of Sprague Electric for the principle of p–n junction
isolation caused by the action of a biased p–n junction (the diode) as a key concept behind the IC.

Generations:In the early days of simple integrated circuits, the technology's large scale limited each
chip to only a few transistors, and the low degree of integration meant the design process relatively
simple. As the technology progressed, millions, then billions of transistors could be placed on one
chip, and good designs required thorough planning, giving rise to new design methods. They are
listed in the table below.

IC Packages

The package encapsulates the integrated circuit die and plays it into a device which can be easily
connected. Each outer connection on the die is connected via a tiny piece of gold wire to a pad or pin
on the package. Pins are the silver extruding terminals on an IC, which can be connected to other
parts of a circuit.

There are many different types of packages, each of which has unique dimensions, mounting-types,
and/or pin-counts as shown in Figure 3.
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Figure 3: Different IC packages

Polarity Marking and Pin Numbering

All ICs are polarized and every pin is unique in terms of both location and function. Most ICs will
use either a notch or a dot to indicate which pin is the first pin as shown in the figure 4. (Sometimes
both, sometimes one or the other) .

Figure 4: Notation of a DIP IC

The pin number increases sequential staring from the notch counter-clockwise around the chip.

DIP (Dual in-line packages)

DIP, short for dual in-line package, is the most common through-hole IC package that is encountered.
These little chips have two parallel rows of pins extending perpendicularly out of a rectangular,
black, plastic housing. The typical representation of DIP IC is as shown in Figure 4.

Logic families
A logic family of monolithic digital integrated circuit devices is a group of electronic logic
gates, constructed using one of several different designs, usually with compatible logic levels and
power supply characteristics within a family. A "logic family" may also refer to a set of techniques
used to implement logic within VLSI integrated circuits such as central processors, memories, or
other complex functions.
Some of the popularly used logic families are:
● TTL (Transistor-Transistor Logic): Made of bipolar transistors mainly used for logical
operations.
● CMOS (Complementary Metal Oxide Semiconductor): Made from MOSFETs and
requires less power to operate and wide range of supply voltages.
● ECL (Emitter Coupled Logic): Used for extremely high speed operation.
● NMOS,PMOS: Used for Very Large Scale Integrated Circuits (VLSI)
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Some of the IC’s used in this laboratory are IC 74XX series, IC 74151, IC7474, and IC7476 to name
a few.

IC 74XX series:
The 74XX series contains hundreds of devices that provide everything from basic logic gates to flip-
flops, counters, special purpose bus transceivers and arithmetic logic units (ALU). These series can
either be designed using TTL logic or CMOS technology.
The part numbers for 74XX series logic devices use the following naming convention:

Figure 5: Part numbers for a typical 74XX series IC

● Two or three letter prefix indicates the manufacturer of the device for Ex: SN7400 where SN
for Texas Instruments.
● Two digits, where "74" indicates a commercial temperature range device and "54" indicates
military temperature range and "64" indicates a short-lived series with an intermediate
"industrial" temperature range.

● The next alphabet/s represents its electrical characteristics. Some of them are:
L: Low power. Larger resistors allowed 1 mW dissipation at the cost of a very slow 33 ns
gate delay.
H: High -speed. 6 ns gate delay but 22 mW power dissipation.

S: High -speed Schottky. It performs faster operation than 74H at the cost of increased power
consumption.
LS: Low power Schottky. It is same as ‘S’ but with reduced power consumption and
switching speed.
AS: Advanced Schottky with greater speed, lower power consumption.
F: Fast. It is the Fairchild's version of TI's 74AS.

All the above ICs use bipolar transistors. However, ICs with CMOS technology is also the most
widely used. Some of them are:
HC: High-speed CMOS, similar performance to LS,
HCT: High speed, compatible logic levels to bipolar parts.

● The last alphabet/s represents the manufacturer’s suffix. For example SN74LS08N means this
is a device made by Texas Instruments (SN). It is a commercial temperature range TTL device
(74). It is a member of the "Low power Schottky" family (LS), and it is housed in a plastic
through-hole DIP (N).
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INTRODUCTION TO DIGITAL IC TRAINER

Figure 3: Digital IC Trainer

Digital IC Trainer is a self contained Equipment with the following facilities for TTL/CMOS IC
Experiments.
♦ Input Switch: Provides switch for Input AC Power.
♦ Power Indicator: Illuminates to indicate the presence of AC power.
♦ Logic Output status Indicator: Individual LED Display Logic Output status (High or Low).
♦ Input Logic Switches: Logic Input status Level (High or Low) with LED Indicators.
♦ TTL Clocks: Frequency of 1Hz, 10Hz, 100Hz, 1 KHz and Monopulse.
♦ Connecting Sockets: 2mm/4mm Socket or terminals to connect patch cards.
♦ +5Volts Output: This delivers necessary VCC to all digital circuits.
♦ 0 Volts Output: Common Ground.
♦16 pin Zero Insertion Force (ZIF) sockets and 40pin ZIF socket/ bread board

Operating Instruction:
Connect the 230 volts AC power supply and switch ‘ON’ the Toggle switch on the left side of the
Top Panel and we can see LED will glow. Digital IC Trainer is ready for use.
Select the TTL/CMOS IC to be used for the experiment insert the IC in ZIF socket and lock the ZIF
by moving lever up wards. Now all the pins of the IC are available outside at 2mm sockets for
connecting inputs and outputs using patch cards.
Inputs such as logic clocks, of different frequency, monopulse, logic levels, BCD inputs, can be
selected from the patch panel. Outputs are observed through LED indicators.
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VERIFICATION OF LOGIC GATES

Aim: To study about logic gates and verify their truth tables.
Learning Objective: Identify various ICs and their Logical Operation.
Components required:
SL No. COMPONENT SPECIFICATION QTY
1. 2 Input Quadruple AND Gate IC 7408 1
2. 3 Input Triple AND Gate IC 7411 1
3. 2 Input Quadruple OR Gate IC 7432 1
4. 1 Input Hex Inverter or NOT Gate IC 7404 1
5. 2 Input Quadruple EX-OR Gate IC 7486 1
6. 2 Input Quadruple NAND Gate IC 7400 1
7. 3 Input Triple NAND Gate IC 7410 1
8. 4 Input Dual NAND Gate IC 7420 1
9. 2 Input Quadruple NOR Gate IC 7402 1
10. IC TRAINER KIT - 1

11. PATCH CHORDS - -

Theory: Logic gates are the basic components in digital electronics. A logic gate is a general purpose
electronic device used to construct logic circuits. These logic gates perform the basic Boolean
functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR. Table 1.
below shows the circuit symbol, Boolean function, and truth table. The gate has one or more inputs
and one output. The small circle on the output of the circuit symbols designates the logic
complement. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs.
A gate can be extended to have multiple inputs if the binary operation it represents is commutative
and associative.

These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of more
complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC gates are
classified not only by their logic operation, but also the specific logic-circuit family to which they
belong. Each logic family has its own basic electronic circuit upon which more complex digital
circuits and functions are developed.
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AND, OR and NOT are called as basic gates. AND, OR logic gates can have ‘n’ inputs
(n≥ 2) and gives single output. NOT gate also called as “inverter”, has
single input and produces single output.

AND gate: It is a basic logic gate that produces high state output only when all the inputs are logic
high or at logic ‘1’ state. It performs logical multiplication.

OR gate: It is a basic logic gate that produces high state output if any one of the inputs is logic high.
It performs logical addition.

NOT gate: It is a basic logic gate that produces an inverted output for a given input.

There are two universal gates:

NAND and NOR gates.
NAND gate: It is an universal logic gate that produces high state output if any one of the inputs is at
logic ‘1’ state. It is the complement of AND gate.

NOR gate: It is a universal logic gate that produces high output only when all the inputs are logic
high. It is the complement of OR gate.

There are two other types of digital logic gates which although are not the basic gates in their own ,
however, as they are constructed by combining together with other logic gates, their output Boolean
function is important enough to be considered as complete logic gates. These two “hybrid” logic
gates are called the Exclusive-OR (Ex-OR) Gate and its complement the Exclusive-NOR (Ex-NOR)
Gate.

Ex-OR gate: It is a logic gate that that produces high state output if it has odd number of ones.

Ex-NOR gate: It is a logic gate that that produces high state output if it has even number of ones. It
is the complement of Ex-OR gate.

Procedure:
1. Identify the IC required.
2. Check the components for their working.
3. Insert the appropriate IC into the IC base of the trainer kit such that the notch of the IC is
facing towards the Vcc, where the IC pin no. 7 and 14 are connected to ground and VCC
respectively.
4. Make connections as shown in the circuit diagram. Switch on the power supply.
5. Provide the input data via the input switches as per the truth table and observe the output on
output LEDs.
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Table 1.
2 INPUT QUADRUPLE AND GATE : PIN DIAGRAM:
SYMBOL:

3 INPUT TRIPLE AND GATE:

2 INPUT QUADRUPLE OR GATE:

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1 Input Hex Inverter or NOT Gate:

SYMBOL: PIN DIAGRAM:

2 INPUT QUADRUPLE EX-OR GATE:

SYMBOL: PIN DIAGRAM:

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2 INPUT QUADRUPLE NAND GATE:

SYMBOL: PIN DIAGRAM:

3 INPUT TRIPLE NAND GATE:

4 INPUT DUAL NAND GATE:

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2 INPUT QUADRUPLE NOR GATE:

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II Realization of basic gates using NOR and NAND gates:

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PROCEDURE:
· Check the components for their working.
· Insert the appropriate IC into the IC base.
· Make connections as shown in the circuit diagram.
· Provide the input data via the input switches and observe the output on output LEDs

Viva Questions:
1. Which of the following is the fastest logic?
A. ECL B. TTL C. CMOS D. LSI
2. Output will be a LOW for any case when one or more inputs are zero for a(n):
A. OR gate B. NOT gate C. AND gate D. NOR gate
1. TTL operates from a -------------- supply
A. 5V B. 9V c. 12V D. 15V
1. Logically, the output of a NOR gate would have the same Boolean expression as a(n):
A. NAND gate immediately followed by an inverter
B. OR gate immediately followed by an inverter
C. AND gate immediately followed by an inverter
D. NOR gate immediately followed by an inverter
1. What is the difference between 7400 IC and 7411 IC?
2. Why NAND & NOR gates are called universal gates?
3. Realize the EX – OR gate using minimum number of NAND gates.
4. Give the truth table for EX-NOR and realize using NAND gates.
5. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
6. Compare TTL logic family with CMOS family.
1.
2. Give the truth table for EX-NOR and realize using NAND gates.
3. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
4. Compare TTL logic family with CMOS family.
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EXPERIMENT NO. 1
IMPLEMENTATION OF DEMORGAN’S THEOREM AND SOP/POS
EXPRESSIONS
Aim: 1. To verify
(a) Demorgan’s Theorem for 2 variables
(b) The sum-of product and product-of-sum expressions using universal gates.

Components required: IC 7400, IC 7402, IC 7404, IC 7408, IC 7432, Patch Cords and Trainer Kit.

Theory: Augustus De Morgan, a 19th-century British mathematician developed a pair of important

rules regarding group complementation in Boolean algebra referred to as Demorgan’s theorems.
Applications of these rules include simplification of logical expressions in computer programs and
digital circuit designs. They are as follows.

(i)
Statement: The complement of a product is equal to the sum of complements.

(ii)
Statement: The complement of a sum term is equal to the product of complements.

In a Boolean function, the variables appear either in complemented or an uncomplemented form.

Each occurrence of a variable in either form is called a “literal”. These literals can be grouped either
as a product term or sum term. A product term is defined as either a literal or product of literals (also
called conjunction). A sum term is defined as either a literal or sum of literals (also called
disjunction). These literals and terms are arranged in two forms.
(i) Sum of Products (SoP): It is the group of product terms ORed together. If each product term
(also called minterm) in SoP contains all literals, then it is called canonical SoP.
(ii) Product of Sum (PoS): It is the group of sum terms ANDed together. If each sum term (also
called maxterm) in PoS contains all literals, then it is called canonical PoS.

Procedure:
1. Identify the IC required and place on the trainer kit such that the notch of the IC is facing
towards the Vcc, where the IC pin no. 7 and 14 are connected to ground and VCC respectively.
2. Connections are made as per the logic diagram.
3. Switch on the power supply.
4. Apply suitable logical inputs as per the truth table and verify the output.

NOTE: If correct output is not obtained, each and every gate is to be checked separately and even
then if the output is not obtained, then IC has to be replaced.
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(a) Verification of Demorgan’s theorem for two variables

Logic diagram:

Truth table:

(B) The sum-of product and product-of-sum expressions using universal gates.
1) Sum of product (SOP): Y=BD+AD
Y=F(A,B,C,D) = ∑(5,7,9,11,13,15)
Simplification using K-map:
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ii)Implementation Using NAND gates iii) Implementation Using NOR Gates

2) Product of Sum (POS): Y=(A+B)D

Y=F(A,B,C,D) = П(0,1,2,3,4,6,8,10,12,14)

Simplification using K-map:

ii) Implementation Using NAND gates iii) Implementation Using NOR

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Truth table:

Viva Questions:
1. State Demorgan’s theorem for three variables.

2. What is sum of product and product of sum?

3. Anything ORed with its own complement is equal to
A) 0 B) 1 C) Itself D) Its complement.

4. By using DeMorgan's theorem, X = A(B + C) is simplified to ________.

A) X = A(B + C) B) X = ABC C) X = A + B + C D) X = A + BC
5. A NOR gate with a bubble on one of its inputs is equivalent to
A) a NOR with bubbles in its inputs.
B) a NAND with bubbles on its inputs.
C) a NAND with a bubble on one input.
D) a NOR.

6. Anything that is complemented twice is equal to

A) 0. B) 1. C) Itself. D) Its complement.

7. An AND gate with inverted inputs functions as

A) OR gate. B) NAND gate. C) Inverter. D) NOR gate.

8. For a simplified Boolean expression f = AD' + AC + B'C, minimum no. of NAND gates required is
A) 5 B) 6 C) 4 D) 8
9. The Boolean function A + BC is a reduced form of
A) AB + BC B) (A + B)(A + C) C) A’B + AB’C D) (A + C)B

10. What is Gray code? Why this code is used in K-map?

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DIGITAL ELECTRONICS [17ECL38]

EXPERIMENT NO. 2
ADDERS AND SUBTRACTORS
Aim: To design and implement the following Adder and subtractor using logic gates.
(a) Full Adder using (i) Basic logic gates and (ii) NAND gates.
(b) Full subtractor using (i) Basic logic gates and (ii) NAND gates.

Components Required: IC 7486, IC 7432, IC 7408, IC 7400, Patch Cords and Trainer Kit.

Theory: A combinational circuit that performs the addition of two bits is called a half adder. A half
adder needs two binary inputs and two binary outputs. A half adder has no provision to add a carry
from the lower order bits when binary numbers are added. When two input bits and a carry are to be
added the number of input bits becomes three and the input combination increases to eight. For this
full adder is used.
A combinational circuit that performs the addition of three bits is a full adder. It consists of three
inputs and two outputs. Like half adder it also has a sum bit and a carry bit. The new carry generated
is represented by ‘Cout’ and the carry generated from the previous addition is represented by ‘Cin’.
When two input bits and a borrow have to be subtracted the number of input bits equal to three and
the input combinations increases to eight, for this a full subtractor is used.

Procedure:
1. Identify the IC required and place on the trainer kit such that the notch of the IC is facing
towards the Vcc, where the IC pin no. 7 and 14 are connected to ground and VCC respectively.
2. Connections are made as per the logic diagram
3. Switch on the power supply.
4. Apply suitable logical inputs as per the truth table and verify the output.
a). FULL ADDER
i) Full adder using Basic Gates
TRUTH TABLE
INPUTS OUTPUTS
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

BOOLEAN EXPRESSIONS:
Sum= A B C
Carry=A B + B C+ A C
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DIGITAL ELECTRONICS [17ECL38]

Logic Circuit

ii) Full Adder using NAND gates only

b)FULL SUBTRACTOR
i) Full Subtractor using BASIC gates
TRUTH TABLE
INPUTS OUTPUTS
A B Bin D Bo
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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DIGITAL ELECTRONICS [17ECL38]

BOOLEAN EXPRESSIONS:
D= A Bin C
Bo= B + B Bin + Bin

Logic Circuit

ii)Full Subtractor using NAND gates only

VIVA QUESTIONS:

1)What is a half adder?

2)What is a full adder?
3)What are the applications of adders?
4) What is a half subtractor?
5)What is a full subtractor?
6)What are the applications of subtractors?
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DIGITAL ELECTRONICS [17ECL38]

7)Realize a full adder using two half adders

EXPERIMENT NO.3
PARALLEL ADDER AND SUBTRACTOR

AIM: To design and set up the following circuit using IC 7483.

i) A 4-bit binary parallel adder.
ii) A 4-bit binary parallel subtractor.

LEARNING OBJECTIVE:
▪ To learn about IC 7483 and its internal structure.
▪ To realize a adder & subtractor using adder IC 7483

COMPONENTS REQUIRED:
IC 7483, IC 7486, Patch Cords & IC Trainer Kit.

THEORY
The Full adder can add single-digit binary numbers and carries. The largest sum that can be obtained
using a full adder is 112.Parallel adders can add multiple-digit numbers. If full adders are placed in
parallel, we can add two-or four-digit numbers or any other size desired. Figure below uses
STANDARD SYMBOLS to show a parallel adder capable of adding two; two-digit binary numbers.
The addend would be on A inputs, and the augend on the B inputs. For this explanation we will
assume there is no input to C0 (carry from a previous circuit)

To add 102 (addend) and 012 (augend), the addend inputs will be 1 on A2 and 0 on A1. The augend
inputs will be 0 on B2 and 1 on B1. Working from right to left, as we do in normal addition, let’s
calculate the outputs of each full adder. With A1 at 0 and B1 at 1, the output of adder1 will be a sum
(S1) of 1 with no carry (C1). Since A2 is1 and B2 is 0, we have a sum (S2) of 1 with no carry (C2)
from adder1. To determine the sum, read the outputs (C2, S22, and S1) from left to right. In this case,
C2 = 0, S2 = 1, and S1 = 1. The sum, then, of 102and 012 is 0112.To add four bits we require four full
adders arranged in parallel. IC 7483 is a 4- bit parallel adder whose pin diagram is shown.

(NOTE: 7483 IS A CARRY LOOK AHEAD ADDER)

MSB LSB
Cin
INPUTS A3 A2 A1 A0
B3 B2 B1 B0
OUTPUT Cout S3 S2 S1 S0
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IC 7483 PIN-OUT:

i) A 4-bit binary parallel adder.

An Example: 7+2=11 (1001)
● 7 is realized at A3 A2 A1 A0 = 0111
● 2 is realized at B3 B2 B1 B0 = 0010
Sum = 1001
ADDER CIRCUIT:

PROCEDURE:
● Check all the components for their working.
● Insert the appropriate IC into the IC base.
● Make connections as shown in the circuit diagram.
● Apply augend and addend bits on A and B and cin=0.
● Verify the results and observe the outputs.

ii) A 4-bit binary parallel subtractor.

ii)a. 4-BIT BINARY SUBTRACTOR (A>B).

Subtraction is carried out by adding 2’s complement of the subtrahend.

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Example: 8 – 3 = 5 (0101)

● 8 is realized at A3 A2 A1 A0 = 1000
● 3 is realized at B3 B2 B1 B0 through X-OR gates = 0011
● Output of X-OR gate is 1’s complement of 3 = 1100
● 2’s Complement can be obtained by adding Cin =1

Therefore
Cin = 1
A3 A2 A1 A0 = 1 0 0 0
B3 B2 B1 B0 = 1 1 0 0
S3 S2 S1 S0 = 0 1 0 1
Cout = 1 (Ignored) (Result is positive)

ii)b 4-BIT BINARY SUBTRACTOR (A<B).

Subtraction is carried out by adding 2’s complement of the subtrahend.
Example : 3 - 8 = -5 (1011)

● 3 is realized at A3 A2 A1 A0 = 0011
● 8 is realized at B3 B2 B1 B0 = 1000
● Output of X-OR gate is 1’s complement of 8 = 0111
● 2’s Complement can be obtained by adding Cin =1

Therefore
Cin = 1
A3 A2 A1 A0 = 0 0 1 1
B3 B2 B1 B0 = 0 1 1 1
S3 S2 S1 S0 = 1 0 1 1
Cout = 0 (Result is negative)

● Take 2’s complement of S3 S2 S1 S0 and the result will be -5.

PROCEDURE:
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DIGITAL ELECTRONICS [17ECL38]

● Check all the components for their working.

● Insert the appropriate IC into the IC base.
● Make connections as shown in the circuit diagram.
● Apply Minuend and subtrahend bits on A and B and cin=1.
● Verify the results and observe the outputs

Cin A B Cout S3 S2 S1 S0 Remarks

0 7 2 0 1 0 0 1
0 15 15 0
1 8 3 1 0 1 0 1 A>B, result is positive, Cout is
ignored.
1 3 8 0 1 0 1 1 A<B, result is negative (2’s
complement form), Cout=0
indicates negative result.

(NOTE: Draw the internal gate level diagram of IC 7483 in record.)

VIVA QUESTIONS:

1)What is parallel adder?

2)What are the applications of parallel adders?
3) Define 1s compliment & 2s compliment.
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EXPERIMENT NO. 4
STUDY OF IC 7485 5- BIT MAGNITUDE COMPARATOR
Aim: To design and implement 5-bit magnitude comparator using IC 7485.

Learning Objective:
1. To learn about various applications of comparator
2. To learn and understand the working of IC 7485 magnitude comparator
3. To learn to realize 5-bit comparator using 4-bit comparator
Components Required: IC 7485, Patch cords and Trainer kit.

Theory: A digital comparator or magnitude comparator is a hardware electronic device that takes
two numbers as input in binary form and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in central processing unit s (CPUs) and
microcontrollers (MCUs).

IC 7485: The IC 7485 is a 4-bit magnitude comparator that can be expanded to almost any length. It
compares two 4 bit binary and produces three magnitude results.

Procedure:
1. Make the connections as per the Pin diagram.
2. Verify the output with the truth table.

Examples:
EX. A3 A2 A1 A0 B3 B2 B1 B0 A>B A=B A<B
1 0 0 1 0 1 1 0 1
2 1 1 1 1 1 1 1 0
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3 1 0 0 1 1 0 0 1
4 0 1 0 1 0 0 0 0

Diagram for 4-bit Comparator:

Logic Diagram of 5-bit Comparator:

Input Output

EX. A4 A3 A2 A1 A0 B4 B3 B2 B1 B0 A>B A=B A<B

1 1 0 0 1 0 0 1 1 0 1
2 1 1 1 1 1 1 1 1 1 0
3 0 1 0 0 1 0 1 0 0 1
4 0 0 1 0 1 1 0 0 0 0
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Note: Using two 7485 ICs we can realize 8-bit comparator.

Functional Table for IC 7485:

Viva Questions

1) What is a comparator?
2) What are the applications of comparator?
3) Derive the Boolean expressions of one bit comparator and two bit comparators.
4) How do you realize a higher magnitude comparator using lower bit comparator?
5) Design a 2 bit comparator using a single Logic gates?
6) Design an 8 bit comparator using a two numbers of IC 7485?

NOTE:
Write the following in Record-
i) Internal gate level diagram of IC 7485

Experiment No. 5
STUDY OF ICs 74151 and 74153
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DIGITAL ELECTRONICS [17ECL38]

Aim: To realize
(a) Adder and Subtractor using IC 74153.
(b) 3-variable function using IC 74151(8:1 MUX).

Learning Objective:
1.To learn about various applications of Multiplexer
2.To learn and understand the working of IC 74151 and IC 74153
3. To learn to realize any function using Multiplexer .
Components required: IC 74151, IC 74153, Patch cords and Trainer kit.

Theory: A multiplexer is combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is controlled by
a set of selection lines. Normally there are 2n input lines and n selection lines whose bit combinations
determine which input is selected. An electronic multiplexer can be considered as a multiple-input,
single-output switch. A multiplexer is also called a data selector.
Conversely, a demultiplexer (or demux) is a device taking a single input signal and selecting one of
many data-output-lines, which is connected to the single input. A demultiplexer has one data input, 2n
select lines, and n output lines. A demultiplexer is also called a data distributor.
Procedure:
1. Make the connections as per the logic diagram.
2. Verify the output with the truth table.

Pin Details of IC74153:

Note: 1. when EA and EB equal to ‘1’, device is not enabled and outputs are ‘0’.
2. The Pin [16] is connected to + Vcc. Pin [8] is connected to ground.
3. If MUX ‘A’ has to be initialized, EA is made low and if MUX ‘B’ has to be Initialized,
EB is made low.

(i) Adder & Subtractor using IC 74153

a) Half Adder & Half Subtractor:
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DIGITAL ELECTRONICS [17ECL38]

Truth Table:
Half Adder Half Subtractor:

b) Full Adder & Full Subtractor:

Truth Table: Full Adder
Input Output

A B Cin SUM Cout

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0
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1 1 1

Implementation Table:

Full Subtractor:
A B Bin Diff Bout

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Implementation Table:

Pin Details of IC74151:

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DIGITAL ELECTRONICS [17ECL38]

In this experiment, 8:1 MUX is implemented using IC 74151. It is a popular 16-pin DIP IC which provides
eight inputs, three select lines and two complementary outputs y & . The o/p Y selects one of the
eight inputs based on the select lines (S0,S1,S2). Vcc is on pin 16 and GND is on pin 8. Pins 5 and 6
are the outputs, the output on pin 6 is the inverted version of the output on pin 5. The enable is on pin
7. It is the most widely used IC as it is a commercial temperature range device with low power
dissipation (135 mW) and low propagation delay time (9 ns).

Logic Symbol of 8:1 MUX

b) 3-variable function using IC 74151(8:1 MUX).

Realize the following expression using IC 74151
F (A,B,C) = ∑m (1,3,5,6)
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DIGITAL ELECTRONICS [17ECL38]

Truth table
INPUT OUTPUT
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Viva Questions:
1) What is a multiplexer?
2) What is a de-multiplexer?
3) What are the applications of multiplexer and de-multiplexer?
4) Derive the Boolean expression for multiplexer and de-multiplexer.
5) How do you realize a given function using multiplexer
6) What is the difference between multiplexer & demultiplexer?
7) In 2n to 1 multiplexer how many selection lines are there?
8) How to get higher order multiplexers?
9) Implement an 8:1 mux using 4:1 muxes?
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Experiment 6
Realize a Boolean Expression using Decoder IC 74139

Aim: To study Decoder and Demultiplexer

Components required: IC 74139 and digital IC trainer kit.
Theory:
Decoders are similar to demultiplexers but without any data input. A decoder is a
circuit that changes a code into a set of signals. In other words, decoder is a
combinational circuit that converts the input of one code format into another coded
format at the output side. It can process n inputs and generate 2n outputs.

The term is often used in reference to MPEG-2 video and sound data, which must be
decoded before it is output. Most DVD players, for example, include a decoder card
whose sole function is to decode MPEG data. It is also possible to decode MPEG data
in software, but this requires a powerful microprocessor.

1) 2 to 4 Line decoder (active low):

The pin configuration, logic circuit and truth table of IC 74139 (active low outputs), a
dual 2 to 4 Line decoder is as shown below:

2) 2 to 4 Line decoder (active high):

Logic circuit for 2 to 4 Line decoder Truth table:
(Active high):
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DIGITAL ELECTRONICS [17ECL38]

3) 74139 Dual 2 to 4 Line Decoder

The IC chip 74LS139 has two binary decoders. In addition to and Ground, each
decoder has two inputs A and B, and 4 outputs Y0, Y1, Y2 and Y3. Moreover, an
input is used so that the circuit will function only when .

Truth Table:
The truth table for another half is same as first half.
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4) Realization of Boolean Expressions

i) Half Adder :S= Σ (1,2); C= Σ (3)
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ii) Full Adder :S= Σ (1,2,4,7); C= Σ (3,5,6,7)

Truth table of 3:8 decoder realized using two 2:4 decoder (74139)
INPUT OUTPUT
C B A Y0=1Y1 Y1=1Y2 Y2=1Y3 Y3=1Y4 Y4=2Y1 Y5=2Y2 Y6=2Y3 Y7=2Y4
0 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 1 1 1 1 1 1
0 1 0 1 1 0 1 1 1 1 1
0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 1 1 1 0 1 1 1
1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0

Result: The Realization Boolean Function using DECODER is verified.

QUESTIONS:-
1. What is Decoder/Encoder ? What are its application?
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DIGITAL ELECTRONICS [17ECL38]

2. Write one real time application

3. Can decoder be used as Demux?
4. Write applications of Demux.

Experiment-7
FLIP-FLOPS
Aim: To realize Master-Slave JK, D and T Flip-Flops using NAND Gates.
Learning Objective:
1. To learn about various Flip-Flops
2. To learn and understand the working of Master slave FF
3. To learn about applications of FFs
4. Conversion of one type of Flip flop to another
5. Analyze timing diagram of flip flops

Components Required: IC 7400, IC 7410, IC trainer kit and patch cords

Theory:
▪ Basically Flip-Flops are the bistable multivibrators that stores logic 1 and logic 0.Shift
registers, memory, and counters are built by using Flip – Flops. Any complex sequential
machines are build using Flip – Flops. Sequential circuit (machine) output depends on the
present state and input applied at that instant.
▪ The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic
sequential logic circuit possible. This simple flip-flop is basically a one-bit memory bi-stable
device that has two inputs, one which will “SET” the device (meaning the output = “1”), and
is labeled S and another which will “RESET” the device (meaning the output = “0”), labeled
R.
▪ Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop back to its
original state with an output Q that will be either at a logic level “1” or logic “0” depending
upon this set/reset condition.
▪ JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a
universal flip-flop circuit. The sequential operation of the JK flip flop is exactly the same as
for the previous SR flip-flop with the same “Set” and “Reset” inputs. The difference this time
is that the “JK flip flop” has no invalid or forbidden input states of the SR Latch even when S
and R are both at logic “1”.
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DIGITAL ELECTRONICS [17ECL38]

▪ The JK flip flop is basically a gated SR flip-flop with the addition of a clock
input circuitry that prevents the illegal or invalid output condition that can occur when both
inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop
has four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”.
▪ A D flip flop has a single data input. This type of FF is obtained from the SR FF
by connecting the R input through an inverter, and the S input is connected directly to data
input. The modified clocked SR flip-flop is known as D-flip-flop and is shown below. From
the truth table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable
state when the inputs are same and high.
▪ T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop.
Both the JK inputs of the JK flip – flop are held at logic 1 and the clock signal continuous to
change.
Procedure:
1. Identify the IC required.
2. Check the components for their working.
3. Insert the appropriate IC into the IC base of the trainer kit such that the notch of the IC is
facing towards the Vcc, where the IC pin no. 7 and 14 are connected to ground and VCC
respectively.
4. Make connections as shown in the circuit diagram. Switch on the power supply.
5. Provide the input data via the input switches as per the truth table and observe the output on
output LEDs.

1) SR FLIP FLOP

(A) LOGIC DIAGRAM (B) SYMBOL

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DIGITAL ELECTRONICS [17ECL38]

2 ) D FLIP FLOP

(A) LOGIC DIAGRAM (B) SYMBOL

3. JK-FLIP FLOP
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DIGITAL ELECTRONICS [17ECL38]

LOGIC DIAGRAM TRUTH TABLE

4) T-FLIP FLOP

LOGIC DIAGRAM TRUTH TABLE

4)JK MASTER SLAVE FLIP FLOP

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DIGITAL ELECTRONICS [17ECL38]

LOGIC DIAGRAM

TRUTH TABLE: (PRE = CLR = 1)

PROCEDURE :

· Check all the components for their working.

· Insert the appropriate IC into the IC base.

· Make connections as shown in the circuit diagram.

· Verify the Truth Table and observe the outputs.

Result: All the Flip-Flops has been verified.

QUESTIONS:-
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DIGITAL ELECTRONICS [17ECL38]

1. What is the difference between Flip-Flop & latch?

2. Give examples for synchronous & asynchronous inputs?

3. What are the applications of different Flip-Flops?

4. What is the advantage of Edge triggering over level triggering?

5. What is the relation between propagation delay & clock frequency of flip-flop?

6. What is race around in flip-flop & how to over come it?

7. What are multivibrators ? Explain astable, monostable and bistable. Give example for each

Circuit Diagram of Master Slave JK Flip-Flop

Truth table for Master Slave JK Flip-Flop

Preset Clear J K Clock Qn+1

0 1 X X X 1 0 Set
1 0 X X X 0 1 Reset
1 1 0 0 Qn No Change
1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
1 1 1 1 Qn Toggle
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Circuit Diagram of D Flip-Flop

Truth table for D Flip-Flop

Preset Clear D Clock Qn+1
1 1 0 0
1 1 1 1 0

Circuit Diagram of T Flip-Flop

Viva Questions:

1. Give the comparison between combinational circuits and sequential circuits.

2. Define synchronous & Asynchronous sequential circuit.
3. What is the difference between latch and flip-flop?
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DIGITAL ELECTRONICS [17ECL38]

4. What are the functions of preset and clear inputs? Are they synchronous or asynchronous?
5. List various types of flip-flop with their abbreviations.
6. What is the difference between toggling and race around condition? How race around
condition can be overcome?
7. How do you convert JK flip-flop into a D flip-flop?
8. Write the characteristic equations of SR, JK, T and D flip-flop
9. What are the applications of different Flip-Flops?
10. What is the advantage of Edge triggering over level triggering?
11. What is the relation between propagation delay & clock frequency of flip-flop?

Experiment- 8
SHIFT REGISTERS
Aim: To realize the following shift registers using IC7495
(a) SISO (b) SIPO (c) PISO (d) PIPO (e) Ring (f) Johnson counter.

Learning Objectives:
1. To illustrate the operation of shift registers
2. To study different shift register configurations

Components Required: IC7495, IC Trainer Kit and Patch Cords

Theory:
▪ Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They
are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
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DIGITAL ELECTRONICS [17ECL38]

the input of the next flip-flop. All the flip-flops are driven by a common clock, and all are set
or reset simultaneously.
▪ Different types of shift register are Serial in serial out shift register, Serial in parallel out shift
register, Parallel in serial out shift register, Parallel in parallel out shift register, Bidirectional
shift register shift register.
▪ The serial in/serial out shift register accepts data serially – that is, one bit at a time on a single
line. It produces the stored information on its output also in serial form.
▪ The serial in/parallel out shift register accepts data serially – that is, one bit at a time on a
single line. It produces the stored information on its output in parallel form.
▪ The parallel in/serial out shift register accepts data in parallel. It produces the stored
information on its output also in serial form.
▪ The parallel in/parallel out shift register accepts data in parallel. It produces the stored
information on its output in parallel form.
▪ A Ring counter also called as an Overbeck counter is a Shift Register (a cascade connection of
flip-flops) with the output of the last flip flop connected to the input of the first. It is
initialized such that only one of the flip flop output is 1 while the remainder is 0. The 1 bit is
circulated so that the state repeats every n clock cycles if n flip-flops are used. The "MOD" or
"MODULUS" of a counter is the number of unique states. The MOD of the n flip flop ring
counter is n.
▪ A Johnson counter also called as twisted ring counter or switched tail counter is a modified
ring counter, where the inverted output from the last flip flop is connected to the input to the
first. The register cycles through a sequence of bit-patterns. The MOD of the Johnson counter
is 2n if n flip-flops are used. The main advantage of the Johnson counter is that it only needs
half the number of flip-flops compared to the standard ring counter for the same MOD.
Johnson Counters can be used as phase shift square wave generator, clock divider.
▪ The primary application of the shift registers is to binary information in a register can be
moved from stage to stage within the register or into or out of the register upon application of
clock pulses. This type of bit movement or shifting is essential for certain arithmetic and logic
operations used in microprocessors.

PIN DIAGRAM:
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DIGITAL ELECTRONICS [17ECL38]

M=1 for parallel operation

M=0 for serial operation

1) SERIAL IN SERIAL OUT (SISO)-shift right:

2) SERIAL IN PARALLEL OUT (SIPO):

3) PARALLEL IN PARALLEL OUT (PIPO):

4) PARALLEL IN SERIAL OUT (PISO):

.
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DIGITAL ELECTRONICS [17ECL38]

Procedure:
a) SERIAL IN SERIAL OUT (SISO), SERIAL IN PARALLEL OUT (SIPO) and shift right:

(i) Connect mode control pin (pin no 6) to ‘0’ and apply serial data bit by bit at serial input (pin
no 1) terminal starting from LSB.
(ii) Apply clock pulses at clock-S (pin no 9) terminal after each data bit and observe output at QA
(pin no. 13) as serial out from 1st clock pulse upto 4 th clock pulses.
(iii)Now, Observe the outputs at Qa Qb Qc Qd which is SIPO.
(iv) Observe that serial data input is shifting right every time input and clock is applied. This is
shift right operation.

b) PARALLEL IN PARALLEL OUT (PIPO) and PARALLEL IN SERIAL OUT (PISO):

(i) To load the parallel input data in to the shift register ( ie to make Qa Qb Qc Qd = parallel input
data)
● Connect mode control pin no. 6 to ‘1’. The parallel inputs A, B, C, D to be loaded into shift
register are given to pin no 2,3,4,5 respectively.
● Clk P (pin no 8) is pulsed only once. Now, A, B, C, D parallel inputs appear at the respective
outputs QA, QB, QC, QD. This is PIPO.
(ii) To get this parallel data as PISO on Qd line
Connect mode control (pin no 6) to ‘0’ and apply 3 clock pulses at clock S (pin no 9) and observe the
output at Qd as serial out.

(ii) Ring and Johnson counter.

i) RING COUNTER

LOGIC DIAGRAM:
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DIGITAL ELECTRONICS [17ECL38]

TRUTH TABLE:

CP QA QB QC QD
t0 1 0 0 0
t1 0 1 0 0
t2 0 0 1 0
t3 0 0 0 1
t4 1 0 0 0
t5 0 1 0 0
t6 0 0 1 0
t7 0 0 0 1
t8 1 0 0 0

Procedure:

ii) JOHNSON COUNTER

LOGIC DIAGRAM:

TRUTH TABLE:

CP QA QB QC QD
t0 1 0 0 0
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t1 1 1 0 0
t2 1 1 1 0
t3 1 1 1 1
t4 0 1 1 1
t5 0 0 1 1
t6 0 0 0 1
t7 1 0 0 0

Procedure:

Result: (i) All the shift operations are verified.

(ii) Truth tables of Ring counter and Johnson counter are verified.
Viva Questions:
1. What is shift register and mention their types.
2. Shifting a register content to left by one bit position is equivalent to
3. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the
nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
a)1100 b)0000 c)0011 d)1111

4. What is Johnson counter? What are its advantages over ring counter?
5. What is ring counter? Mention its applications.
6. Differentiate between serial data & parallel data.
7. What is the significance of Mode control bit?
8. Which shift register type would have a complete binary number shifted in one bit at a time
and have all stored bits shifted out one at a time?
a) SIPO b) SISO c) PIPO d)PISO
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Experiment- 9
MOD-N COUNTER USING IC 7490 and IC 74192
Aim: To realize (i) Mod-N Asynchronous Counter using IC7490
(ii) Mod-N Synchronous Counter using IC74192
Learning Objectives:
1. To learn about Asynchronous and Synchronous Counter and its application
2. To learn the design of asynchronous and Synchronous up counter and down counter
Components required: IC 7490, IC trainer kit, patch cords
Theory:
Counter is a sequential circuit which is used for counting pulses.
Counter is the widest application of flip-flops. It is a group of flip-
flops with a clock signal applied. Counters are of two types.
Asynchronous or ripple counters and Synchronous counters. Depending
on the way in which the counting progresses, the synchronous or
asynchronous counters are classified as follows −Up counters, Down
counters and Up/Down counters
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The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-8
counter. So in general, an n-bit ripple counter is called as modulo-N counter. Where, MOD
number = 2n. Application of counters are Frequency counters, Digital clock, Time measurement,
A to D converter, Frequency divider circuits etc.
The 7490 is a BCD/decade counter that consists of four Master-Slave JK flip-flops internally
connected to provide Mod-2 (Divide by 2 ) and Mod-5 Counter(Divide by 5). It can count from 0 to 9
cyclically in its natural mode. It counts the input pulses and the output is received as a 4-bit binary
number through pins QA, QB, QC and QD. The binary output is reset to 0000 at every tenth pulse and
count starts from 0 again. The Mod of the IC 7490 is set by changing the RESET pins R0 (1), R0 (2),
R9 (1), R9 (2). It is possible to increase the counting capability of a Decade number by connecting
more ICs n series.

The 74192 is a Presettable Synchronous 4-Bit Up/Down Decade Counter.Presetting the counter to
the number on the preset data inputs (Input A - Input D) is accomplished by a LOW asynchronous
parallel load input (Load). The counter is incremented on the low-to-high transition of the UP input
(and a high level on the Clock- DOWN) and decremented on the low to high transition of the
DOWN input (and a high level on the UP input). A high level on the CLR input overrides any other
input to clear the counter to its zero state. The Terminal Count up (CO) goes low half a clock period
before the zero count is reached and returns to a high level at the zero count.

The Terminal Count Down (BO) in the count down mode likewise goes low half a clock period
before the maximum count (9 in the 74192) and returns to high at the maximum count. Cascading is
effected by connecting the CO [carry] and BO [borrow] outputs of a less significant counter to the
Clock-Up [UP] and Clock-Down [DOWN] inputs, respectively, of the next most significant counter
Procedure:
1. Connections are made as per the logic diagram.
2. Apply the clock pulses and verify the truth table.

Pin Diagram:

Internal Diagram:
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Conditional Table:

(a) IC 7490 as BCD/ Decade Counter

Truth Table:

(b) IC 7490 as MOD-8 COUNTER:

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Truth Table:

Clk QD QC QB QA
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1

PIN DETAILS OF IC-74192:

a) COUNTER WHICH COUNTS FROM 8 TO 0

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b) COUNTER WHICH COUNTS FROM 7 TO 0

NOTE: After 1001, output becomes 0111.

Result: Mod-N Asynchronous Counter using IC7490 and Synchronous Counter using IC74192 is
realized and verified.

Viva Questions:
1. How many flip-flops are required to construct a decade counter
a) 10 b) 3 c) 4 d) 2
2. How many flip-flops are required to construct mod 30 counters?
a) 5 b) 6 c) 4 d) 8
3. Is 7490IC a synchronous or asynchronous counter?
4. What are synchronous counters?
5. What are the advantages of synchronous counters?
6. What is an excitation table?
7. Write the excitation table for D, T FF
8. Design mod-5 synchronous counter using T FF?
9. What is a presettable counter?
10. What are the applications of presettable counters?
11. Explain the working of IC 74193
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EXPERIMENT- 10

PSEUDO RANDOM SEQUENCE GENERATOR USING 7495.

Aim : Design Pseudo Random Sequence generator using 7495.

Components required: IC 7495, IC trainer kit, patch cords

Theory:
Maximum Length PN sequences are binary sequence generators that are capable of outputting all
possible combinations of binary sequences in 2m where m is the size of the LFSR (Linear Feedback
Shift Registers ) used in generating sequences. Terms like Pseudorandom binary sequences (PRBS)
or pseudonoise sequences are also used to refer m-sequences.
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To generate a 2m -sequence, feedback connection of LFSRs are connected according to a primitive

polynomial (generator polynomial).

DESIGN 1: Generator polynomial = 1+X3 +X4

1+X3 +X4 = 1 X0 + QA X1 + QB X2+ QC X3 + QD X4

X0 coefficient is ‘1’ and connected to serial input

X1 coefficient is ‘0’ and QA is kept open
X2 coefficient is ‘0’ and QB is kept open
X3 coefficient is ‘1’ and QC is connected to XOR input
X4 coefficient is ‘1’ and QD is connected to XOR input

Sequence length S = 24-1= 15

DESIGN 2: Generator polynomial = 1+X2 +X3

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Sequence = 1001011 Sequence length S = 7

PROCEDURE:

• Check all the components for their working.

• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Initially load ABCD=1111 with M=1
• Make M=0 for shifting operations
• Verify the Truth Table and observe the outputs.

INTRODUCTION TO MULTISIM SIMULATION TOOL

Multisim is an electronic schematic capture and simulation program which is part of circuit design
programs. Multisim was originally created by a company named Electronics Workbench, which is a
division of National Instruments. Multisim is an industry-standard, best-in-class SPICE simulation
environment. It is the teaching solution to build expertise through practical application in designing,
prototyping, and testing of analog, digital and power electronic circuits. The Multisim helps in
prototyping various circuits and optimize it before realizing any circuit on printed circuit board
(PCB).

Multisim can be used to simulate digital, analog and power electronics circuits based on the
application. This helps in faster realization providing graphical visualization. It is used across all the
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industries for faster simulation of the circuits. Multisim has over 36,000 components validated by
leading semiconductor manufacturers. The Multisim library of has up-to-date amplifiers, diodes,
transistors, and switch mode power supplies paired with advanced simulation makes it possible to
cover a wide variety of application specific design.

Multisim includes microcontroller simulation, integrated circuits and also provide an option to import
and export features to the Printed Circuit Board layout software for further realization of the
hardware board. Multisim is widely used in academia and industry for circuit’s education, electronic
schematic design and SPICE simulation. Students can use Multisim to optimize their circuit design
performance and save prototype iterations in different application areas such as analog design, power
electronics, renewable energy, and complete analog/digital system level designs.

STEPS FOR CONDUCTING EXPERIMENTS USING ‘MULTSIM 14.0’

SIMULATION TOOL

1. Click on ‘Multisim 12.0’ on the desktop.

2. Open/Create Schematic
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A blank schematic Circuit 1 is automatically created. To create a new schematic click on File – New
– Schematic Capture. To save the schematic click on File /Save As. To open an existing file
click on File/ Open in the toolbar.

3. Place Components

To Place Components click on Place/Components. On the Select Component window, click on

Group-> All groups. Type the components needed for the circuit. Click OK to place the component
on the schematic.

4. Place the selected component on the schematic.

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5. Rotate Components: To rotate the components right click on the component and click on rotate
90 Clockwise (Ctrl +R) or rotate 90 Counter Clockwise (Ctrl+Shift+R).

6. Place Wire/Connect Components: To connect components, click on Place/Wire drag and place
the wire. Components can also be connected by clicking the mouse over the terminal edge of one
component and dragging to the edge of another component. (Refer Figure 6).

Figure 6
7. Validation of Input and Output (Refer Figures 7a & 7b)
● To give input, Click on Place -> components-> All Groups-> Type SPDT(Single Pole
Double Throw) switch in component icon.
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● Click on Place -> components-> Groups -> Select sources-> Type VCC in component icon.
● Click on Place -> components-> Groups -> All Groups-> Type DGND(Digital Ground) in
component icon.
● To observe the output, Click on Place -> components-> Groups ->Select Indicators-> Probe.
● Connect the above components using wires.

Figure 7a

Figure 7b

8. Simulation: To simulate the completed circuit Click on Simulate/Run or F5. This feature can also
be accessed from the toolbar.
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Experiment No: 11
SIMULATE FULL ADDER USING SIMULATION TOOL
AIM: To simulate full adder using basic logic gates using Multisim.

APPARATUS REQUIRED: PC, Multisim software

COMPONENTS:7486N, 7432N,7408N,Vcc,Ground,SPDT,Probe,wire

THEORY:
Multisim is the schematic capture and simulation application of National Instruments Circuit Design
Suite, a suite of EDA (Electronic Design Automation) tools that assists you in carrying out the major
steps in the circuit design flow. Multisim is designed for schematic entry, simulation, and exporting
to downstage steps, such as PCB layout.

LOGIC DIAGRAM OF FULL ADDER

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TRUTH TABLE FOR VERIFICATION

INPUT OUTPUT
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SIMULATION OUTPUT
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RESULT: full adder circuit using basic logic gates is simulated using Multisim and the truth table is
verified.

Experiment No: 12
SIMULATE MOD 8 SYNCHRONOUS UP/DOWN COUNTER USING
SIMULATION TOOL
AIM: To simulate mod 8 synchronous up/down counter using Multisim.

APPARATUS REQUIRED: PC, Multisim software

THEORY
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter.
Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. If
the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is
called as synchronous counter.
Modulus Counter (MOD-N Counter)-
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A 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-8
counter. So in general, an n-bit ripple counter is called as modulo-N counter. Where, MOD number
= 2n .

A mod-8up counter counts from 0 to 7. It stores the initial value, and increments that value on each
clock tick, and wraps around to 0when the count reaches 7. So, the stored value follows a cycle: 000
001 010 011 100 101 110 111

A mod-8down counter counts from 7 to 0. It stores the initial value, and decrements that value on
each clock tick, and wraps around to 7when the count reaches 0. So, the stored value follows a
cycle: 111110 101 100 011 010 001 000

OBSERVATION
For Mod 8 up counter- 0 ,1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3,……
For Mod 8 down counter- 7, 6, 5, 4, 3. 2, 1, 0, 7, 6, 5, …….

For Mod 8 up/down counter-

switch connected to Vcc- down counter 7, 6, 5, 4, 3. 2, 1, 0, 7, 6, 5, ……
switch connected to Gnd- up counter 0 ,1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3,……

MOD 8 UP COUNTER CIRCUIT

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MOD 8 DOWN COUNTER CIRCUIT

MOD 8 UP/ DOWN COUNTER CIRCUIT

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RESULT-
Mod 8 synchronous up counter, down counter and up/down counter are simulated using Multisim and
the output sequence is observed.
EXPERIMENT NO: DATE:
TITLE:

SUMMARY OF THE EXPERIMENT WITH RESULTS:

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SIGNATURE OF THE LAB INCHARGE

EXPERIMENT NO: DATE:

TITLE:

SUMMARY OF THE EXPERIMENT WITH RESULTS:

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SIGNATURE OF THE LAB INCHARGE

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