* Let us consider the Full Adder circuit :

}£"
a

This stem drives

° ☐ "" " " """" *
"
Mh" " Mt ""

both S and

te
cont
→
so a
fault in this
Cin ☐ ( out
stem can either be

detected using the

s
b
coat

so
or

t,
.

ein ☐
of
can use one
we
any
them to detect in
a
fault
this stem because this stem

is common between them ( it

drives both s and cont) .

Suppose there is a
fault in the wire
highlighted in red

b.
So for off define what is the Otp
every ,
we called as cone
of the .

=
Find out all the
primary inputs &

the related
circuitry responsible for
this Otp .
 a. =D
-2
÷=D#
=D
?#
""
a

s
-
ein
b

-
-
Cone sum
of
cone carry out
of
-

NOTE ① In practice have multi input multi output circuits

usually
:
we - -

.
,

te
So what do is find the each these outputs
we
,
we cone
of of .

te
'

↳
'

Suppose there are n outputs .

then there will be

/ gate n' single

'

↳ A wire inside the circuit can

belong to more than one -

olp circuits
.

6
↳ So for each wire need find test vector the fault in
,
we to a
for it
,
that will detect

the in these circuits

same
any one
of n
.
 te
↳
Eg Suppose there is a wire common to both 01 & 0s ,
&
say if
s @0 fault in that wine is detected

in the ckt need not bother about

Oi then we
checking for it in 0s
-

.
,

te
Out
of all the cones a
particular wire
belongs to
,
find at least one cone and a test vector which will

detect a fault in that wire .

NOTE : ① Now for the entire discussion henceforth ,

we will assume that there is a single Otp circuit .

te
'

↳ In
practice
'

,
we have multi -

olp circuits
,
but we can treat that multi -

op ckt as n

circuits
single olp .

6
↳ we circuit
will assume that
given a
single olp ,
we want to find test vectors that cover

all single stuck -

at faults in that circuit .

6
' '

If we do it for all n
single -

olp circuits ,
then
every
wire will
get covered .

-
✗ ✗
 NOTE :
Q Why do consider single stuck at faults ?
only
.
we -

'

Ans=_ consider n' input output boolean circuit

Let us a -

single .

to
Q .
Does there exist an input n - bit vector that can make the olp = 1 ?
to
EE ① ②

0=132
✗ ¥7k 1

É →
-

:#
te
te
Ans =
Yes No such input exists
(0×00) that can make o1p=1

Satisfiability
To find such an
input vector
algorithmically ,
we can think
of a trivial age . ( to test

each
input combination
from the truth table ) which takes 0 ( 2n ) time
complexity .

te
↳ For this problem ,
there is no
polynomial time
complexity algorithm .
This problem is the

famous
satisfiability Problem ,
@ hick is
NP-complete )
b
Suppose & to ( say ) s@
we have a
very large ckt ,
we want test for a 0 fault in the wire shown .

)
?⃝
 )
I

So ,
in order to test s@ 0
fault ,
we need to drive a 1 on that wire .
( Fault sensitization )
•
↳ Now need
,
We to
perform fault propagation .

te
↳ SO the
,
we need to affix non -

controlling values to G , & Gz to be 0 .

Solve
satisfiability
problem
↳
y
{ {I z
Now to do =
s@ 0
fault analysis we need such input

#
,
,

values to drive 1 at the

faulty wire &
simultaneously I

f.
at
drive a 0 non -

controlling wire
of Gi .

I •

£
↳ solve multiple satisfiability problems ! Solve another

& satisfiability problem . . .

and soon . . .

Perhaps this is
why we use the
single stuck - at
fault
at
model ,
as
analyzing more than I stuck -

fault becomes
computationally intractable
due to the
presence of satisfiability problem .

As this is
far as course concerned ,
we will be
dealing with multi -

input multi -

output circuit .

6
since
↳ But
nwe can make it into cones
,
we deal with multi -

input single -

output circuits .

te
at test
And in each
of them ,
we look
generating vectors for each one
of the single stuck - at
 fault .
We dont assume more than one wire to be
faulty because that will make

the entire problem non -

tractable .

←
→→ -

MOT ① The
synthesis tool doesnt require 012^1 to
analyze stuck -
at
faults .

to
↳ used
some
optimized ages .

are .

→ → -

* n -

input single -

output circuit :

↳
( find out all the
single stuck - at
faults in the circuit .

te
We will now start
focusing on Test Verification algorithms .

* Let us consider a circuit :

3 0
this output can
be either 0 or 1 .

I
 In this circuit is 0
>
,
it possible to
get or 1
very quickly .

6
↳ Q do ?
.
How we
prove it
te
And We use the technique of Induction to prove this :

te
Let levels circuits ( ckt dig above )
define in for logic gates
the see .

us
.

↳*
The level 0
primary inputs at -

are .

* The output is (Max

of input
1)
level
of of a
gate .
level + .

We
perform Induction on levels : ( consider basic
gates only )

For
÷
-
1 : 1=1 ,
there will be a
single gate
Base
cast For each
of the basic
gates ,
we can
get a 01g as output .( Evident from
Truth Table
of
the

the gate )
↳ Ckt level I 1
of
=
can
give olp =
on

k Let it is true circuits level

for all
of
:
K
us
say
=
.

te
↳ Let us consider 1=(1-+1) .
We can
generate any input combination required by 1--4<+1 ) as each
gate
 in level is either 011 output So Cktl )
=
K capable of producing as
.
the level __

gate can also produce

011 as
output .

6
↳ The
particular combination
of inputs required by the
gate at level -4<+1 ) can be obtained
by multiple cones at level -
K to

produce the desired output (0/1) .

=
→→ -

NOTL① The theorem discussed above is true

only for a fan - out
free circuit .

6
*
Satisfiability problem for a circuit without fanout has
polynomial time
complexity .

*
Satisfiability problem for a circuit WITH fan out has exponential time
complexity .

-
→ → -

Refer Pg -
183 to 18
his
next
topic .
AT Consider a multi -

input single -

output circuit .
It has a wire l which is stuck at v
,

te
I want to find a test vector that will detect l s @ v.

}
"" " " " ^ " "" "
" " " "" " "*
*

begin :

set all values to se

Justify ( e. E)

If 0=0 then ( e. D)
propagate
else
propagate ( e. 5)

end

*
Justify ( e. val )
: ( fig -
6. u Pg -
Isu ) ( line justification in a fanout -

free
circuit )

begin
set l to real

l is
if a
primary input then return

/* l is ( output) 1
a
gate *

c =
controlling value of l
 i inversion l
of
=

inval = val ⑦ i

if ( inxal = E)
then for
every input j of l

Justify ( j ,
inval )
else

begin
select one input ( j ) of l

Justify ( j ,
inxal )

end

end

( ) (
*
Propagate l Error
propagation
:
,
err in a fanout -

free circuit .

/* ere is D or 5 * I

begin
set l to err

if is
l
primary output then return

K =
the foment l
of

C
controlling value K
=

of
 i inversion K
of
=

for input than l

every j of K other

(j e)
Justify ,

Propagate ( k ,
err ④ i )
end

handled by Justify &

f- :S @0
need

}
now we

✗
⑦→ propagate { 1,1 }
Egf
to
b
g
Input =

,
0
,
✗
,
O detects f : s@0

i D ④ detatectepdo fault .

O c

po ↳ the
✗ d
g=o ago.
runs in
polynomial time
for this exam
µ.
I
as the ckt is fan out free .

°
e
h
O

Justify ( f. 1)
↳ : set a = I

b = I

f- =
I

Now need f- =D to
primary output ( Po )
,
we to
propagate .

te
↳ to do need to set 0
so
,
we
g= .

↳
?⃝
 6
↳ To
do so
,
we set c- 0
,
D= ✗

to i PO need
Now
propagate =D to
,
we h=1 .

6
↳ To do so ,
we set e= 0 .

NILE : Run the entire algo .

once to understand the flow
of the
algo .

→→ -

NOT ① We have to
generate the test vectors in order to catch stuck -
at
faults .

te
is
Test
generation strategy of
2
types
:

1) Fault Independent test generation

c. 2) Fault oriented test

generation

Generate random test vector & find output : once in the absence
of faults &

once in the presence of faults

to
 to
↳
If the olp matches in both cases ,
then this
randomly generated TY doesn't catch that stuck -
at

fault .
We check this
randomly generated Tv for all the stuck -
at faults present in our

ckt & those faults from the fault set that detected this
randomly
,
remove are
by
generated TV .

b
We
keep repeating this process with
different randomly generated TV until our fault set

becomes
empty .

÷
There
might be some
faults that are
difficult to detect ( or remain undetected )
by the Fault Independent TV
generation method
.

te
↳ So Fault
for these specific faults ,
we
generate TVs separately with the help of the
oriented Tv
generation method
.

NOT In this course ,

we will see a bunch
of
Fault Independent T V
-

generation methods

to
Then we will see 3 Fault oriented TV
generation methods .