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Lect Register EE208
Lect Register EE208
Shift Register: A group of FF connected to provide either entering or shifting in/out the data
Moving the data from one place to other:
2. Parallel Shifting:
Shifting all the data
simultaneously
Serial IN-Serial OUT
°The flip-flops used to construct registers are usually edge-triggered JK, SR or D types.
°Common clock triggers at –ve edge to all FF.
°As output of one FF is connected to input of next FF, at every trigger the data stored in one FF is
transferred to the next FF.
°Transferred takes place like: Q -> R, R-> S, S->T and the
serial data input is transferred to Q.
To shift a 0 into the flip-flop, J=0 and K=1, To shift a 1 into the flip-flop, J=1 and K=0
Serial IN-Serial OUT
Clock Serial Q R S D
input
0 0 0 0 0 0
1 1 0 0 0 0
2 0 1 0 0 0
3 0 0 1 0 0
4 0 0 1 0
Problem
°Draw the waveform to shift the number QRST=1010 into the shift
register shown in fig below.
0
8-bit Serial IN Serial OUT Register: RS FF
°8 RS FF required: 74 LS91
°How to convert D FF from RS FF: Inverter should be connected
between R and S on the first FF.
0/1
R Q bar
Clock
B is Control line
1 (high) / 0 (low)
A typical response of a 54/74164
B is held high: NAND gate is enabled and the serial input data is passes through NAND
gate inverted.
B is held low: The NAND gate output is forced high,
Parallel IN-Serial OUT
54/74166, 8FF + Logic Circuits
D Q D R D S D T
0 1 0 0 0 0 1
_ _ _ 1 1 1 0 0 0 0
_
Q R S T
2 1 1 1 0 0 0
3 1 1 1 1 0 0
CLK
Y 4 0 1 1 1 1 0
5 0 0 1 1 1 0
6 0 0 0 1 1 0
7 0 0 0 0 1 0
{
{
1
Serial Data in 0 1 1 1
1 0 1 1
Sequence to be detected
Applications of shift registers
°SERIAL ADDER
S2
Serial Out Full Adder
Serial in S1 S0 A7 A6 A5 A4 A3 A2 A2 S2
Ai Si
B2
Bi
C1 Ci - 1 Ci C2
serial in
Q D
B7 B6 B5 B4 B3 B2
Serial Out
CLK