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Problem—012 Design and implement a gated oR Ladeh uging only NAND gates with asynchronous PRESET (active toc) and CLEAR (active Low)- Lirewens quired ingfruments? @ Te-wto (2 pieces) iG denigtic es mesic! cox] 2 | R | aut | tate | Gen [ox | Tnvaltd | Alot Used | reels xl [9 Se} ja] io | x | x | x] 6 | act 1/4) 0] x) X | Qh | Memory | ft} af a] of o[ g, | Memory | Ladi | Aeao; 1 | 6 | Reset | ifajajafol] 4 | et 4a} 4) 2 | 4 | Tavalid) Nol used Excitation Table Te te RG om cu] o | | AS iao K Ape '® cael [afa}e [xia eee) 4/0 Ie | aes a 0 Hiatal | A | ie ete A oO. eee |” | pl | x | 4 oh ee e : Ejeet 18 | 2 | 0 dal Soke | eee | eee er . ata 4 |x 0 | Cirowit Diaguam: | PRESET ; 3g elR— Problem 02 ‘8 Exdend the cineui{ tmplemented fn (4) to make a recline edged ‘tiggened master-elaye D-flip Mop with asynchronous PRESET (active low) ond CLEAR (active fos) using only NAND gates - Use the ctneuit of (4) as the slave part. Lisiens. @ 7400-7 (41 pieces) @ vAto-Te (2 pieces) acteristic tables PRESET | Gene | ck | > | Gens ote fe) O | X | X | Tnvalid| Net used ° ab x x 4 Sot Fifa| Opal ree Ses Or La react 2 4 x X | Oy | Memony yt clone] 05 lo; “lboReael “hgtdl “deluge aclpiae | cliccl (4 ° ~S i a x | ] | —— | | Lor | Js] B © 7404 te (4 pices) @© 773 Te (2 pieces) 2. Design sequential cimcuits to transform a T FF Prd ab Datel Katia [ | ey 5 a [> Sn [ t | na] Sup (So 20) 0 | | Ba t Leste | ols | Fe a eli |x 2 14] ai faa re) From _T -_J-K FFS ° Ext Tables a [kK (ilar OT eee | eo] Capo | 4 Olea 0 | Bie |e 4. ete meio | eae 1 a. [ro Petpet [ort | C020 ot 00 o] o| ofa [a] T= 39 +kg al aed ae Cinouit Diagyamn’ e a | ks 47 Ge 1? as | | [ee | Seas | JemAgce cc eee ents: O43 re (1 pies) @7432 Ic (4 pice) @ 7404 Tce (Leiece) @ 740 Te (4 prec) @ T FF From _D FF To _<+K FFE 5 raf aa © | ee Bead e BS 1.20. | jes On SO spe: | 1 | | 2 | 4 © | eo OF [68 [7 aarig02| of tet |. 07) Ope | 13) Late] 12h Gee ee One laa i eel [0 Poy

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