)MPUTER ORGANIZATION MAIN PARTS OF PROCESSOR i The processor contains ALU, control-circuitry and many registers. + The processor contains ,1* general-purpose registers R, through Res- + The IR holds the instruction that is currently being executed. + The control-unit generates the timing-signals that determine when a given action is to take place. + The PC contains the memory-address of the next-instruction to be fetched & executed. + During the execution of an instruction, the contents of PC are updated to point to next instruction. * The MAR holds the address of the memory-location to be accessed. + The MDR contains the data to be written into or read out of the addressed location. * MAR and MOR facilitates the communication with memory. GR > Instruction-Register, PC > Program Counter) (MAR > Memory Address Register, MOR Memory Data Register) STEPS TO EXECUTE AN INSTRUCTION 1) The address of first instruction (to be executed) gets loaded into PC. 2) The contents of PC (i.e. address) are transferred to the MAR & control-unit issues Read signal to memory. 3) After certain amount of elapsed time, the first instruction is read out of memory and placed into MOR. 4) Next, the contents of MDR are transferred to IR. At this point, the instruction can be decoded & executed. 5) To fetch an operand, it's address is placed into MAR & control-unit issues Read signal. As a result, the operand is transferred from memory into MDR, and then it is transferred from MDR to ALU. 6) Likewise required number of operands is fetched into processor. 7) Finally, ALU performs the desired operation. 3 If the result of this operation is to be stored in the memory, then the result is sent to the MOR. 9) The address of the location where the result is to be stored is sent to the MAR and a Write cycle is initiated. 10) At some point during execution, contents of PC are incremented to point to next instruction in the Prostar: y in CO, Hy Protos 5 men I morn ay Pnfriconnec fed a Syskry bus, which ¢ d qT al luekut bs Pv | & Slee ale te oa eo fee | | ie [sae 8 fe gence purpose reyister Figure 1.2. Connacion between the processor and the main memory Dui wsoS COMPUTER ORGA\ 0 aa oe ADDRESSING MODES. ; Adaccilfferent ways in which the location of an operand is specified in an instruction are referred tg 4 a Addressing Modes (Table 2.1). ‘Wale ‘Operand = Value i Register w BAe Ri Absolute (Direct) LOC EA=Loc Indiet iy EA=IRI} 00) BA {LOC} + ter ay An (REX Baewith ide Rj FA=(R}+ RA ‘ae with index XR) EAs (RI + IR +X nd oie Relative FO) EAm (PCL +x Aatoinerement iy A= (Ri ocrement Ri ‘Attodecrement ai (Decrement Ri, FA= (Ri) 2) Absolute Mode Register Mode 7 The operand is the contents of a register, 7 ARE tame (or address) of the register is given in the 1 fisisters are used as temporary storage locations * For example, the instruction Move R1, R2 #Copy content of register R1 into register R2. Absolute (Direct) Mode ra : = + The operand is in a memory-location, * The address of memory-location is given ex + The absolute mode can represent global vai * For example, the instruction Move LOC, R2 plicitly in the instruction. riables in the program, iCopy content of memory-location LOC into register R2. Immediate Mode + The operand is given explicitly in the instruction, ‘+ For example, the instruction Move #200, RO * Clearly, the immediate mode is only used Place the value 200 in register RO. to specify the value of a source-operand.INDIRECTION AND POINTERS ‘« Instruction does not give the operand or its address explicitly. '* Instead, the instruction provides information from which the new address of the operand can be determined. Pres, ‘+ This address is called Effective Address (EA) of the operand. Indirect Mode ‘The EA of the operand is the contents of a register(or memory-location). ‘The register (or memory-location) that contains the address of an operand is called a Pointer. + We denote the indirection by -+name of the register or — new address given in the instruction. E.g: Add (R1),RO_ ;The operand is in memory. Register Ri gives the effective-address (8) of w the operand. The data is read from location B and added to contents of ‘ am] ¥ c ‘Main 9° * memory ca a (2) Through @ general purpose register |b) Through a memory location Figure 2.11 leiroc oddessng. + To execute the Add instruction in fig 2.11 (a), the processor uses the value which is in register R1, a the EA of the operand. « It requests a read operation from the memory to read the contents of location B. The value read is the desired operand, which the processor adds to the contents of register RO. « Indirect addressing through a memory-location is also possible as shown in fig 2.11(b). In this case, the processor first reads the contents of memory-location, A, then requests @ second read operation using the value B as an address to obtain the operand. Move NET Move aU. Itabeanon Clear ” —+ 00rd e230 ro) i Decrement RL Baxi L008 Move mo stM Tigre 2.12 Use of indvec addveaing inthe pogion of igure 2 10 Program Explanation + In above program, Register R2 is used as a pointer to the numbers in the list, and the operands are accessed indirectly through R2. * The initialization-section of the program loads the counter-value n from memory-location N into Ri and uses the immediate addressing-mode to place the address value NUML, which is the address of the first number in the list, into R2. Then it clears RO to 0. + The first two instructions in the loop implement the unspecified instruction block starting at LOOP. * The first time through the loop, the instruction Add (R2), RO fetches the operand at locatic NUMI and adds jt to Ro, * The second Add instruction adds 4 to the contents of the pointer R2, so that it will contain the address value NUM2 when the above instruction is executed in the second pass through the loop. SEEa : COMPUTER ORGANIZATION = = | : INDEXING AND ARRAYS a + Aydiferent kind of flexibility for accessing operands is useful in dealing with lists and arrays, On Index moda AS = The operation ERE oe ce} afea efines an offset(also called a displacement, re where X=the constant value which defines an o - ‘ Ri=the name of the index register which contains address of a new location, “ + The effective-address of the operand is given by EA-X+[Ril] & sagneccontents of the index-reaister are not changed inthe process of generating the effective. : + The constant X may be given either * 85 an explicit number or * 8S a symbolic-name representing a numerical value. (2) Otvetis gen a a constant Otek isin the incor rgistor ba Fowe212. ieexed oddrening . 3dak®) Illustrates two ways of using the Index mode, In fig(a), the index register, R1, contains the agaress of a memory-location, and the value % Gefines an offset(also called a displacement) from this 2GGress to the location where the operand is foura: * To find EA of operand: Eg: Add 20(R1), R2 EA=>1000+20=1020 tran atternative use is illustrated in fig(b). tiere, the constant X corresponds to a memory address, and ne index register define the offset to the Operand. In either case, the effective-address 's the sum of two values; one is given explicitly in the instruction, and the other is stored in a register. Move LST Loor EEEEFERRE S RI SUM) R2.SUME Ba, SUMS — in occesing 7 Figure 2.15, Indexed addressing vied Fag 2.14 Abst oh sucent’ movis test scores i the isin Figure 2.14 FFELT 3 132Base with Index Mode '* Another version of the Index mode uses 2 registers which can be denoted as (Ri, Ri) '* Here, a second register may be used to contain the offset X. » The second register is usually called the base register. * The effective-address of the operand is given by EA=[Ri] +{RJ] * This form of indexed addressing provides more flexibility in accessing operands because both components of the effective-address can be changed. Base with Index & Offset Mode * Another version of the Index mode uses 2 registers plus a constant, which can be denoted as X(Ri, Rj) * The effective-address of the operand is given by EA=X+(Ri]+[Ri] * This added flexibility is useful in accessing multiple components inside each item in a record, where the beginning of an item is specified by the (Ri, Rj) part of the addressing-mode. In other words, this mode implements a 3-dimensional array. RELATIVE MODE * This is similar to index-mode with one difference: The effective-address is determined using the PC in place of the general purpose register Ri + The operation is indicated as x(PC). + X(PC) denotes an effective-address of the operand which is X locations above or below the current contents of PC. * Since the addressed-location is identified “relative” to the PC, the name Relative mode is associated with this type of addressing. + This mode is used commonly in conditional branch instructions. * An instruction such as Branch > 0 LOOP —_;Causes program execution to go to the branch target location identified by name LOOP if branch condition is satisfied. ADDITIONAL ADDRESSING MODES 1) Auto Increment Mode > Effective-address of operand is contents of a register specified in the instruction (Fig: 2.16) > After accessing the operand, the contents of this register are automatically incremented to point to the next item ina list. > Implicitly, the increment amount is 1. > This mode is denoted as (Rij+ — jwhere Ri=pointer-register. 2) Auto Decrement Mode > The contents of a register specified in the instruction are first automatically decremented and are then used as the effective-address of the operand. > This mode is denoted as -(Ri) _ jwhere Ri=pointer-register. > These 2 modes can be used together to implement an important data structure called a stack. a Vee tb Hein on voor kas RD = toes cot Looe Move ___ROSUM Froww 216 Se. \\/ COMPUTER ORGANIZATION By { REGI: (RTN) fon 2) 2 + The penne ed = ‘ ‘are: 1) Memory-location 2) p-. oe fegister & 3 s [Description & ‘Contents of memorylocation | ae transferred into register ‘Add the contents of register and places their sum into 83 F Contents of 1/0 register DATAIN 5 ‘ transferred into register R1 TRS] © (Raj RQ) RI €DATAIN assembly lat format is used. Transfer data from memory location LOC to register Ri. The contents LOC are unchanged by the execution of this instruction, but the old contents of register Rl are overwritten -Source2, Destination | Add ABC Add the contents of | Move 8, C ‘memory-locations A&B. | Add A, C original contents of this location. ‘Operand B is both a source and a destination. Copy contents of memory- | Load A location A into accumulator. | Add B ‘Add B ‘Add contents of memory- | location B to contents of | accumulator register & | lace sum back into accumulator. | Store| Copy the cones of te toad A ‘accumulator into location C. ‘Opcode [no Source/Destination] Push ‘Locations of all operands | Not possible are defined implicitly. | ‘The operands are stored in 1 2 pushdown stack. than to data stored in memory-locations. The instructions: Access to data in the registers is much faster * Let Ri represent a general-purpose register. are generalizations of the Load, Store and Add Instructions for the single-accumulator case, in which register Ri performs the function of the accumulator. + In processors, where arithmeti ic operations as allowed only on operands that are in registers, the task C<-[A]+{8] can be performed by the instruction sequence: Move ARI Move B,Rj ‘Add Ri,Rj Move Rj,C EEE 132byte-addressable memory, successive addresses refer to successive byte locations in the r-. + Byte locations have addresses 0, 1, 2... ++ {If the word-length is 32 bits, successive words are located at addresses 0, 4, 8... with each word having 4 bytes, BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS * There are two ways in which byte-addresses are arranged (Figure 2.3). 1) Big-Endian: Lower byte-addresses are used for the more significant bytes of the word. 2) Little-Endian: Lower byte-addresses are used for the less significant bytes of the word rem eutn cases, byte-addresses 0, 4,8, .... are taken as the addresses of successive words inthe rY ri Consider a 32-bit integer (in hex): 0x12345678 which consists of & byte : sists of 4 bytes: 1: J. Hence this integer will occupy 4 bytes in memory, ce » Assume, we store it at memory address starting 1000, * On littie-endian, memory will look like Address | Value 1000 [78 [1001 —T's6- 1002 [34 1003 | 12 » On big-endian, memory will look like Address | Value 1000 }i2 1001 [34] 1002156] (003178 } WORD ALIGNMENT * Words are said to be Aligned in memory if they begin at a byte-address that is a multiple of the number of bytes in a word. + For example, > If the word length is 16(2 bytes), aligned words begin at byte-addresses 0,2, 4 . > If the word length is 64(2 bytes), aligned words begin at byte-addresses 0,8, 16..... + Words are said to have Unaligned Addresses, if they begin at an arbitrary byte-address. a) ———« R is measured in cycles per second. + Cycles per second is also called Hertz (Hz) / (este PERFORMANCE EQUATION «Let. T = Processor time required to executed a program. N = Actual number of instruction executions. .ded to execute one machine instruction. 5 = Average number of basic steps nee R = Clock rate in cycles per second. + The program execution time is given by Nx T= =(1) + Equl is referred to as the basic performance equation. 2 To achieve high performance, the computer designer must reduce the value of T, which means reducing N and S, and increasing R. 7 The value of Nis reduced if source program is compiled into fewer machine instructions. The value of 5 is reduced if instructions have a smaller number of basic steps to perform. «cone Zale valu of can be increased by using a higher frequency clock, 0 be taken while modifying values since changes in one parameter may affect the other JE 1-32 bal* design It refers to th Specifications, proncescribes the function of 2nd design of the various units of digital computer that store and Process information. ((tuneriona, UNITS, A computer consists of 5 functionaln 1) Input 2) Memory 3) ALU 4) Output & 5) Control units, 'y Independent main parts: Memory Aritumstic and lap = Invewonnee network Contest Process vo eo : Figure 1.1 Basic functional units of a computer. -‘cerind rn th tad fete tecnico con be -, ‘The value of T will be reduced by same factor as R is increased .." SBN are not a PERFORMANCE “he on anid awed how waa ec ne : hatch is eS ON + SPEC selects & ‘standard programs along Somains. (SPEC 5 orem Petes paterson ene * SPEC Rating is given by SPEC rating = 50 test is 50 times wee » The computer under * SPEC rating ME on he reference fast as reference-computer. prc atOmeti mean ofthe resus Conpeaea, Me ail apd £2 Brogram 4 in the suite, Overall spec ‘ating for the computer is given by 4 Issue @ Read comma And, then wait us 3. Transter the instructi 4, Transfer the addr 5 Ieee @ Head con 6, Transfer content 7, Transfer contents ot 4 Perform addition of 1 9. Transfer contents ¢ 10. Kd 1 to operand in ster the contents of register PC to Fogister MAR, nid to me mntil It haw ferred the requested word int Fegister MOR, lon From MOR into TR and decade \t, LOCA from 1K to MAR, and and wait Until MOI iy loaded, MOR to the ALU, FO) to the ALY. Ne two OfreraNds in the AL and Wransfer resuit into RO, PC to ALY, N ALU and transter incremented adtroas to PC,g sO COMP" Problem 1 aes Write a program that can evaluate the expression A*B+C*D In a sage seomaer GRE Assume that the processor has Load, Store, Mul accumulator Solution: A program for the expression is: Load A Multiply B Store RESULT Load C Multiply D ‘Add RESULT Store RESULT roblem 2: Registers R1 and R2 of a computer contains the decimal values 1200 and 4600. What is the effective- address of the memory operand in each of the following instructions? (a) Load 20(R1), RS (b) Move #3000,R5 (c) Store R5,30(R1,R2) (d) Add -(R2),R5 (e) Subtract (R1)+,R5 IZA’ Solution: (a) EA = [R1]+Offset=1200+20 = 1220 (b) EA = 3000 (c) EA = [R1]+{R2]+Offset = 1200+4600+30=5830 (d) EA = [R2}-1 = 45: (e) EA = [R1] = 1200 ) 10 Problem 3: Registers Ri and R2 of a computer contains the decimal values 2900 and 3300. What is the effective- ‘address of the memory operand in each of the following instructions? (a) Load R1,55(R2) (b) Move #2000,R7 (c) Store 95(R1,R2),R5 (d) Add (R1)+,R5 (e) Subtract-(R2),R5 . Solution: 2) Load R1,55(R2) > This is indexed addressing mode. So EA = 55+R2=55+3300-3355. b) Move #2000,R7 > This is an immediate addressing mode. So, EA = 2000 ©) Store 95(R1,R2),R5 > This is a variation of indexed addressing mode, in which contents of 2 genisters are added with the offset or index to generate. EA. So, 95+R1+R2=95+2900+3300=6255. d) Add (R1)+,R5 > This is Autoincrement mode. Contents of Ri are the EA so, 2900 is the EA. €) Subtract -(R2),R5 > This is Auto decrement mode. Here, R2 is subtracted by 4 bytes (assuming 32-bt processor) to generate the EA, so, EA= 3300-4=3296. Problem 4: Given a binary pattern in some memory-location, is it possible to tell whether this pattern represents a machine instruction or a number? Solution: 2 No; any binary pattern can be interpreted as a number or as an instruction.‘control flags(SIN) are used For this transfer, buffer-register DATAIN & status mn... + When a key is pressed, the corresponding ASCII code is stored in a DA m1 Ne SIN=1.-> When 2 characters typed in the keyboard, This informs the processor character is in DATAIN. When the characteris transferred to the processor. + An analogous proces takes pace when charac ore ancfered frm te processor tot For this transfer, buffer-register DATAOUT & a status control flag SOUT are used. > SOUT=1 > When the display is ready to receive acharacter. > SOUT=0 > When the characteris being transferred to DATAOUT. + The buffer registers DATAIN and DATAOUT and the status flags SIN and SOUT are part of cir Commonly «nown as 2 device interface. eas menoae ase Fame 19 nomen or pm, koro ag Program to ead + line of characters and Giaplay TC Moe #10C BOs pater miter RO to pa wo sds of theft atin in mecry ce the ares ae to be sore READ ‘Title #2INSTATUS Was or a character tobe ered Braet READ $5 the eyo bier DATAIN, . Move DATAIN.(20) Tater the cara ma DATA into . the memory thal SIN to 0), ECHO TexBit — $AOUTSTATUS Wait fo the dpi tn = play to become ready MoweBie (ROLDATAOUT Moe the charcer jt ed the pay aes reper (this cla SOUT to 0) Compare #CRRO}+ Chachi the character jst red a CR (encringe return). Iti ot CH, then Bennct#0 READ tatch bck aad read antes eharster Ako, eremeot the patter to store the on owen 1 Sooo | Fagor 2204 progam tat eats a be d oacen ond talon t ft +, Some address values are used to refer to peripheral device buffer registers sucl?as DATAIN & DATAOUT. ¢ No special instructions are needed to access the contents of the registers; data can be transferred Detween these registers and the processor using instructions such as Move, Load or Store. * For example, contents of the keyboard character buffer DATAIN can be transferred to register R1 in the processor by the instruction MoveByte DATAIN,R1 + The MoveByte operation code signifies that the operand size is a byte. * The Testbit instruction tests the state of one bit in the destination, where the bit position to be tested is indicated by the frst operand.UTION & STRAIGHT roa uted a follows is cae » ial, the Address of the first instruction ae Instructions, one or (cro circuits use the information in the PC to fetch and execute ions, one at a time, in the order of oe Of increasing addresses. T 3) During the execution iction, : of each instruction, Pc i There ae 2, hases for Instruction Execution: The instruction is fetched fr ed from the memory-location and placed in the 1. 2) Execute Phase: The contents of 1R is examined to determine which operation Is to be med. The specified-operation is then performed by the proce | loaded into PC (Figur 6 is called Straight-Line 6 incremented by 4 to point to ne sigeea Boe [asa | Perec; [Tiere | 1, aaa Eee as 2. | een oa ae num : | aoa) Figure 2.8 A pogrom or Program Explanation * Consider the program for adding a list of n numbers (Figure 2.9). + The Address of the memory-locations containing the n numbers are symbolically given 2s. NUM1, NUM2.....NUMD, * Separate Add instruction is used to add each number to the contents of register RO. * Afterall the numbers have been added, the result is placed in memory-location SUM.) Fin 29 sempre rete) 132