Clock Clock

Domain1 Domain2

Clock Domain Crossing: Issues &

Solutions
Udit Kumar, PhD, IIT Delhi.
16+ years experience, Author
https://www.linkedin.com/in/udit-kumar-phd-iit-delhi

Website: https://www.sites.google.com/view/learnvlsi
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Outline
⚫ What is Clock Domain Crossing (CDC)
 The Problem
 Leads to Chip Failure, No software fix!!
⚫ CDC Issues & Solutions
 Control Crossing
 Synchronizer
 Reconvergence
 Divergence
 Slow to Fast Crossing
 Passing a Pulse
 Data Path Crossings
 Design Flow impact on CDC Paths
 Synthesis
 Low Power
 Physical Implementation

⚫ Design Flow and CDC Checking tools

⚫ Conclusions
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Clock in a Digital System
⚫ A clock has
 Period of repetition (linked with its frequency)
 Phase depicts rise & fall transitions
 A flop can be triggered thru any of clock edges.
 The phase of two clocks may be different,
Tp

-ve
+ve

Phase

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Domain of a clock
⚫ Logic which is
triggered by clock (or
derived clocks)
 Also known as
Synchronous system.
Domain 100Mhz

⚫ Conversely, domains
with clocks of variable
phase and frequency
are different clock
domains.
 Also known as
Asynchronous.
Domain 27Mhz

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6
 Why have multiple clock domains?
⚫ SoC have multiple interfaces with very different clock
frequencies.

Synchronous clocks
but considered Async.

To reduce Clocktree
Balancing
complexities.
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Clock
⚫ Use one edge of the clock in the whole design.
⚫ Avoid combination logic on the clock path.
⚫ Avoid convergence and divergence in the clock path clock
must be last element if there are convergence.
⚫ Only use specially designed module in the clock path. e.g. Mux
in the clock path must be glitch free mux.
⚫ Keep clock generation or reset generation in one module in
whole design.

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Precautions when Crossing a domain

⚫ Domain crossing can be seen in real life:

 Crossing countries
 Train changing tracks
 Etc…
⚫ Needs special agents to make it error free & safe.
⚫ For the same reason, precaution is needed when
signals cross over domains.

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9
 The CDC Path
⚫ When clocks are asynchronous, the signals that interface
between are called clock domain paths.
Asynchronous Path,
No SETUP/HOLD Checks

SETUP/
SETUP/ HOLD
HOLD

C1 C2

⚫ Within each domain, setup & hold time checks ensure proper
functioning of the design.
⚫ No timing check exists on CDC Paths.

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Meta-stability
⚫ A flip-flop needs input to be stable before and after the clock edge. (Setup &
Hold Time) .

⚫ In CDC crossing, there will be setup & hold violations.

⚫ Then, the output of flip-flop may take much longer time to reach a valid logic
level. This is called metastability.

Very
close

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11
MTBF - Mean Time Between Failure
⚫ Reciprocal of failure rate: Should be as high as possible
⚫ Failure means signal goes metastable after first stage synchronizer and
continues to be metastable one cycle later when it is sampled in the
second stage synchronizer flop.

Duration of
Techno dependent metastable output
(1/Tau)

data changing
Synchronizing frequency
clock frequency

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12
Example on how to calculate MTBF
⚫ MTBF (Mean Time Between Failures): Average time a system
will run between failures.
⚫ A system has 4000 components with a failure rate of
0.02% per 1000 hours. Calculate MTBF.

⚫ No of failure per hour=

 (Failure rate) * (Number of components)
 (0.02 / 100) * (1 / 1000) * 4000 = 8 * 10-4 per hours

⚫ MTBF = 1 / (8 * 10-4 ) = 1250 hours

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13
Why is it important?
⚫ Multiple cases of Chip Failure due to this effect across the
world
 Convergence of Signals leading to control FSM moving to
unwanted state.

Leads to Chip Failure, No Software fix!!

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Clock crossing: Minimum Solution
⚫ A synchronizer is a device that samples the asynchronous
signal and output a signal that is synchronized to a destination
clock domain.
Asynchronous signal synchronizer
AW AS
AW
C1

Clk
Synchronized signal

Clk

AW

AS

Synchronizing cell should come from special cell library.

Assignment:
How to calculate number of Synchronizer flop for given frequency.
NEED TO FOLLOW MORE RULES

synchronizer

AW
C1

C2

Design has Synchronizer But..

Having a Synchronizer is not enough, One needs to follow more rules!

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 No combinational Logic at Crossing point

⚫ Unconstrained path has delay imbalance, will lead to glitches

in the path.

DA1

CLK A DB1 DB2

AW

DA2
CLK C CLK B

Make sure that CDC signal is directly coming from a flop.

Reference: Cadence Technical paper, http://www.fpga-faq.com/FAQ_Pages/cdc_wp.pdf

Re-Convergence of Synchronized Signals
DA1 DB1
AW
CLK A
Can also
Lead to
CLK B
Bad FSM
triggering
DA2 DB2
AW
CLK A

CLK B

Actual

Chip Killer
!!

Compute the controls & then do one transfer across domain

Reference: Cadence Technical paper, http://www.fpga-faq.com/FAQ_Pages/cdc_wp.pdf
Divergence in Cross over path
⚫ Divergence in Cross over path

IP1

C1

C2

IP2

C2

Avoid having multiple Synchronizer for one control signal.

Crossing Fast to Slow
Data Hold problem (Signal crosses from a fast clock domain to a slow clock domain)

To avoid CDC issues, Hold the data till a time-out (using Pulse extenders).

Q1 D1

Clk1
Clk1
Counter ==N clk2

Hold data (for minimum 3 RX clock edge) till the

transfer takes place (Traffic police).
Passing a Pulse from One domain to
Another Domain

Pulse to Toggle Toggle to Pulse

Synchronizer

C1
C1

C2

Assignment:
How to successfully pass a signal from faster clock frequency to
slower clock frequency.
Data Path: Multi bit transfer
⚫ Enable Based Synchronizer

EN
C1

C1

C2

⚫ Recirculation Mux Synchronizer

C1

C1

C2
Data Path: Asynchronous FIFO

Use Gray encoding for read & Write Pointer.

Assignment:
Design a non power of 2 depth FIFO, having even depth with
use of gray encoding pointer. E.g. FIFO with depth 12.
Data Path: Recommendations

Have glitch free mux in the data path from special cell library.

Avoid combo logic on data path.

C1

C1

C2

Have Synchronizer from special cell library

Avoid combo logic on control path.

 Synthesis Impact on CDC Paths
⚫ Glitch Free Mux

C1

C1

C2

RTL NETLIST

⚫ Clock gating
NETLIST

C1 C1

C2 C2

RTL NETLIST
 Synthesis Impact on CDC Path
⚫ Register Replication

C1 C2

C2
C1

RTL

C2
⚫ Logic Restructuring
NETLIST

C1

C1

C2
C2

C1
RTL NETLIST
Low Power Design Example
PD1: 1.0V, Always On PD2: 0.8 V, Always On
Level Shifter

RAM
Core
Processor
PMB

Isolation Isolation
Isolation_enable

PD3: 1.0 V, OFF PD4: 1.0 V, OFF

Low Power Impact on CDC path
⚫ Isolation affecting synchronizer

Synchronizer Synchronizer
Isolation Cell

C1 C1

C2 C2
iso_enable

RTL NETLIST
C1
Solution
⚫ Have better control during synthesis on CDC Path.
⚫ One way is to have a CDC Design Library
 Instantiate the RTL in the Design
 Having equivalent functionality in netlist cell.
⚫ Based upon CDC paths understanding, generate constraints
for better design optimization/Physical implementation.
 Physical Implementation Impact
⚫ Huge delay in between Sync flops Delay between Sync Flops

C1 C1

C2 C2

Logical View Unconstrained Physical Implementation

Hard Macro from Special Clock Library

C1

C2

Logical View

Reference: https://www.slideshare.net/rameraja/4-u-5-slides-with-notes-8425918
Skewed data path
⚫ Data path is severely skewed due to No
constraints & also due to Physical constraints
Huge delay
imbalance
100 ns

1ns Not Checked

In flow

Capture Period : 5 ns

Need to constrain data bus even though

Use transfer is
set_max_Delay on
constraints.
an Asynchronous interface, using set max delay.
Design Flow and CDC Checking tools
⚫ CDC analysis should be done at System Specification
RTL, also at netlist level.
Architecture Design
⚫ Reuse the RTL level constraints
during netlist CDC analysis.
RTL Design
⚫ EDA Tools for CDC analysis
 Questa CDC - Mentor Graphics Static Checks
 Meridian CDC – RealIntent
 VC SpyGlass CDC – Synopsys Synthesis
 Jasper Gold – Cadence
 CDC – Blueperalsoftware Static Checks
 ALINT-PRO – ALDEC
Physical Design

Fabrication
Conclusion
⚫ Clock Domain Crossing require special handling both at
logical and implementation time.
⚫ The cells in the CDC path must be chosen from special cell
library.
⚫ Use constraints for CDC friendly design optimization.
Link for other presentations
⚫ HDL Design using Verilog:
https://www.linkedin.com/feed/update/urn:li:activity:690110117
3491798016
⚫ HDL Design Guidelines:
 https://www.linkedin.com/feed/update/urn:li:activity:6903289386
536968192
⚫ VLSI Design Flows and Open source tools:
 https://www.linkedin.com/feed/update/urn:li:activity:6886886690
405924864
⚫ https://www.sites.google.com/view/learnvlsi/webinar
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