ETEN 3002 Note 7: Differential

Amplifiers, Rev. 2

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References:
[1] Sedra and Smith, Microelectronic Circuits, Int’l 7th Ed. , Oxford University
Press, 2016, Ch. 8
[2] Sedra and Smith, Microelectronic Circuits, 4th Ed. , Oxford University Press,
1998

Revision notes:
1. 14 Nov. 2017- Draft started by Adrian Sutinjo [AS] of School of Electrical
Engineering, Computing and Mathematical Sciences (EECMS), Curtin
University
2. 19 Sep. 2018 - Rev. 1 started by AS. Added context regarding lowering ​gm ​to
> iC2 ​above Fig. 2.
gain higher linearity (above Fig. 6). Correction ​iC1
Corrected the last sentence re. CMRR: "the higher the ​REE ​and the lower the ​
ΔRC ​, the higher the CMRR.”
3. 23 Sep. 2019 - Rev. 2 started by AS. Corrected the CMRR expression to bring
it in line with [1: Sec. 8.3.2, Eq. 8.95).

Introduction [1]
A differential amplifier amplifies the voltage difference between its input
terminals, but ignores the voltage level common to the two inputs. This is
advantageous in applications where a signal has to be transported a long
distance through a pair of wires, for example. The good information is the voltage
between the wires, but in transit the wires are subjected to noise and
interference (undesirable) that are common to both. At the receiving end, a
single-ended amplifier (such as the types we have been considering up to now)
would amplify both the signal and interference, whereas a differential amplifier
would amplify just the desired (differential) signal. That is how an ideal
differential amplifier is supposed to work. In reality, there are impairments we
must contend with and manage. Understanding how differential amplifiers are
supposed to work and the degree to which they approximate the ideal case is the
topic of our study.

BJT Differential Pair [1: 8.2], [2: 6.1]

Simple BJT Differential Pair

​Fig. 1 The basic BJT differential-pair configuration. (Figure 8.14

Microelectronic Circuits, Int'l 7th Ed. © 2016 Oxford University Press)
​
​
Fig. 1 shows a basic BJT differential pair. It consists of two matched BJTs
operating in the active region that are biased with a current source and two
matched resistors. Matched transistors and resistors are the key assumptions in
ideal differential pair analysis. In our analysis, we consider the total voltages and
currents as indicated by the uppercase subscript lowercase notation. The emitter
currents are

IS (vB1 −vE )/VT

iE1 = α
e ​

IS (vB2 −vE )/VT

iE2 = α
e ​

where we assume that ​IS ​, ​α​and ​VT ​are identical for the pair of transistors. Note
a few things here:
vB1,2 ​is the base voltage with respect to ground.
The emitter voltage, ​vE ​, is the voltage at the top of the current source which is
common to both emitters.

Taking the ratio of the emitter currents, we obtain

iE1
iE2
= e(vB1 −vB2 )/VT = evid /VT ​

where ​vid ​is the difference between the input voltages. Let’s look at that
expression for a moment. We know that ​VT ≈ 26 mV​at room temperature. We
observe the following:
When there is no input voltage difference, there the emitter (and collector)
currents are identical.
It does not take much input voltage difference (the order of a few times ​VT ​) to
cause a dramatic change in the emitter (and collector) current ratio: if ​vB1 ​is
greater than ​vB2 ​by few times ​VT ​, most of the current flows through ​Q1 ​and
little flows through ​Q2 ​.

In Fig. 1, the output voltage is taken as the difference between the collector
voltages which depends on the difference between the collector currents. This
collector current difference is the quantity we need to calculate. We can obtain
that by finding the expressions for ​iE1 ​and ​iE2 ​from the knowledge of the ratio of
the emitter currents. To do that, we begin with the current summation
relationship at the common emitter node ​E ​.

iE1 + iE2 = I ​
Note that ​I ​is a DC only (constant) quantity. We can write the following quantity

iE1 /iE1 1
​iE1
I = iE1
iE1 +iE2 = iE1 /iE1 +iE2 /iE1 = 1+iE2 /iE1 ​

which results in the expressions for the emitter currents we are after

I I
iE1 = 1+iE2 /iE1 = 1+e(vB2 −vB1 )/VT
​

I I
iE2 = 1+iE1 /iE2 = 1+e(vB1 −vB2 )/VT
​

These equations tell us that if there is no input voltage difference, the emitter
currents are exactly equal at ​I /2​. The collector currents are

αI
iC1 = 1+e(vB2 −vB1 )/VT
​

iC2 = αI
1+e(vB1 −vB2 )/VT
​

The output voltage is

vO = vC2 − vC1 = VCC − RC iC2 − VCC + RC iC1 = RC (iC1 − iC2 )​

which we can write as

vO = RC αI ( 1+e(vB21−vB1 )/VT − )​= RC αI ee(vB1 −vB2 )/VT −1

(vB1 −vB2 )/VT
1
​
1+e(vB1 −vB2 )/VT +1
= RC Iα tanh ( vB12V−vT B2 )​

We observe that for ​vB1 > vB2 ,​ ​iC1 > iC2 ​such that ​vC1 < vC2 ​and ​vO > 0​.
 ​Fig. 2 Transfer characteristics of a basic BJT differential pair. (Figure 8.16 Microelectronic
Circuits, Int'l 7th Ed. © 2016 Oxford University Press)

Fig. 2 above illustrates how we obtain differential voltage gain with a differential
pair. A small perturbation in the differential input voltage causes a large collector
current difference due to the steepness of the transfer characteristics. Note that ​
iC1,2 /I ​are the quantities in the brackets in the expression for ​vO ​above. Here ​
vid = 0.5VT ​results in collector current difference of ​0.2I ​, which results in the
differential output voltage of ​vO ≈ 0.2IRC ​.

Large-signal basic BJT pair

αI
Collector currents iC1 = 1+e(vB2 −vB1 )/VT
​

iC2 = αI
1+e(vB1 −vB2 )/VT
​
Differential output vO = vC2 − vC1 = RC (iC1 − iC2 )​
voltage

Extending the Linear Region of the BJT Differential Pair

 ​Fig. 3 The transfer characteristics of the BJT differential pair (a) can be linearized (b) (i.e., the
linear range of operation can be extended) by including resistances in the emitters. (Figure
8.17 Microelectronic Circuits, Int'l 7th Ed. © 2016 Oxford University Press)

Although the simple differential BJT pair has high gain, the gain is linear for very
small range of ​vid ​. We can extend the linear range by reducing the gain by
introducing matched emitter resistors, ​Re ​, shown in Fig. 3. Performing KVL from
the B1,2 to E, we get

vB1 − vBE1 − iE1 Re = vE ​

vB2 − vBE2 − iE2 Re = vE ​

If we assume that ​vBE1 = vBE2 ​, then after taking the difference, we get

vB1 − vB2 = vid ≈ (iE1 − iE2 )Re ​

or

vid
Re ≈ iE1 − iE2 ​

which suggests that ​Re ​scales down the influence of ​vid ​resulting in less emitter
current difference for a given differential input voltage.

MOSFET Differential Pair [1: 8.1] [2: 6.6]

 ​Fig. 4 A MOSFET differential pair (Figure 8.5 Microelectronic
Circuits, Int'l 7th Ed. © 2016 Oxford University Press)

A MOSFET differential pair consisting of two matched n-channel MOSFET is

shown in Fig. 4. Let ​kn = kn′ W /L​and the MOSFETs are operating in the
saturation region. The drain currents are

iD1 = kn
2
(vGS1 − Vt )2 ​

iD2 = kn
2
(vGS2 − Vt )2 ​

Taking the square root of each and then taking the difference, we obtain

​ ​ ​ ​
√​iD1 − √​iD2 = √​ 2 (vGS1 − vGS2 ) = √​k2n (vG1 − vG2 )​
kn

where we use ​vGS1 − vGS2 = vG1 − vG2 = vid ​as ​vS ​is common to ​Q1 ​and ​Q2 ​.
Another constraint is the sum of drain currents

iD1 + iD2 = I ​

We now have two equations and two unknowns, which may be solved to yield [1:
8.1] [2: 6.6]

​ ​
iD1 = I
2
+ vid
2
√​kn I √​1 − (vid /2)2
I/kn
​
iD2 = I
2 − vid
2
√​kn I √​1 −
(vid /2)2
I/kn ​

When there is no differential input voltage, ​vid = 0​and

iD1 = iD2 = I/2​

In addition, ​vGS1 = vGS2 = VGS ​such that

I
2 = kn
2 (VGS − Vt )2 ​

Substituting this expression, we obtain

​
+ v2id VGSI−Vt √​1 − ( VGS
2
iD1 = I
2
vid /2
−Vt
) ​

​
− v2id VGSI−Vt √​1 − ( VGS
2
iD2 = I
2
vid /2
−Vt
) ​

Switching Voltage
Now, let’s find ​vid ​at which full switching occurs, i.e., ​iD1 = I, iD2 = 0​. Using
the expression for i​ D1 ​above

​
= v2id VGSI−Vt √​1 − ( VGS )
vid /2 2
I
2 −Vt
​

​
1 = VGSvid−Vt √​1 − ( VGSid−Vt ) ​
v /2 2

The equality is fulfilled for

​
vid
VGS −Vt = √​2​

which suggests that full switching occurs for

​
∣vid ∣ = √​2(VGS − Vt )​

that is ​∼ ±40%​in excess of ​VGS − Vt = VOV ​(“overdrive” voltage). This is

depicted below in Fig. 5.
 ​Fig. 5 Normalized plots of the currents in a MOSFET differential pair. Note that
VOV is the overdrive voltage at which Q1 and Q2 operate when conducting drain
currents equal to I/2, the equilibrium situation. Note that these graphs are
universal and apply to any MOS differential pair. (Figure 8.6 Microelectronic
Circuits, Int'l 7th Ed. © 2016 Oxford University Press)
​

Small Differential Input Voltage

For small differential input, ​vid /2 << VGS − Vt ​, we may approximate these
expressions as

I vid I
iD1 ≈ 2
+ 2 VGS −Vt
​

I vid I
iD2 ≈ 2 − 2 VGS −Vt ​

Recall that ​gm = kn (VGS − Vt )​and ​ID1 = ID2 = I/2 = kn

2
(VGS − Vt )2 ​such
that

gm = I
VGS −Vt
​

which, ​vid /2 << VGS − Vt ​, results in

iD1 ≈ I
2
+ vid g2m = I
2
+ id ​

iD2 ≈ I
2
− vid g2m = I
2
− id ​

Let there be matched drain resistances, ​RD ​connected between the drains and
the voltage source ​VDD ​. The drain voltages are

vD1 = VDD − iD1 RD ≈ VDD − I2 RD − vid g2m RD ​

vD2 ≈ VDD − I2 RD + vid g2m RD ​

The differential output voltage is ​vod = vD2 − vD1 ​

vod = gm RD vid ​

and the differential voltage gain is

vod
Ad = vid
= gm RD ​

This expression and our knowledge of switching voltage suggest that we can
gain higher linearity by sacrificing gain through lowering ​gm ​. For the MOSFET
differential pair in Fig. 4, we may lower ​gm ​by increasing the overdrive voltage as
shown in Fig. 6. Note that in this context, we lower ​gm ​to achieve the same ​I ​;
this may be accomplished by lowering ​W /L​. As a result, higher ​VOV ​is needed
to attain the same ​I ​.
​Fig. 6 The linear range of operation of the MOS differential pair can be extended by operating
the transistor at a higher value of V_OV. (Figure 8.7 Microelectronic Circuits, Int'l 7th Ed. ©
2016 Oxford University Press)
​

Basic MOSFET pair

​
Switching voltage ∣vid ∣ = √​2(VGS − Vt )​
vod
Small-signal differential gain Ad = vid
= gm RD ​

Small-Signal Analysis of a BJT

Differential Pair [1: 8.2] [2: 6.2]
 ​Fig. 7 BJT pair with small-signal input. (Figure 8.18 Microelectronic Circuits, Int'l
7th Ed. © 2016 Oxford University Press)

We refer to Fig. 7 where it is assumed that the BJT pair is biased at proper DC
level. Note that whatever is connected to the bases of ​Q1 ​and ​Q2 ​are capable of
supplying DC current into the base. We start with

αI
iC1 = 1+e−vid /VT
​

αI
iC2 = 1+evid /VT
​

where ​vid = vB1 − vB2 ≪ VT ​such that ​evid /VT ≈ 1 + vid /VT ​which gives

αI αI/2 αI αI vid
iC1 ≈ 2−vid /VT = 1−vid /2VT ≈ 2 + 2 2VT ​

αI/2 αI vid
iC2 ≈ 1+vid /2VT
≈ αI
2
− 2 2VT
​

where the last approximation is due to keeping the linear term in a geometric
≈ 1 + x + x2 + ..., x < 1​). We see that for ​
series (​​1/[1 − x]
vid = 0, iC1 = iC2 = I/2​. Recall that for a BJT, ​gm = IC /VT ​which for our
context is ​gm = αI/2VT ​such that

iC1 ≈ αI
2
+ gm v2id = αI
2
+ ic ​
 αI
iC2 ≈ 2
− gm v2id = αI
2
− ic ​

which are the same as our findings for the MOSFET pair. These expressions
suggest that the differential voltage is split equally between the B-E junction of
the transistor. The total collector voltages are

αI
vC1 = VCC − iC1 RC = VCC − 2
RC − gm v2id RC ​
αI
vC2 = VCC − iC2 RC = VCC − 2
RC + gm v2id RC ​

The differential output voltage is ​vod = vC2 − vC1 ​

vod = gm vid RC ​

and the differential voltage gain is

vod
Ad = vid
= gm RC ​

Alternative View and Including the Effect of External

Emitter Resistance ​Re ​
 ​Fig. 8 BJT pair with small-signal input using the T-
model. (Figure 8.19b Microelectronic Circuits, Int'l 7th
Ed. © 2016 Oxford University Press)

Alternatively, using the T-model view of the BJT shown in Fig. 8, we can look at ​
vid /2​as the voltage dropped across the internal ​re ​of the BJT such that

vid
2
= ie re ​

or

vid
ie = 2re
​

The same small-signal emitter current ​ie ​flows across the emitter of ​Q1 ​to the
emitter of ​Q2 ​as shown in Fig. 8. This viewpoint is convenient for cases where
external emitter resistors ​Re ​are connected as we show in Fig. 3 and 9 below. In
that case, the differential input voltage would be dropped across ​re + Re ​such
that

vid
ie = 2re +2Re ​(where ​Re ​is present)
 ​Fig. 9 A differential amplifier with emitter resistances. Only signal
quantities are shown (in color).
​(Figure 8.20 Microelectronic Circuits, Int'l 7th Ed. © 2016 Oxford
University Press)

Input differential resistance

The differential input resistance is ​Rid = vid /ib ​. Using the expression for ​vid ​
above and ​ib = ie /(β + 1)​, we have

Rid = (β + 1)2(Re + re )

Differential voltage gain

The small signal collector currents are equal an opposite as shown in Fig. 9.

αvid
ic = αie = 2re +2Re
​

The differential output voltage is

αRC vid
vod = re +Re ​

The differential voltage gain is

 vod αRC RC
Ad = vid
= re +Re
≈ re +Re
​

Recall that that this is the same result as that we found for the CE amplifier with
an emitter resistance in Note 3.

Small-signal BJT pair incl. ​Re ​

vod αRC RC
Differential voltage gain Ad = vid = re +Re ≈ re +Re ​
Differential input resistance Rid = (β + 1)2(Re + re )

Common-Mode Response [1: 8.3]

Common-Mode & Differential-Mode Voltages

​Fig. 10 Differential- and common-mode (CM)

voltages.

Two voltages ​vA ​and ​vB ​in Fig. 10 may be stated in terms of a common voltage
component and a difference voltage component

vA = vCM + vD /2​
vB = vCM − vD /2​
where

vA +vB
​vCM = 2
​

​vD = vA − vB ​

We saw that ideal differential amplifiers only respond to a differential input

voltage. In this section, we study the effects that cause a differential amplifier to
produce an output voltage in response to a common mode input.

BJT Pair with Finite Current Source Resistance [1: 8.32, 2:

8.6]

​Fig. 11 (a) BJT differential pair with common-mode input and finite current source output
resistance (b) Redrawn by splitting the current source and current source resistance.

Perfectly matched components

Recall from Note 6, that the output resistance of a current source is high but
finite. We include that as ​REE ​in Fig. 11a and examine its effect on the BJT pair.
We assume that the transistors and resistors are matched. The base terminals
are subjected to a common mode voltage ​vCM ​. Because the components are
matched and the voltage input is purely common mode, they may be thought of
as two independent mirror-image circuits in Fig. 11b.
Summing the currents at the node above ​I /2​in Fig. 11b, we get

vCM −vBE
iE = 2REE
+ I2 ​

The collector voltage is

vC1 = vC2 = VCC − iC RC = VCC − αiE RC = VCC − αRC ( I2 + vCM −vBE

2REE
)​

If ​REE → ∞​, then ​vC1,2 ​remains constant in the presence of common mode
input voltage. However, with finite ​REE ​, ​vC1,2 ​changes in response to ​vCM ​.
Hence, if we take the common mode output, ​
vOCM = (vC1 + vC2 )/2 = vC1 = vC2 ​, then we have a response. However, the
differential mode output is zero because ​vC1 = vC2 ​.

Mismatch in ​RC ​
A differential response would be generated if the perfect match between the two
halves of the circuit is not maintained. For instance, let the collector resistance
connected to ​Q2 ​be ​RC + ΔRC ​. Then, ​vC1 ​would remain the same while

vC2 = VCC − α(RC + ΔRC ) ( I2 + 2REE )​

vCM −vBE

Hence,

vC2 − vC1 = −αΔRC ( I2 + 2REE )​

vCM −vBE

So, now we have both common mode and differential mode outputs due to a
common mode input voltage.

From the small-signal’s perspective, each half of the circuit in Fig. 11b is, in fact, a
CE amplifier with an emitter resistance (Note 3) such that

vc1 = αie RC = − 2RαR C

EE +re
vicm ​

vc2 = αie (RC + ΔRC ) = −α R2RC +ΔR C

EE +re
vicm ​

= ie (re + 2REE )​is the small-signal component of the input

where ​vicm
common mode voltage (​​vCM = VCM + vicm ​). The differential voltage output is
vod = vc2 − vc1 = − 2RαΔR C
EE +re
vicm ​

The ratio of the differential voltage output due to common mode (CM) voltage
input is

vod ΔRC
Acm = vicm = − 2RαΔR C
EE +re
≈ − 2REE
​

where the approximation is valid for ​α ≈ 1​and ​2REE ≫ re ​. From earlier

discussion, the differential voltage gain is

vod
Ad = vid
= gm RC ​

Therefore, the ratio ​∣Ad /Acm ∣​which we call common-mode rejection ratio is

∣ ∣ 2gm REE
CMRR = ∣ AAcmd ∣ = ΔRC /RC ​
∣ ∣

where high CMRR usually desirable. This expression suggests that the higher the
REE ​and the lower the ​ΔRC ,​ the higher the CMRR.

Common-mode gain of a BJT pair

vod ΔRC
Differential voltage out. due to CM Acm = vicm
= − 2RαΔR
EE
C
+re
≈ − 2REE
​
voltage in.
Common-mode rejection ratio
∣ ∣ 2gm REE
CMRR = ∣ AAcmd ∣ = ΔRC /RC ​
∣ ∣

DC Offset [1: 8.4]

BJT Pair Input Offset Voltage [2: 6.3]
 ​Fig. 12 (a) The BJT differential pair with both inputs grounded. Device mismatches result in a
finite dc output V_O. (b) Application of the input offset voltage V_OS ≡ V_O/A_d to the input
terminals with opposite polarity reduces V_O to zero. (Figure 8.29 Microelectronic Circuits,
Int'l 7th Ed. © 2016 Oxford University Press)
​

Fig. 12a depicts a BJT differential pair where the resistors and transistors don’t
quite match. We therefore expect that no input voltage would create some
difference in collector currents, resulting in some output voltage difference. We
consider these effects one at a time.

Difference in ​RC ​
Let there be a difference of ​ΔRC ​in the collector resistors

ΔRC
RC1 = RC + 2
​
ΔRC
RC2 = RC − 2
​

With zero input voltage, assuming matched transistors, the collector currents are
identical each of which is ​αI/2​. The DC collector voltages are

VC1 = VCC − αI
2
RC1 ​
VC2 = VCC − αI
2
RC2 ​

The output voltage is

VO = VC2 − VC1 = αI
2
(RC1 − RC2 ) = αI
2
ΔRC ​
We have a non-zero differential output voltage with zero input voltage. If a zero
differential output voltage is desired, we need a non-zero differential input
voltage of (Fig. 11b)

VO α(I/2)ΔRC
VOS = Ad = gm RC ​

Using ​gm = IC /VT = αI/2VT ​, we get

∣VOS ∣ = VT ΔR
RC
C
​

we use the absolute sign because the polarity of the input offset voltage is
usually not known ahead of time. If we use ​RC ​with ​5%​tolerance, the input
offset voltage is approximately ​±26 × 0.05 = ±1.3 mV.

Transistor mismatch
Let the scaling currents be mismatched by ​ΔIS ​

ΔIS
IS1 = IS + 2
​
ΔIS
IS2 = IS − 2
​

Note that ​VB1= VB2 = 0​and the emitter voltage is common to both ​Q1 ​and ​Q2 ​
such that ​VBE1 = VBE2 = VBE ​. The emitter currents are

IE1 = IS1 VBE /VT

α e = IS VBE /VT
αe (1 + 2IS )
ΔIS
= I
2 (1 + 2IS )​
ΔIS

IE2 = I
2 (1 − 2IS )​
ΔIS

The differential output voltage is

αI ΔIS
VO = 2 IS
RC ​

The input offset voltage is

α(I/2) ΔIS
VOS = VO
Ad
= gm IS
= VT ΔI
IS
S
​

For example, ​ΔIS /IS = 4%​results is ​VOS ≈ ±1​mV

Putting the voltage offsets together

The voltage offset due to the resistor tolerance and transistor mismatch may be
considered as independent and random effects. Therefore, the expected
cumulative offset may be calculated by taking the square root of the sum of the
squares of the contributions. For example,
​
VOS = √​VOS:ΔR
2
C
2
+ VOS:ΔIS
​

For example, from previously calculated offsets due to ​5%​​RC ​tolerance and ​4%​​
IS ​tolerance we get
​
VOS = √​1.32 + 12 = 1.64​mV

BJT Input Bias and Offset Currents [2: 6.3]

With zero input voltage, assuming matched transistors, the base currents are
equal

I/2
IB1 = IB2 = β+1
​

Let the ​β ​of ​Q1 and ​Q2 ​be mismatched by ​Δβ ​

Δβ
β1 = β + 2
​
Δβ
β2 = β − 2
​

Substituting these into the base current expressions, we get

(1 − 2β )​
Δβ
I/2 I/2 I/2
IB1 = β+Δβ/2+1 = Δβ/2 ≈ β+1
(β+1)(1+ β+1 )

IB2 = I/2
β−Δβ/2+1
≈ I/2
β+1
(1 + Δβ
2β
)​

The there is a base current difference of

I/2 Δβ
IOS = ∣IB1 − IB2 ∣ = β+1 β
​

The input bias current is defined as the average of the bias currents

IB1 +IB2 I/2

IB ≡ 2
= β+1
​
Using that expression, the input offset current is

IOS = IB Δβ
β
​

For example, for ​IB = 0.01​mA and ​β ​difference of ​20%​, ​IOS = 2 μA​. While this
number sounds small, caution is in order. Remember that whatever is connected
to the bases of the BJT differential pair must support current flow into the bases
(for npn pair or out of the bases for pnp pair). One way to do this is by connecting
shunt resistors from B1 and B2 to ground. We want to make these resistors at
least comparable to ​rπ = VT /IB ​which for ​IB = 0.01​mA would be ​∼ 2.5 kΩ​.
Hence, the small ​IOS ​would translate to input offset voltage of few micro-amps
times a few kilo-ohms which could result in a few tens of millivolts, which is
higher than the input offset voltages computed earlier.

BJT pair DC offsets

Input offset voltage due to ​ΔRC ​ VOS = VT ΔR

RC
C
​

Input offset voltage due to ​ΔIS ​ VOS = VT ΔI

IS
S
​

Input offset current due to ​Δβ ​ IOS = IB Δβ

β
​

Offset Voltage for a MOSFET Pair [2: 6.6]

 ​Fig. 13 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor
mismatches, a finite dc output voltage V_O results. (b) Application of a voltage equal to the
input offset voltage V_OS to the input terminals with opposite polarity reduces V_O to zero.
​(Figure 8.28 Microelectronic Circuits, Int'l 7th Ed. © 2016 Oxford University Press)

We can perform very similar analysis to the BJT case for the MOSFET pair with
zero input shown in Fig. 13.

RD ​mismatch
Let

ΔRD
RD1 = RD + 2
​
ΔRD
RD2 = RD − 2
​

Under zero voltage input, the G-S voltages are the same for both transistors. The
drain current through each transistor is ​I /2​. The output offset voltage is

VO = VD2 − VD1 = I2 ΔRD ​

The input offset voltage is

VO ΔRD I/2 VGS −Vt ΔRD

VOS = Ad
= gm RD
= 2 RD
​

where we have used ​gm = I

VGS −Vt
​. For example, ​5%​resistor tolerance and an
overdrive voltage of 0.2 V results in ​VOS = 5​mV.
Mismatch in (W/L)
Let the (​ W /L)​differ by ​Δ(W /L)​

(W ) =
L 1
W
L
+ 12 Δ ( W
L
)​
(W
L )2 =
W
L − 12 Δ ( W
L )​

This mismatch causes mismatch in the drain current

kn′ kn′ Δ(W /L) I Δ(W /L)

ID1 = W
2 ( L )1 (VGS − Vt )2 = I
2 + 2 2 (VGS − Vt )2 = I
2 + 2 2(W /L) ​
ID2 = I
2
− I2 Δ(W /L)
2(W /L)
​

The output offset voltage is

I Δ(W /L)
VO = 2 (W /L) RD ​

The input offset voltage is

VO I Δ(W /L) VGS −Vt Δ(W /L)

VOS = Ad
= 2 (W /L)gm
= 2 (W /L)
​

A mismatch of ​W /L​of ​2%​for 0.2 V overdrive voltage translates to 4 mV offset.

Mismatch in threshold voltage

Let

ΔVt
Vt1 = Vt + 2
​
ΔVt
Vt2 = Vt − 2
​

This mismatch causes mismatch in the drain current

kn′ W ΔVt 2
ID1 = 2 ( L ) (VGS − Vt − 2 ) ​
ΔVt /2 2
( ) ​
kn′ 2
= 2
(W
L
) (V GS − Vt ) 1 − VGS −Vt

) (VGS − Vt )2 (1 − VGS ) = I2 (1 − )​
kn′ ΔVt ΔVt
≈ 2
(W
L −Vt VGS −Vt

where the approximation assumes ​ΔVt /2 ≪ VGS − Vt ​. Similarly,

L ) (VGS − Vt ) (1 + VGS −Vt ) (1 + VGS −Vt )​

kn′ 2 ΔVt ΔVt
ID2 ≈ 2 (W = I
2
The output offset voltage

ΔVt
VO = VD2 − VD1 = −IRD VGS −Vt
​

The input offset voltage

∣VOS ∣ = ∣VO /Ad ∣ = ΔVt ​

which is a sensible result. For modern MOS technology, ​ΔVt ​could be up to a few
mV.

The total offset may be calculated by taking the square root of the sum of the
squares of the offset voltages. Unlike a BJT pair, a MOSFET pair does not suffer
from input offset current as the gate current is zero.

MOSFET pair DC offsets

VGS −Vt ΔRD

Input offset voltage due to ​ΔRD ​ VOS = 2 RD ​
VGS −Vt Δ(W /L)
Input offset voltage due to ​Δ(W /L)​ VOS = 2 (W /L) ​
Input offset current due to ​ΔVt ​ VOS = ΔVt ​