CHAITANYA Y

PROFESSIONAL SUMMARY

Vedic School Of VLSI Design

Underwent Static Timing AnalysisTraining Aug 2022 – Feb2023

 Trained in Pre layout & Post layout STA.

 Good knowledge and understanding of STA concepts.
 Hands on experience on Synopsys tools:, PRIME TIME & STAR RC.
CORE COMPETENCY

● Good knowledge and understanding of STA concepts: Fixing setup and hold violations,
understanding of timing reports, CRPR, effect of skew on timing, OCV, latch concepts
● Hands on experience on Synopsys tools:PRIMETIME & STARRC.

● Good knowledge on Unix/Linux.

● Understanding of complete ASIC design flow and Physical Design flow

● Analytical, Team building and Problem-solving.

ACADEMIC PROFILE

Qualification Institute Percentage/CGPA

B.tech QIS college of Engineering & 6.3%
Technology , Ongole
Diploma Chirala Engineering College., 72.20%
Chirala
SSC R.V.V.R.U. Public School, 5.8%
Uppugundur

ACADEMIC PROJECTS

❖ Title: Radiation hardened 9T SRAM Bit cell with optimized Speed and Power for Space Application.

● Description: The power consumption and speed of SRAMs are important issues that have
led to multiple designs to minimize power consumption during both read and write
operations. Knowing about the issues with the existing 14T SRAM cells and the failure of 6T
and 10T SRAM cells in initial testing is the motivation for this project. In this project, a 9T
static random-access memory (SRAM) cell design, that consumes less dynamic power and
has high read stability along with size optimization is proposed.
● Tools used: DSCH and Dmicrowind.
PERSONAL DETAILS

Name : Yarlagadda Gopi Krishna Chaitanya

Father’s Name : Yarlagadda Subbiaiah
Date of Birth : 22 /07/1997
Gender : Male.
Marital Status : Single
Languages Known : English, Telugu& Hindi
Permanent Address : H.NO: 14-91 Uppugundur(V),N.G Padu(M),
Prakasam (D) ,523186

DECLARATION

I do hereby confirm that the information given in this resume is true and correct to the best of my
knowledge.

Date: . Y.
Chaitanya
Place: