Electrical Power and Energy Systems 157 (2024) 109800

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International Journal of Electrical Power and Energy Systems

journal homepage: www.elsevier.com/locate/ijepes

Design and analysis of a switch fault-tolerant multi-input single-output

DC-DC converter for high reliability applications
Mudadla Dhananjaya a, Swapnajit Pattnaik b, Devendra Potnuru c, Ramesh Devarapalli d, *,
Fausto Pedro Garcia Marquez e, *
a
Department of EEE, Anil Neerukonda Institute of Technology and Science (A), Visakhapatnam, Andhra Pradesh, India
b
Dept. of Electrical Engineering, National Institute of Technology, Raipur, Chhattisgarh, India
c
Department of EEE, GVP College of Engineering for Women, Visakhapatnam, India
d
Department of Electrical/Electronics and Instrumentation Engineering, Institute of Chemical Technology, Indianoil Odisha Campus, Bhubaneswar 751013, India
e
Ingneium Researcg Group, Universidad Castilla-La Mancha, 13071 Ciudad Real, Spain

A R T I C L E I N F O A B S T R A C T

Keywords: The DC–DC converters have been used extensively in various industrial applications such as consumer elec­
Reliability tronics, aerospace, electric vehicles, and renewable energy systems. The reliability ensures that the converter
Multi-input converters continues to operate safely and efficiently despite the presence of faults. Enhancing the reliability of DC-DC
Switch fault-tolerant
converters is a challenging task, as power switches are the most fragile components that can be affected by
faults in the system. Hence, to address these challenges and ensure the safety of the converter, it is vital to
implement appropriate fast fault-diagnosis techniques and fault-tolerant strategies. Many new network topol­
ogies have been presented in literature, which lead to a shift from single input–single output to multiport
converters. These converters are suitable for integrating different energy sources. However, the majority of them
are operated using a time-sharing method, in which only one energy source is used at a time, and the others are
inactive at any specified duty cycle. Therefore, the converter and input sources are underutilized in the con­
ventional time-sharing approach. This paper proposes a new multi-input single-output (MISO) converter topol­
ogy with fully integrated switch fault tolerance. It can perform multi-input buck, boost, and buck-boost
operations. More importantly, the converter can operate uninterruptedly for single or multiple switch faults.
Using simulation and experimental results, a 400 W prototype circuit is designed to analyze the converter’s
reliability and performance.

1. Introduction
In the recent past, many multiport DC-DC converter topologies are
developed to hybridize the different types of energy sources, power
conversion in DC microgrids, and facilitate as an auxiliary power supply
in electric vehicles (EVs). These DC converters are designed with the
core objectives of fewer components, increasing the power density and
efficiency and reducing the overall cost of the power converter
compared to the several single-input DC-DC converters [1–4].
The MISO buck-boost converter was developed in [5]. However, it is
used in negative output applications. Overcoming this limitation, MISO
topologies were further developed as detailed in [6] and [7]. These
enhancements enable the converter to operate in buck, boost, and buck-
boost modes, and the system has also been extended to n-inputs. How­
ever, one input port is allowed to transfer energy to the load at a time.
The constraint mentioned in [6,7] is addressed in [8–10], enabling
sources to independently or simultaneously provide power to the load
using fewer semiconductor devices. Nevertheless, the circuit topologies
discussed in these references rely on a time-sharing scheme, which re­
stricts the efficient utilization of input sources. A systematic approach is
presented in [11,12] to develop the MISO converters using conventional
converters for the performance enhancement.

* Corresponding authors at: Ingneium Researcg Group, Universidad Castilla-La Mancha, 13071 Ciudad Real, Spain (Fausto Pedro Garcia Marquez). Department of
Electrical/Electronics and Instrumentation Engineering, Institute of Chemical Technology, Indianoil Odisha Campus, Bhubaneswar 751013, India (Ramesh
Devarapalli).
E-mail addresses: mudadladhananjaya.eee@anits.edu.in (M. Dhananjaya), swapnajit.pattnaik@gmail.com (S. Pattnaik), devendra.p@gvpcew.ac.in (D. Potnuru),
Dr.R.Devarapalli@gmail.com (R. Devarapalli), FaustoPedro.Garcia@uclm.es (F.P. Garcia Marquez).

https://doi.org/10.1016/j.ijepes.2024.109800
Received 2 May 2023; Received in revised form 13 December 2023; Accepted 15 January 2024
Available online 24 January 2024
0142-0615/© 2024 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-
nc-nd/4.0/).
M. Dhananjaya et al. International Journal of Electrical Power and Energy Systems 157 (2024) 109800

Fig. 1. Proposed MISO topology: (a) Dual-input version, (b) n-input version, (c), Dual-input switch fault-tolerant, and (d) n-input switch fault-tolerant.

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M. Dhananjaya et al.
Fig. 1. (continued).
In [13–16], various MISO configurations are presented for grid-
connected and EV applications. These topologies can enhance the
output voltage and utilization of input sources. However, it increases the
components count, leading to high costs and complexity. A new DISO
converter was developed in [17] and is specifically useful for IOT ap­
plications. This converter effectively minimizes voltage stress. A MISO
system based on Sepic and CUK topologies is presented in [18] to inte­
grate energy sources and provide lower stress. Nevertheless, the con­
verter operates by a time-sharing control with more device count. In
[19], the MISO configuration integrates two boost topologies with a
shared diode and filter capacitor. The converter achieves zero voltage
switching (ZVS) and zero current switching (ZCS) in all modes without
additional auxiliary circuits, simplifying the circuit and enhancing
efficiency.
The DISO configuration, introduced in [20] employs a switched
inductor network to enhance the output voltage and minimize voltage
ripple at the load. In [21], the MISO converter is suggested for high step-
up output voltage using voltage multiplier cells and incorporating a
current-sharing mechanism. However, the increased component count
may impact the converter’s size and complexity. In [22], an Interleaved
DC-DC converter with Boost configuration is presented, offering open
switch tolerance through the use of redundant switches for reconfigu­
ration after fault detection. An elaborate description on fault identifi­
cation and fault tolerant control of converters is suggested in [23].
Furthermore, [24] suggests a method for diagnosing and controlling
faults in m-phase interleaved DC-DC converters. This technique involves
disconnecting short-circuit faults using a controlled relay, effectively
transforming them into open-circuit issues.
It is observed that there are limitations in many of the topologies
available in the literature viz. (i) time-sharing voltage control concept is
employed, which reduces the utilization of input sources, (ii) more de­
vice count leads to bulkier and weight, and (iii) Switch fault-tolerant is
not addressed in the existing MISO converter topologies. This study
proposes a fully integrated switch Fault-Tolerant MISO (FTMISO) con­
verter and operate buck, boost and buck-boost modes of operation. The
control is simple and provides better utilization of input sources. The
important contributions of the article are as below:
• Proposed a new MISO converter circuit topology with a switch fault-
tolerance
• The converter can be operated in simple control and avoiding time-
sharing control
• Continuity of power supply for load is assured even for multiple
switch faults
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International Journal of Electrical Power and Energy Systems 157 (2024) 109800
• The output voltage magnitude is preserved in all buck, buck-boost,
and boost modes of operation even after the switch fault.
• Significantly less control complexity and comparatively lesser num­
ber of components involved.
The following are the remaining portions of the article: The sug­
gested MISO operation is detailed in Section II. Section III discusses
small-signal modelling. Section IV covers parameter design, power loss
estimates, performance comparison, reliability, and fault-diagnostic
technique. Section V details the simulation and experiment, as well as
the outcomes. In Section VI, the main points are summarized.
2. Operation of the proposed MISO configuration
The circuit of the proposed FTMISO converter is depicted in Fig. 1(a),
and it can be extended to N-inputs as shown in Fig. 1(b). It has three
switches (S1-S3), diodes (D1-D3), energy storage elements (L1, L2, and C),
V1, V2 are input DC supplies, and the output voltage is V0. In the n-input
version, the proposed configuration requires few switches, diodes, ca­
pacitors and inductors, respectively, viz. NSwitch = n + 1, Ndiodes = 3,
Capacitor = 1, and, NInductor = n. In this topology, multi-input, buck, buck-
boost, and boost modes of operation are possible without using time-
sharing control. In time-sharing control, only one dc source provide
energy to load in a particular duty cycle, and other sources are waiting
during that interval, which causes the underutilization of input sources.
In the proposed topology, the control of the converter is such that a
simultaneous supply of power to load is possible. The most important
feature of this topology is that it has a fully integrated switch fault
tolerance and continues the operation of the load uninterruptedly, even
for the failure of one main power switch or multiple numbers of
switches, as illustrated in Fig. 1(c) and (d). More precisely, with the open
circuit switch fault on any main power switch, if single or multiple
switches of S1-S3, the MISO converter operation is assured with the
magnitude of pre-fault voltage. The proposed configuration is useful in
multi-input voltage sources and enabling continuous power supply even
for switch faults. The advantages of the developed converter:
(a) Requires a lesser number of components
(b) Possible to extend for N-inputs
(c) Operate at the buck, boost, and buck-boost modes
(d) Switch fault-tolerant capability in any mode of operation
M. Dhananjaya et al. International Journal of Electrical Power and Energy Systems 157 (2024) 109800

Fig. 2. Equivalent circuits in: (a) mode 1, (b) mode 2.

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Fig. 3. The current path in a switch fault condition: (a) mode 1, (b) mode 2.

Table 1 Table 2
Output voltage and switching combinations in different configurations in Redundant switching combinations in different configurations in Switch Fault
Healthy Case. Case.
Operating Switching Switching Output Voltage Faulty Boost mode of Buck-Boost mode of Buck mode of
modes mode 1 mode 2 device operation operation operation

Buck D1, D2, S3 D1, D2, D3 V0 = V2 (1 − D) + (V1 + V2 )D Mode Mode 2 Mode Mode 2 Mode 1 Mode 2
Boost S1, S2 D1, D2, S3 V0 = (V1 + V2 )/(1 − D) 1 1
Buck-Boost S1, S2 D1, D2, D3 V0 = [V2 (1 − D) + (V1 + V2 )D]/
S1 S5, D1 S3, D1, S5, D1 D1, D2, S3, D1, D1, D2,
(1 − D)
D2 D3 D2 D3
S2 S5, D1 S3, D1, S5, D1 D1, D2, S3, D1, D1, D2,
D2 D3 D2 D3
2.1. Operating modes S3 S1, S2 S4, D1, S1, S2 D1, D2, S4, D1, D1, D2,
D2 D3 D2 D3
A. MISO boost operation S1, S2 S5, D1 S3, D1, S5, D1 D1, D2, S3, D1, D1, D2,
Mode 1: D2 D3 D2 D3
S1, S3 S5, D1 S4, D1, S5, D1 D1, D2, S4, D1, D1, D2,
In this mode, L1 and L2 are magnetized by input sources (V1, V2)
D2 D3 D2 D3
through S1 and S2, respectively. The C discharges the energy to the load S2, S3 S5, D1 S4, D1, S5, D1 D1, D2, S4, D1, D1, D2,
(R), as shown in Fig. 2(a). D2 D3 D2 D3
Mode 2: S1, S2, S3 S5, D1 S4, D1, S5, D1 D1, D2, S4, D1, D1, D2,
D2 D3 D2 D3
In this mode, S1, S2, S4 and S5 are turned OFF, and D3 is reverse
biased. Voltage sources (V1, V2) and the inductor (L1, L2) deliver energy
to the C and R through the switch S3, diode D1 and D2. The current flow
path is shown in Fig. 2(b).

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M. Dhananjaya et al. International Journal of Electrical Power and Energy Systems 157 (2024) 109800

Bode Diagram
100

Magnitude (dB)
50

-50 System: p
Phase Margin (deg): 66.4
Delay Margin (sec): 0.493
-100
-90 At frequency (rad/s): 2.35
Closed loop stable? Yes
Phase (deg)

-180 -2 -1 0 1 2 3
10 10 10 10 10 10
Frequency (rad/s)
Fig. 4. Bode plot.

The current path in this mode is shown in Fig. 3(b). Inductors L1 and
Table 3 L2 deliver energy to the C and R through the switch S3 and diode D1 and
Component specifications.
D2.
Parameter Simulation Experimental The output voltage expression of the proposed boost mode is in Eq.
Input voltages (V1, V2) 55 V, 25 V 55 V, 25 V (1).
Output voltage (V0) 160 V 160 V
Load current (I0) 2.5 A 2.5 A (V1 + V2 )
V0 = (1)
Switching frequency (f) 30 kHz 30 kHz (1 − D)
Inductor (L1, L2) 0.9mH, 0.7 mH 1 mH, 0.6mH
Capacitor(CV, C) 180 µF 220 µF where, D = duty cycle.
Load (R) 65 O 65 O
The details of the control of switches and respective output voltage
equations are given in Table 1 in case of switches are healthy. Similarly,
B. Switch fault-tolerant operation the switching operation in the switch fault case is shown in Table 2 for
In this case, the switch fault is initiated on S1 and S2 during the different modes of operation.
operation. The switch fault tolerance operation of the converter with
this open switch fault.
Mode 1: 2.2. Stresses analysis
In this mode, switch S5 is turned ON. Inductor L1 and L2 are
magnetized by the source ports V1 and V2, as shown in Fig. 3(a). Voltage and current stress analyses are crucial for selecting suitable
Mode 2: devices for the proposed converters, such as active switches. These an­
alyses help determine the appropriate voltage and current levels the

Table 4
Comparison of components and modes of operation.
Ref. Ninput Noutput NS, L C Total Voltage N-input Gain Modes of operation Switch fault-
D components stress Extension tolerant feature
VSmax

9 2 1 8 2 1 11 VS = V0 Yes V[2d2 (1 − k) + k(1 + dm ) ] Boost –

V0 =
(1 − dm )
10 2 1 6 1 1 8 VS = V0 – E1 D1 + E2 D2 Buck, Boost, and Buck- –
V0 =
(1 − D1 − D2 ) Boost
12 2 1 9 1 1 11 VS = V0 + Yes D1 V1 Buck, Boost, and Buck- –
V0 = V1 + +
Vi (1 − D1 + D2 − D12 ) Boost
D2 V2
(1 − D1 + D2 − D12 )
16 2 1 5 2 4 11 VS = Vi – E1 E2 Buck and Boost –
V0 = +
(1 − d1 ) (1 − d2 )
17 2 1 7 1 2 10 VS = V0 + – VPV (2 − D1 − D3 )D1 + Vb D3 Boost –
V0 =
Vi (1 − D1 )
20 2 1 8 3 3 14 VS = V0 Yes (VC1 + VPV )(1 + D) Boost –
V0 =
(1 − D)
Pro. 2 1 8 2 1 11 VS = V0 Yes V0,BU = V2 (1 − D) + (V1 + V2 )D Buck, Boost, Buck-Boost, Yes
V0,BO = (V1 + V2 )/(1 − D) and Switch-fault tolerant

[V2 (1 − D) + (V1 + V2 )D]

V0,BB =
(1 − D)

Ninput = Number of inputs, Noutput = Number of outputs, NS, D = Number of switches and diodes, L = Inductors, C = Capacitors, VSma = Maximum voltage stress of the
switch.

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M. Dhananjaya et al. International Journal of Electrical Power and Energy Systems 157 (2024) 109800

Table 5
List of the parameters and values. v 0 (s) = Gvd ̂
̂ d(s) (11)
Parameter Value ⎡ [ ] ⎤
V1 L2 − V2 L1
λb (switch) 0.012 s(1 − D)
v 0 (s) ⎢
̂ L1 ⎥
Ta 25 ◦ C =⎢ ⎥
⎣s(1 − D)2 C + s2 (L1 +L2 ) + s3 C(L + L ) ⎦ (12)
̂
d(s)
ϴJA 5 ◦ C/W R 1 2

λb (diode) 0.0038
T 50 ◦ C
λb (Capacitor C = 220 uF) 0.0004 From eq. (12), the bode plot is shown in Fig. 4, and the gain margin and
Ea 0.35 phase margin are infinite dB, and 69◦ respectively.
πSR 1
λb (Inductor L = 5 mH) 0.000030
A 7 4. Parameter design, power loss calculations, comparative
assessment, Reliability, and Fault-Diagnostic methodology

devices must withstand, ensuring their proper operation and reliability. 4.1. Parameter design
Semiconductor stress calculations are presented in boost operation in
healthy cases. The current stress and voltage stress are in Eqs. (2)–(4), To design a new converter, the calculation of parameters values plays
respectively. a significant role. Hence, in this section, description of design of con­
Voltage stress: verter parameters is presented using the equations given in (13)-(16) as
VS1 = VS2 = VS3 = VS4 = VS5 = V0 (2) per the guidelines presented in [26]. The designed parameters and
specifications of the proposed system, including simulation and hard­
VS1, VS2, VS3, VS4, VS5 are voltage across the switch respectively ware, are presented in Table 3.
Current stress: Step 1: Design Power Rating
Mode 1: Pomax = Vo × Iomax , Pomin = Vo × Iomin (13)
iS1 = iL1 , iS2 = iL2 (3)
Step 2: Deciding load value
Mode 2: Vo Vo
RLmin = , RLmax = (14)
iS1 = iS2 = 0, iS3 = iL1 = iL2 (4) Iomax Iomin

iS1, iS2, and iS3 are current flow through the switch, respectively Step 3: Voltage conversion ratio is calculated in (15)
Vo Vo
MV,DCmax = , MV,DCmin = (15)
3. Small signal analysis VDCmin VDCmax

The proposed converter’s transfer function is developed from a small Step 4: The duty cycle is calculated as in (16)
signal analysis [25]. The mathematical modelling in state-space form is MV,DCmax MV,DCmin
given below for the designed converter form (5)-(12) dmin = , dmax = (16)
η η
Ẋ(t) = Bx(t) + Cu(t) (5)
Step 5: Inductance calculation is
y(t) = Dx(t) + Eu(t) (6) 2 RLmax
L1min = L2min = (17)
27 fs
where, diagonal matrix = A, state vector = X(t), output vector = y(t) and
B, C, D and E are system matrices with appropriate sizes. Step 6: Current ripple through inductor
Where the converter average model is in (15)-(17),
Dmin (1 − Dmin )V0
⎡
i (t)
⎤ ⎡
iL1 (t)
⎤ ΔiL1 max = ΔiL2 max = (18)
d ⎣ L1 ⎦ fs L
iL2 (t) = B⎣ iL2 (t) ⎦ + Cu(t) (7)
dt
vc (t) vc (t) Step 7: Capacitance calculation is
⎡ ⎤ Dmax V0
0 0
− (1 − D) Cmin = (19)
⎢ (L2 + L1 ) ⎥ Vcpp RLmax fs
⎢ ⎥
⎢ ⎥
⎢ − (1 − D) ⎥
B=⎢ 0 0 ⎥ (8) V0 = Output voltage, fs = Switching frequency, Dmax = Max. duty ratio,
⎢ (L2 + L1 ) ⎥
⎢
⎢
⎥
⎥ Vcpp = Peak-to-peak capacitor voltage, and RLmax = Max. load resistance
⎣ (1 − D) − 1 ⎦ and ‘η’ is the efficiency of the converter.
0
C RC Vr
⎡ ⎤ Vcpp = (20)
2
V1 D (1 − D)(V1 + V2 )
⎢ L + ⎥
⎢ 1 (L1 + L2 ) ⎥ The ripple voltage (Vr) is 1 % V0
⎢ ⎥
⎢
C = ⎢ V2 D (1 − D)(V1 + V2 ) ⎥
⎥ (9)
⎢ L + (L1 + L2 ) ⎥ 4.2. Power loss calculations
⎣ 2 ⎦
0
The power loss analysis is an important aspect in optimizing the
D = [0 0 1] (10) design of the power converter. It is also required to determine the effi­
ciency of the converter which inturn determines the power density of the
The proposed configuration control transfer function is as follows converter. The power loss analysis is described for the proposed con­
verter as below.

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Fig. 5. Flow chat for switch fault detection and control.

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400 5.5 5.5

V0 (V)

i (A)

i (A)
200 5 5

L1

L2
0 4.5 4.5
0 1 2 1 1.0001 1.0002 1 1.0001 1.0002
Time (s) Time (s) Time (s)
(a) (b) (c)
Fig. 6. Simulation results at (V1 = 55 V; V2 = 25 V): (a) V0, (b) iL 1 , and (c). iL 2

Fig. 7. Simulation results at (V1 = 25 V; V2 = 45 V): (a) V0, (b) iL 1 , and (c).iL 2

Fig. 9. Simulation results during multiple switch faults at (V1 = 55 V; V2 =

25 V).
Fig. 8. Simulation results during switch fault at (V1 = 55 V; V2 = 25 V).

Total converter power losses and efficiency are as in Eqs. (21)–(24) P out
η= (24)
and as given in [27] Pout + Psw + Pcon
Ploss IGBT = Pcon + Psw (21) where, Pout is the output power

The conduction losses can be evaluated as

∫ 4.3. Comparative assessment
1 T
Pcon = (Ron iF + VFo )iF dt (22)
T 0
An assessment of the proposed converter’s performance is provided
in this section. Table 4 compares the proposed converter and different
The switching loss is calculated as
Multi-Input Single-Output (MISO) topologies based on various factors,
Psw = (EOFF,j + EON,j ) × f (23) including output voltage and extension for N-inputs. It becomes
apparent that each topology has its own advantages, and no single to­
The proposed converter efficiency is given in eq. (24) pology is superior in all aspects. However, the proposed converter stands
out as it can perform buck, boost, and buck-boost with fewer

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λswitch = πQ πE λb π T πA (27)

where, πQ = quality factor, π A = application factor, λb = base failure

rate, πT = temperature factor, and environmental factor π E.
[ ( )]
1 1
πT = exp − 1925 − (28)
(273 + TJ ) 298

TJ = junction temperature, and TJ in switch failure rate is

TJ = Psw (θJA ) + Ta (29)

Psw = Switching losses, θJA = ambient resistance and Ta = ambient

temperature
The diode failure rate is
Fig. 10. Reliability of the proposed converter. λdiode = πQ π s π T πE πc λb (30)

πS = electrical stress factor, πC = contact construction factor

The temperature factor ’πT’ in the diode failure rate is
[ ( )]
1 1
πT = exp 2100 − (31)
298 (TJ + 273)

TJ in diode failure rate is as follows

TJ = Ta + (θJA )Pdiode (32)

Pdiode = Diode losses

The inductor failure is obtained as
λinductor = πE λb π T πQ (33)

The temperature factor ’π T’ in inductor failure rate is

[( ) ]
1 1 − 0.11
πT = exp − + (34)
298 (THS + 273) 8.67 × 10− 5

hot spot temperature = THS

THS = 1.11(ΔT) + TA (35)

ΔT = Ambient temperature and TA = ambient operating temperature in

◦
C
where
Fig. 11. Experimental output voltage and inductor currents: (a) V0, (b) iL 1 ,
and (c).iL 2 125WL
ΔT = (36)
A

WL = inductor power loss, and A = radiating surface area

components and a switch fault tolerance feature. The failure rate of the capacitor can be calculated as

4.4. Reliability calculations λcapacitor = πV λb πQ πC π SR π T πE (37)

series resistance factor = πSR,voltage stress factor = πV, capacitance

The reliability calculations are presented in this section based on the
factor = πC
MILHDBK-217F [28]. It is used to estimate the system failures and repair
costs for the proposed converter. The details of the parameter are pre­ ( )17
S
sented in Table 5. πV = +1 (38)
0.6
The reliability is calculated using Eqs. (25)–(40).
S = ratio of the operating voltage to the rated voltage
Rs (t) = e(− λsystem ×t)
(25)
The temperature factor ’πT’ in capacitor failure rate is
System failure rate = λsystem and Rs(t) = probability function without [
− Ea
(
1 1
)]
failure for ’t duration. πT = exp − 5
− (39)
8.67 × 10 (T + 273) 298
The system mean time to failure (MTTF) is done using (26)
Ea = 0.11
∫¥
1 The system failure rate is
MTTF = Rs (t)dt = (26)
λsystem
0 λsystem = λswitch + λdiode + λinductor + λcapacitor (40)

The switch failure rate is as follows

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Fig. 12. Experimental output voltage and inductor currents: (a) V0, (b) iL 1 , and (c).iL 2

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Fig. 13. Experimental voltage and current waveforms of switches (S1-S3 and D1): (a) S1, (b) S2, (c) S3, and (d) D1.

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M. Dhananjaya et al.
Fig. 14. Experimental output voltage switch fault case: (a) Single switch failure
and (b) Multiple switch failure.
4.5. Fault-diagnostic methodology
The fault identification and control algorithm for the converter is
shown in Fig. 5, which takes values of is1, is2 and is3 into account to
estimate system condition. The fault will be detected if any of the values
is zero while the circuit is operating. An open circuit switch fault is
indicated when current through the switch is zero. The fault signals are
denoted as F1, F2 and F3 for switches S1, S2 and S3, respectively. The
remaining two switches S4 and S5 are redundant or auxellary switches.
The control of the switches is based on circuit conditions.
5. Simulation and experimental results
5.1. Simulation verification
The MATLAB/Simulink model of the converter is developed for the
parameters displayed in Table 3 for 400 W, and then it is also tested with
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International Journal of Electrical Power and Energy Systems 157 (2024) 109800
the hardware prototype for better validation of the designed converter
by following the design steps given in the previous section. In the
simulation study, many examinations have been performed by consid­
ering different input voltages and switch fault case. The following have
been considered during the validation.
Case (1): Healthy Case.
In this case, it is assumed that all are ideal with the availability of two
input voltage sources (V1 = 55 V, V2 = 25 V). The proposed converter is
tested with different input voltages, duty ratio (D = 50 %), and a
switching frequency is 30 kHz.
The corresponding simulation results of output voltage (V0),
inductor currents (iL1 and iL2 ) at (V1 = 55 V, V2 = 25 V) are shown in
Fig. 6(a-c) respectively. The proposed configuration has been accessed
in (V1 = 25 V, V2 = 45 V). In this case, Fig. 7(a), shows the output
voltage (V0) and current through the inductors L1 and L2 (iL1 and iL2 ) are
shown in Fig. 7(b)-(c) respectively. Simulated output voltages of Fig. 6
(a) and 7(a) are matched with theoretical results i.e. Eq. (1).
Furthermore, the proposed diagnostic methodology is test in boost
mode of operation is considered during healthy operation till t = 0.5 sec
and later single switch faults are created at t = 0.5, 1 and 1.5 sec for S1,
S2 and S3, respectively, as shown in Fig. 8.
Case (2): Single Switch faults.
A single switch fault is considered for S1 at t = 0.5 sec to validate the
fault tolerance. Similarly at t = 1 sec, an open circuit fault is created for
S2 and at t = 1.5sec for S3. The corresponding output voltage during
healthy and single-switch failure conditions is shown Fig. 8. It is
observed that the output voltage is preserved even during the failure of
switches.
Case (3): Multiple switch faults.
The converter operation during multiple switch faults is also vali­
dated for multiple switch faults. The respevtive output voltage is shown
in Fig. 9. Now, in this case, at t = 0.4sec considered that S1 and S2 failed.
Similarly, it is considered that S2 &S3 failed at t = 0.8 sec and S3 &S4
failed at t = 1.2 sec. Further, at t = 1.6 sec assumed that all the main
switches S1, S2 and S3 failed. It is observed that in all the cases of switch
failures, the output voltage is intact as in the healthy condition with
boost mode of operation, as shown in Fig. 9. To know the effectiveness of
the proposed converter, reliability analysis is performed during healthy
condition as well as switch fault condition based on the description
given in equations (25)-(40) and Table. V. The corresponding plot is
depicted in Fig. 10 for healthy and switch-fault conditions. It is observed
that the degree of reliability is high even under fault conditions and is
nearly the same as in healthy conditions.
5.2. Experimental verification
The experimental set-up comprises of a input supply (0–30 V, 0–10 A
HMP4030), a gate driver (A3120) circuit incorporated in a module, and
a MOSFET (TOSHIBA2SK2611) with inbuilt anti-parallel diodes and
protection. The DSP 28335 controller was utilised to build the control
logic, and digital I/O pins were employed to supply the gate pulses for
the active switches. Table 3 provides the parameter specifications for the
planned prototype. The proposed converter is tested in a healthy state at
V1 = 55 V and V2 = 25 V.
Case (1): Healthy Case.
In this case, all the switches are working well and the corresponding
load voltage (V0) is shown in Fig. 11(a) and current through the in­
ductors (iL1 and iL2 ) are shown in Fig. 11(b)-(c) respectively. The
experimental results, Fig. 11 (a)-(c) are matched with simulation results.
The proposed circuit performed the multi-input boost operation to the
load. In addition, the converter is also verified at other input voltages as
V2 > V1 (i.e. V1 = 25 V, V2 = 45 V) and the waveforms are presented in
M. Dhananjaya et al.
Fig. 15. Dynamic performance of the converter for closed loop control: (a) + 20 % increment in supply voltage and (b) − 20 % decrement in supply voltage.
Fig. 16. Dynamic performance of the converter for closed loop control: (a) + 20 % increment in load and (b) − 20 % decrement in load.
Fig. 12(a)-(c). Fig. 12(a) shows the output voltage, and Fig. 12(b)-(c)
shows the corresponding currents. The waveform of voltage stress and
the waveforms of the current stress of the switches are shown in Fig. 13
(a-d), respectively. The maximum voltage stress of the switches is equal
to the output voltage (V0).
Case (2): Single Switch faults at (V1 = 55 and V2 = 25 V).
Single switch failures and corresponding fault tolerance are also
validated experimentally. The experimental result for output voltage is
shown in Fig. 14(a) for healthy conditions till t<=0.5 sec, later S1 failed
at t = 0.5 sec, S2 failed at t = 1 sec, and S3 failed at t = 1.5 sec. It is
observed that the output voltage waveform is also similar to healthy
condition during switch fault case.
Case (3): Multiple Switch faults at (V1 = 55 and V2 = 25 V).
Fault tolerance during multiple switch faults is also validated
experimentally. The experimental result for output voltage is shown in
Fig. 14(b) for healthy conditions till t<=0.4 sec, later S1 & S2 failed at t
= 0.4 sec, S2 & S3 failed at t = 0.8 sec, S3 & S1 failed at t = 1.2 sec and all
main switches, S1,S2 & S3 failed at t = 1.6 sec. In this case, the output
voltage is also the same as the healthy condition even during multiple
switch fault conditions.
In addition, The closed loop control for the proposed converter is
validated for dynamic change in supply volatge variation as well as load
variation using PID controller as kp = 0.00157, ki = 0.029 and kd =
14
International Journal of Electrical Power and Energy Systems 157 (2024) 109800
0.00012. The sudden supply and load voltage variation are tested for ±
20% of nominal values at V1 = 25 V, V2 = 45 V and the waveforms are
presented in Figs. 15 and 16, respectively. Fig. 15(a) shows the output
voltage of the converter for sudden increment in + 20 % of nominal
valve at V1. The output voltage of the converter for sudden supply
voltage decrement in − 20 % of nominal at V1 is shown in Fig. 15(b). The
output voltage of the converter for sudden load increment in + 20 % of
nominal value of load is depicted in Fig. 16(a) and the decrement in − 20
% of nominal value of load is illustrated in Fig. 16(b). It is observed that
the controller is tracking the desired voltage levels on the converter
during dynamic conditions. The power loss distribution of the power
semiconductors and the efficiency of the proposed configuration in
boost mode in healthy conditions are shown in Fig. 17(a) and (b),
respectively. Prototype circuits are shown in Fig. 17(c).
(ii) At input voltages (V1 = 25 V; V2 = 45 V and V1 < V2).
6. Conclusion
A fully fault-tolerant multi-input, single-output DC/DC converter
structure was discussed. Simulation and experimental results explained
and supported its advantages, modes of operation, and mathematical
proofs. The proposed converter can perform multi-input buck, buck-
boost, and boost operations with reduced part count, which reduces
M. Dhananjaya et al.
Fig. 17. (a) Distribution of various power loss components in the healthy case, (b) Efficiency calculation through experimentation, and (c)Experimental setup
developed in the laboratory: (1) and (2) Input source V1, (3) Input source V2, (4) Controller(DSP 28335), (5) Desktop PC, (6) MOSFETs and driver circuit, (7) In­
ductors (L1, L2), (8) Load (R), (9) Current probe, (10) Differential voltage probe, (11) DSO.
the system’s cost and complexity. Furthermore, it enhances input energy
source utilization through the proposed structure. The converter will
continue functioning as a multi-input single-output converter in an open
circuit fault in any main power switch, maintaining the pre-fault voltage
magnitude. Reliability analysis was conducted under normal and fault
conditions, demonstrating the superiority of the proposed converter
through different scenarios and experimental validation.
CRediT authorship contribution statement
M Dhananjaya: Data curation, Funding acquisition, Methodology,
Software, Validation, Writing – original draft. Swapnajit Pattnaik:
Data curation, Funding acquisition, Project administration, Software,
Validation, Writing – review & editing. Devendra Potnuru: Data
curation, Formal analysis, Methodology, Software, Validation, Writing –
original draft. Ramesh Devarapalli: Conceptualization, Formal anal­
ysis, Methodology, Project administration, Supervision, Visualization,
Writing – review & editing. Fausto Pedro Garcia Marquez: Data
curation, Writing – original draft, Validation, Writing – review & edit­
ing, Supervision.
Declaration of competing interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
15
International Journal of Electrical Power and Energy Systems 157 (2024) 109800
Data availability
Data will be made available on request.
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