CAD for IC Design Lab

EXPERIMENT – 1
Group Members:

Gamini Siddartha (2021H1230213H)

T. Mahipal Reddy (2021H1230217H)

Title:
1. For a given group number, read the ID numbers of both the students. Assign
N = sum of the last 2 digits of ID number of the first student and n = sum of the
last 2 digits of ID number of the second student (if N or n = 0 or 1, then assign it
to 5, if there are more than 2 students in the same group, the ID number of first
2 students are to be considered).

2. For a given value of N, write down a Verilog code to find its nth power.
Given input:

ID_1 = 20211230213,

ID_2 = 20211230217

N = (1+3) = 4,

P = (1+7) = 8

Case 1: N^P = 4^8 =65536

Case 2: P^N = 8^4 = 4096

Code for N_Power without Pipeline:

module PowerN_withoutpipeline(

output reg [63:0] PowerN,PowerP,

output finished1,finished2,

input [7:0] N,P,

input clk,start

);

// reg flag=1'b0;

integer Ncount,Pcount;

wire [7:0] N1,P1;

assign finished1 = (Ncount == 0);

assign finished2 = (Pcount == 0);

assign N1=(N/10)+(N%10);

assign P1=(P/10)+(P%10);

always@(posedge clk)

begin
 if(start)

begin

PowerN=1;

PowerP=1;

Ncount=P1;

Pcount=N1;

end

/* if(N1|P1==0|N1|P1==1)

begin

end*/

if(Ncount != 0)

begin

PowerN=N1*PowerN;

Ncount=Ncount-1;

end

if (Pcount!= 0)

begin

PowerP=P1*PowerP;

Pcount=Pcount-1;

end

end

endmodule
Testbench for N_Power without Pipeline:
module PowerN_withoutpipeline_TB(

);

wire [63:0] NPowerP;

wire [31:0] PPowerN;

wire finished1,finished2;

reg [7:0] N,P;

reg clk,start;

PowerN_withoutpipeline uut(NPowerP,PPowerN,finished1,finished2,N,P,clk,start);

initial

begin

clk = 1'b0;

end

always #5 clk = ~clk;

initial

begin

start = 1'b1;

#10 start = 1'b0;

end

initial

begin

N=13;

P=17

end

initial #200 $stop;

endmodule
Simulation Waveform:

Case 1: N^P = 4^8 =65536

Case 2: P^N = 8^4 = 4096

RTL Schematic:
Code for N_Power with Pipeline:
module Power_N_With_pipeline(

output reg [63:0]powerN,powerP,

input clk,

input [7:0] N,P

);

wire [7:0]J,K;

reg [7:0] N1,N2,N3,N4,N5,N6,N7,N8,P1,P2,P3;

reg [63:0]
powerN1,powerN2,powerN3,powerN4,powerN5,powerN6,powerN7,powerP1,powerP2,powe
rP3;

assign J=(N/10)+(N%10);

assign K=(P/10)+(P%10);

always@(*)

begin
 // Pipeline stage 1

N1 <= J;

powerN1 <= J;

// Pipeline stage 2

N2 <= N1;

powerN2 <= N1*powerN1;

// Pipeline stage 3

N3 <= N2;

powerN3 <= N2*powerN2;

// Pipeline stage 4

N4 <= N3;

powerN4 <= N3*powerN3;

// Pipeline stage 5

N5 <= N4;

powerN5 <= N4*powerN4;

// Pipeline stage 6

N6 <= N5;

powerN6 <= N5*powerN5;

// Pipeline stage 7

N7 <= N6;

powerN7 <= N6*powerN6;

// Pipeline stage 8

powerN <= N7*powerN7;

////////////////////////////////////////////

// Pipeline stage 1

P1 <= K;
 powerP1 <= K;

// Pipeline stage 2

P2 <= P1;

powerP2 <= P1*powerP1;

// Pipeline stage 3

P3 <= P2;

powerP3 <= P2*powerP2;

// Pipeline stage 4

powerP <= P3*powerP3;

end

endmodule

Testbench for N_Power with Pipeline:

module Power_N_With_pipeline_TB(

);

wire [63:0] powerN,powerP;

reg clk;

reg [7:0] N,P;

Power_N_With_pipeline uut(powerN,powerP,clk,N,P);

initial

begin

clk = 1'b0;

//start = 1'b1;
 //#16 start = 1'b0;

//#96 start = 1;

// #15 start =0;

end

always #5 clk = ~clk;

initial

begin

N=13;

P=17;

end

initial #95 $stop;

endmodule

Simulation Waveform:

Case 1: N^P = 4^8 =65536

Case 2: P^N = 8^4 = 4096

RTL Schematic:

Conclusion:

Case 1: N^P = 4^8 =65536

Case 1 Non - Pipelined Pipelined

Latency 8cc 8cc

Throughput 8 bits per cc 64 bits per cc

Timing 75ns 75ns

Case 2: P^N = 8^4 = 4096

Case 1 Non - Pipelined Pipelined

Latency 4cc 4cc

Throughput 4 bits per cc 32 bits per cc

Timing 35ns 35ns

Thus, in the case of non-pipelined and pipelined throughput will be increased

and latency will remain same which is an advantage if we don’t have area as
limitation

It indicates that throughput can be improved but at the cost of area