LTC 3777

LTC3777
150V VIN and VOUT Synchronous

4-Switch Buck-Boost Controller +
Switching Bias Supply
FEATURES DESCRIPTION
nn 4-Switch Current Mode Single Inductor Architecture The LTC®3777 is a high performance buck-boost switching
Allows VIN Above, Below or Equal to VOUT regulator controller that operates from input voltages
nn Wide V Range: 4.5V to 150V above, below or equal to the output voltage. The constant
IN
nn Wide Output Voltage Range: 1.2V ≤ V
OUT ≤ 150V frequency current mode architecture allows a phase-lockable
nn Synchronous Rectification: Up to 99% Efficiency frequency of up to 600kHz, while an input/output constant
nn ±1% 1.2V Voltage Reference current loop provides support for battery charging. The
nn Input or Output Average Current Limit 150V integrated switching bias supply is a high efficiency
nn Integrated 12µA I , 150V, 85mA, Switching Bias step-down regulator that draws only 12µA typical DC supply
Q
for Optimal Thermal Performance current with a regulated output voltage at no load.
nn Programmable 6V to 10V DRV
CC Optimizes Efficiency With a wide 4.5V to 150V input and output range and
nn No Top FET Refresh Noise in Boost or Buck Mode
nn V
seamless transfers between operating regions, the
OUT Disconnected from VIN During Shutdown LTC3777 is ideal for industrial, telecom and battery-
nn Phase-Lockable Fixed Frequency (50kHz to 600kHz)
nn No Reverse Current During Start-Up
powered systems.
nn 150V Rated RUN Pin with Accurate Turn-On Threshold The LTC3777 features a power good output indicator
nn Thermally Enhanced 48-Lead e-LQFP Package and a MODE pin to select between pulse-skipping mode
or forced continuous mode of operation. The PLLIN pin
APPLICATIONS allows the IC to be synchronized to an external clock. The
nn Industrial, Transportation, Medical, Military, Avionics SS pin ramps the output voltage during start-up. Current
foldback limits MOSFET heat dissipation during short-
All registered trademarks and trademarks are the property of their respective owners.
circuit conditions.
TYPICAL APPLICATION
4mΩ VOUT
VIN
16V TO 120V 48V, 10A
30µF
20µF 56µF
1k
5Ω VINSNS BOOST1 15µH
5µF VIN 0.22µF Efficiency and Power Loss
SW1
0.1µF DRV CC
TG1 vs Input Voltage
10µF LTC3777 BG1 100 30
133k
VINOV
100Ω
1.21k SENSEP 98 24
SENSEN 4mΩ EFFICIENCY
BVIN 220pF 100Ω 475k
POWER LOSS (W)
EFFICIENCY (%)
1µF BOV SGND 96 18

PGND
BRUN
BVOUT 220µH BG2
BSW 94 12
12V BOOST2
85mA BVFB
0.22µF
715k BGND
51.1k SW2 92 6
44µF
TG2 VOUT = 48V POWER LOSS
EXTV CC IAVGSNSP IOUT = 10A
1µF 4.7µF 100Ω 90 0
10k IAVGSNSN 0 12 24 36 48 60 72 84 96 108 120
RUN 1k 100Ω VIN VOLTAGE (V)
PGOOD VOUTSNS 3777 TA01b
2.2µF 100k VFB

V5 100pF
0.1µF ITH 12.1k
SS MODE
FREQ PLLIN
56.2k 10k
10nF 3777 TA01a
Rev A
Document Feedback For more information www.analog.com 1

LTC3777
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1)
TOP VIEW
Input Supply Voltage (VIN), BVIN............... 150V to –0.3V
BOOST1
DRVSET
Topside Driver Voltage
EXTVCC
DRVCC
VINOV
SW1
BG1
TG1
VFB
BOOST1, BOOST2......................................161V to –0.3V
NC
SS
V5
48
47
46
45
44
43
42
41
40
39
38
37
Switch Voltage SW1, SW2........................... 150V to –5V
RUN, BRUN............................................... 150V to –0.3V
IAVGSNSP , IAVGSNSN.....................................150V to –10V BRUN 1
NC 2
36
35
VIN
NC
VINSNS, VOUTSNS....................................... 150V to –0.3V BSW 3 34 VINSNS
NC 4 33 NC
EXTVCC Voltage......................................... 36V to –0.3V BVIN 5 32 VOUTSNS
NC 6 49 31 NC
DRVCC Voltage.............................................11V to –0.3V BOV 7 PGND 30 IAVGSNSN
BOOST1-SW1, BOOST2-SW2.......................11V to –0.3V BFBO 8
NC 9
29
28
IAVGSNSP
NC
TG1-SW1, TG2-SW2, BG1, BG2........................... (Note 8) BGND 10 27 RUN
BISET 11 26 NC
V5, BOV, BFBO, BVFB, BISET Voltage............. 6V to –0.3V BVFB 12 25 BOOST2
MODE, PLLIN, SS, PGOOD........................... V5 to –0.3V
ITH, FREQ, DRVSET...................................... V5 to –0.3V
SENSEP 13
SENSEN 14
ITH 15
SGND 16
MODE 17
PLLIN 18
FREQ 19
PGOOD 20
BG2 21
NC 22
SW2 23
TG2 24
SENSEP, SENSEN, VINOV............................. V5 to –0.3V
VFB Voltage................................................ 2.7V to –0.3V
Operating Junction Temperature LXE PACKAGE
48-LEAD (7mm × 7mm) PLASTIC e-LQFP
Range (Notes 2, 3).................................. –40°C to 150°C TJMAX = 150°C, θJA = 36°C/W
Storage Temperature Range................... –65°C to 150°C EXPOSED PAD (PIN 49) IS PGND, MUST BE SOLDERED TO PCB
FOR RATED ELECTRICAL AND THERMAL CHARACTERISTICS
EXTVCC /DRVCC Peak Current...............................100mA
ORDER INFORMATION
LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3777ELXE#PBF LTC3777 LXE 48-Lead (7mm × 7mm) Plastic e-LQFP –40°C to 125°C
LTC3777ILXE#PBF LTC3777 LXE 48-Lead (7mm × 7mm) Plastic e-LQFP –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev A
2 For more information www.analog.com

LTC3777
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 15V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VVINOV = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Operating Voltage Range (Note 4) 4.5 150 V
VOUT Output Supply Operating Voltage Range 1.2 150 V
Regulated Feedback Voltage (Note 5); ITH Voltage = 1.4V l 1.188 1.2 1.212 V
Feedback Current (Note 5) –15 -50 nA
Reference Voltage Line Regulation (Note 5); VIN = 7V to 100V 0.02 0.2 %
Output Voltage Load Regulation (Note 5); Measured in Servo Loop; ∆ITH l 0.01 0.2 %
Voltage = 1.5V to 2V
Transconductance Amplifier gm (Note 5); ITH = 1.4V; Sink/Source 5µA 1.5 mmho
IQ Input DC Supply Current (Note 6) 3.6 5.5 mA
Shutdown RUN = 0V 40 75 µA
Undervoltage Lockout V5 Ramping Up 4.1 4.35 4.6 V
V5 Ramping Down 3.6 3.85 4.1 V
RUN Pin ON Threshold VRUN Rising 1.1 1.2 1.3 V
RUN Pin Hysteresis 100 mV
RUN Pin Source Current VRUN < 1.2V 2.5 µA
RUN Pin Hysteresis Current VRUN > 1.2V 6.5 µA
VIN Overvoltage Lockout Threshold VVINOV Rising 1.18 1.28 1.38 V
(Rising)
VIN Overvoltage Hysteresis 50 mV
SENSE Pins Current VSENSEP = VSENSEN = 0 ±2 µA
IAVGSNSP IAVGSNS Pins Current VIAVGSNSP = VIAVGSNSN = 10V 15 µA
IAVGSNSN
Soft-Start Charge Current VSS = 0V 4 5 6 µA
VSENSE(MAX) Maximum Current Sense Threshold VFB = 1V l 70 90 110 mV
(Buck Region Valley Current Mode)
Maximum Current Sense Threshold VFB = 1V l 120 140 160 mV
(Boost Region Peak Current Mode)
Maximum Input / Output Average VIAVGSNSP = VIAVGSNSN = 10V, VFB = 1V 47.5 50 52.5 mV
Current Sense Threshold
DC(MAX, BOOST) Maximum Duty Factor % Switch C On 90 %
DC(MIN, BOOST) Minimum Duty Factor for Main Switch in % Switch C On 9 %
Boost Operation
DC(MIN, BUCK) Minimum Duty Factor for Main Switch in % Switch B On 9 %
Buck Operation
Gate Driver
TG Pull-Up On Resistance VDRVCC = 6V 3.1 Ω
TG Pull-Down On Resistance 1.5
BG Pull-Up On Resistance VDRVCC = 6V 5.5 Ω
BG Pull-Down On Resistance 3
TG Transition Time: VDRVCC = 6V (Note 7)
Rise Time CLOAD = 3300pF 60 ns
Fall Time
BG Transition Time: VDRVCC = 6V (Note 7)
Rise Time CLOAD = 3300pF 60 ns
Fall Time
Rev A
For more information www.analog.com 3

LTC3777
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 15V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VVINOV = 0V unless otherwise noted.
Top Gate Off to Bottom Gate On Delay CLOAD = 3300pF Each Driver, VDRVCC = 6V 60 ns
Synchronous Switch-On Delay Time
Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF Each Driver, VDRVCC = 6V 60 ns
Top Switch-On Delay Time
DRVCC LDO Regulator
VDRVCC DRVCC Regulation Voltage from Internal VEXTVCC = 0V
VIN LDO 7V < VIN < 150V, VDRVSET = 0V 5.5 5.8 6.1 V
8V < VIN < 150V, VDRVSET = 1/4 VV5 6.5 6.8 7.1 V
9V < VIN < 150V, VDRVSET = Float 7.5 7.8 8.1 V
10V < VIN < 150V, VDRVSET = 3/4 VV5 8.45 8.8 9.15 V
11V < VIN < 150V, VDRVSET = VV5 9.15 9.5 9.85 V
DRVCC Load Regulation from VIN LDO ICC = 0mA to 50mA, VEXTVCC = 0V 0.5 2 %
VEXTVCC DRVCC Regulation Voltage from Internal 7V < VEXTVCC < 30V, VDRVSET = 0V 5.8 6.1 6.4 V
EXTVCC LDO 8V < VEXTVCC < 30V, VDRVSET = 1/4 VV5 6.8 7.1 7.4 V
9V < VEXTVCC < 30V, VDRVSET = Float 7.8 8.1 8.4 V
10V < VEXTVCC < 30V, VDRVSET = 3/4 VV5 8.75 9.1 9.45 V
11V < VEXTVCC < 30V, VDRVSET = VV5 9.65 10 10.35 V
DRVCC Load Regulation from Internal ICC = 0mA to 50mA, VEXTVCC = 12V 0.5 2 %
EXTVCC LDO VDRVSET = 0V
EXTVCC LDO Switchover Voltage EXTVCC Ramping Positive DRVCC – 0.5 V
EXTVCC Hysteresis % of DRVCC Regulation Voltage 10 %
V5 Linear Regulator
V5 Regulation Voltage 6V < VDRVCC < 10V 5.3 5.5 5.7 V
V5 Load Regulation IV5 = 0mA to 20mA, VDRVCC = 7V 0.5 1 %
Oscillator and Phase-Locked Loop
Nominal Frequency RFREQ = 68.5kΩ 225 250 275 kHz
Low Fixed Frequency RFREQ ≤ 20kΩ 30 40 50 kHz
High Fixed Frequency RFREQ = 135kΩ 450 500 550 kHz
PLLIN Input Threshold VPLLIN Rising 2 V
VPLLIN Falling 1.2 V
PLLIN Input Resistance 200 kΩ
Synchronizable Oscillator Frequency PLLIN = External Clock l 50 600 kHz
IFREQ Frequency Setting Current l 18 20 22 µA
PGOOD Output
PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
PGOOD Leakage Current VPGOOD = 5.5V ±1 µA
PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative –10 %
VFB Ramping Positive 10 %
PGOOD delay VPGOOD High to Low 125 µs
Rev A

LTC3777
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). BVIN = 12V, unless otherwise noted.
Switching Bias Supply
VBVIN Input Voltage Operating Range 4 150 V
VBVOUT Output Voltage Operating Range (Note 9) 0.8 VIN V
BUVLO BVIN Undervoltage Lockout BVIN Rising 3.5 3.8 4.15 V
BVIN Falling 3.3 3.6 3.95 V
Hysteresis 250 mV
IQB DC Supply Current (Note 6)
Active Mode 150 350 µA
Sleep Mode No Load 12 22 µA
Shutdown Mode BVRUN = 0V 1.4 6 µA
VBRUN BRUN Pin Threshold BRUN Rising 1.1 1.2 1.3 V
BRUN Falling 0.99 1.09 1.19 V
Hysteresis 110 mV
IBRUN BRUN Pin Leakage Current BRUN = 1.3V (Note 9) –10 0 10 nA
VBOV BOV Pin Threshold BOV Rising 1.1 1.2 1.3 V
BOV Falling 0.99 1.09 1.19 V
Hysteresis 110 mV
Output Supply (BVFB)
VBVFB Feedback Comparator Threshold BVFB Rising 0.786 0.800 0.814 V
VBVFBH Feedback Comparator Hysteresis BVFB Falling (Note 9) 3 5 9 mV
IBVFB Feedback Pin Current BVFB = 1V (Note 9) –10 0 10 nA
Operation
IPEAKB Peak Current Comparator Threshold BISET Floating 170 240 310 mA
BISET Shorted to GND 17 25 33 mA
ILBSWB Switch Pin Leakage Current BVIN = 150V, BSW = 0V 0.1 1 μA
tINT(SS)B Internal Soft-Start Time (Note 9) 1 ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Continuous operation above the specified absolute maximum operating
may cause permanent damage to the device. Exposure to any Absolute junction temperature may impair device reliability or permanently damage
Maximum Rating condition for extended periods may affect device the device.
reliability and lifetime. Note 4: When biased from an auxiliary supply through the EXTVCC pin, the
Note 2: The LTC3777 is tested under pulsed load conditions such that TJ LTC3777 can operate from a VIN voltage lower than 4.5V. Otherwise the
≈ TA. The LTC3777E is guaranteed to meet performance specifications minimum VIN operational voltage is 4.5V after startup.
from 0°C to 85°C junction temperature. Specifications over the –40°C Note 5: The LTC3777 is tested in a feedback loop that servos VITH to a
to 125°C operating junction temperature range are assured by design, specified voltage and measures the resultant VFB.
characterization and correlation with statistical process controls. The Note 6: Dynamic supply current is higher due to the gate charge being
LTC3777I is guaranteed over the full –40°C to 125°C operating junction delivered at the switching frequency. See Applications information.
temperature range. Note that the maximum ambient temperature Note 7: Rise and fall times are measured using 10% and 90% levels.
consistent with these specifications is determined by specific operating Delay times are measured using 50% levels.
conditions in conjunction with board layout, the rated package thermal Note 8: Do not apply a voltage or current source to these pins. They must
impedance and other environmental factors. The junction temperature TJ be connected to capacitive loads only, otherwise permanent damage may
is calculated from the ambient temperature TA and power dissipation PD occur. These pins are rated for an absolute maximum voltage of –0.3V
according to the formula: to 11V.
TJ = TA + (PD • θJA),
Note 9: Guaranteed by design and wafer level measurements.
where θJA = 36°C/W for the e-LQFP package.
Note 3: This IC includes over temperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Rev A

LTC3777
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Load Current and Input Voltage Efficiency and Power Loss
Continuous Mode vs Input Voltage
100 10 100 10
EFFICIENCY VOUT = 12V FIGURE 18 CIRCUIT
96 9 IOUT = 5A
VOUT = 48V
92 fSW = 250kHz 8 97 8
88 7
POWER LOSS (W)
POWER LOSS (W)

EFFICIENCY (%)
EFFICIENCY (%)
84 6 94 6
VIN = 72V EFFICIENCY
80 5
VIN = 48V
76 VIN = 24V 4 91 4
72 3
POWER LOSS
68 2 88 2
64 1
POWER LOSS
60 0 85 0
0.1 1 10 5 10 15 20 25 30 35 40 45 50 55
LOAD CURRENT (A) VIN VOLTAGE (V)
3777 G02
CIRCUIT OF FIGURE 19 3777 G01
Load Step Boost Region Load Step Boost Region Load Step Buck-Boost Region
Continuous Mode Pulse-Skipping Mode Continuous Mode
ILOAD ILOAD ILOAD

5A/DIV 5A/DIV 5A/DIV
IL IL
IL
5A/DIV 5A/DIV
5A/DIV
VOUT VOUT VOUT

1V/DIV 1V/DIV 1V/DIV
AC-COUPLED AC-COUPLED AC-COUPLED
3777 G03 3777 G04 3777 G05

200µs/DIV 200µs/DIV 200µs/DIV
VIN = 36V VIN = 36V VIN = 48V
VOUT = 48V VOUT = 48V VOUT = 48V
Load Step Buck-Boost Region Load Step Buck Region Load Step Buck Region
Pulse-Skipping Mode Continuous Mode Pulse-Skipping Mode
ILOAD ILOAD ILOAD

IL IL IL
VOUT VOUT VOUT

3777 G06 3777 G07 3777 G08

VIN = 48V VIN = 120V VIN = 120V
Rev A

LTC3777
Forced Continuous Mode Pulse-Skipping Mode Forced Continuous Mode
Boost Region Boost Region Buck-Boost Region
SW1 SW1 SW1

SW2 SW2 SW2
IL IL IL
VOUT VOUT VOUT
200mV/DIV 200mV/DIV 200mV/DIV
3777 G09 3777 G10 3777 G11
ILOAD = 0A ILOAD = 0A ILOAD = 0A
Pulse-Skipping Mode Forced Continuous Mode Pulse-Skipping Mode

Buck-Boost Region Buck Region Buck Region
SW1 SW1 SW1

SW2 SW2 SW2
IL IL IL
VOUT VOUT VOUT
200mV/DIV 200mV/DIV 200mV/DIV
3777 G12 3777 G13 3777 G14
VIN = 48V VIN = 120V VIN = 120V
ILOAD = 0A ILOAD = 0A ILOAD = 0A
Start-Up from RUN

Forced Continuous Mode Start-Up Forced Continuous Mode Start-Up Forced Continuous Mode
Pre-Biased Output Boost Region Buck-Boost Region
SW1
50V/DIV SW1 SW1
100V/DIV 100V/DIV
SW2 SW2 SW2
IL IL IL
5A/DIV 500mA/DIV 500mA/DIV
VOUT VOUT VOUT

3777 G15 3777 G16 3777 G17

2.5ms/DIV 5ms/DIV 5ms/DIV
VOUT PRE-BIAS = 12V 15Ω RESISTIVE LOAD 15Ω RESISTIVE LOAD
200mA LOAD
Rev A

LTC3777
Shutdown from RUN Shutdown from RUN
Start-Up Forced Continuous Mode Forced Continuous Mode Pulse-Skipping Mode
Buck Region Boost Region Boost Region
RUN RUN
5V/DIV 5V/DIV
SW1
100V/DIV SW1 SW1
100V/DIV 100V/DIV
SW2
100V/DIV SW2 SW2
100V/DIV 100V/DIV
IL IL IL
500mA/DIV 20A/DIV 20A/DIV
VOUT VOUT
VOUT 50V/DIV 50V/DIV
50V/DIV
3777 G18 3777 G19 3777 G20
5ms/DIV 200µs/DIV 200µs/DIV
15Ω RESISTIVE LOAD 5A LOAD 5A LOAD
Shutdown from RUN Shutdown from RUN

Forced Continuous Mode Forced Continuous Mode
Buck-Boost Region Buck Region Line Transient Rising Edge
RUN RUN
5V/DIV 5V/DIV
VIN
SW1 SW1 100V/DIV
100V/DIV 100V/DIV 12V to 120V
SW2 SW2 ITH

IL IL
IL
20A/DIV 1A/DIV
2A/DIV
VOUT VOUT
VOUT 500mV/DIV
50V/DIV 50V/DIV AC-COUPLED
3777 G21 3777 G22 3777 G23
200µs/DIV 200µs/DIV 1ms/DIV
VIN = 48V VIN = 120V VOUT = 48V
VOUT = 48V VOUT = 48V
NO LOAD ILOAD = 5A
Line Transient Falling Edge DRVCC vs Load Current DRVCC vs Load Current
10.5 6.5
VIN LDO, EXTVCC = 0V label2
label5
label4
label3
VIN LDO, EXTVCC = 0V
EXTVCC = 12V EXTVCC = 8.5V
VIN
100V/DIV
DRVCC VOLTAGE (V)
ITH
DRVCC VOLTAGE (V)
10.0 6.0
2V/DIV
IL
1A/DIV
VOUT
500mV/DIV 9.5 5.5
AC-COUPLED
3777 G24
1ms/DIV VIN = 12V
VOUT = 48V VIN = 12V
DRVSET = V5 DRVSET = 0V
9.0 5.0
0 20 40 60 80 100 0 20 40 60 80 100
LOAD CURRENT (mA) LOAD CURRENT (mA)
3777 G25 3777 G26
Rev A

LTC3777
VINOV Transient Forced Peak Current Threshold vs VITH
Continuous Mode Buck Region Current Foldback Limit (Boost)
200 200
CURRENT LIMIT (SENSEP – SENSEN) (mV)

SW1 BOOST
100V/DIV 150 150
SW2 100 100

100A/DIV
IL 50 50
10A/DIV
0 0
VOUT
50V/DIV
–50 –50
3777 G27
10ms/DIV –100 –100
VIN = 120V
VOUT = 48V BUCK
50Ω RESISTIVE LOAD –150 –150
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
VFB (V) VITH (V)
3777 G28 3777 G29
Valley Current Threshold vs VITH Maximum Current Limit Regulated Feedback Voltage
(Buck) vs Temperature vs Temperature
100 200 1220
150
FEEDBACK VOLTAGE (mV)

50 BOOST 1210
100
50
0 1200
0
–50
–50 BUCK 1190
–100
–100 –150 1180

0 0.2 0.4 0.6 0.8 1.1 1.3 1.5 1.7 1.9 2.1 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
VITH (V) TEMPERATURE (°C) TEMPERATURE (°C)
3777 G30 3777 G31 3777 G32
Undervoltage Lockout Threshold V5 Low Dropout Regulation

(V5) vs Temperature Voltage vs Temperature EXTVCC LDO vs Temperature
4.4 5.7 12
EXTVCC = 30V
4.3 11
RISING DRVSET = V5
4.2 5.6
10
UVLO THRESHOLD (V)
V5 LDO VOLTAGE (V)
DRVSET = 3/4 • V5
4.1
DRVCC (V)
9
4.0 5.5 DRVSET = 1/2 • V5
8
3.9 DRVSET = 1/4 • V5
7
3.8 5.4
DRVSET = GND
FALLING
3.7 6
3.6 5.3 5
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3777 G33 3777 G34 3777 G35
Rev A

LTC3777
Oscillator Frequency Frequency Setting Current
VIN LDO vs Temperature vs Temperature vs Temperature
12 800 20.5
FREQ = V5 VFREQ = 0.8V
700 20.4
11
SWITCHING FREQUENCY (kHz)

20.3
600
10 DRVSET = V5, VIN = 11V 20.2
500 RFREQ = 120k
20.1
DRVCC (V)
DRVSET = 3/4 • V5, VIN = 10V
IFREQ (µA)
9
400 20.0
8 DRVSET = 1/2 • V5, VIN = 9V
300 RFREQ = 67.5k 19.9
7 DRVSET = 1/4 • V5, VIN = 8V 19.8

200
19.7
6 DRVSET = GND, VIN = 7V RFREQ = 27.5k FREQ = GND
100
19.6
5 0 19.5
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
3777 G36 3777 G37 3777 G38
Input Supply Current Soft-Start Pull-Up Current

vs Temperature RUN Threshold vs Temperature vs Temperature
5 1.4 5.2
ON
OFF
4 1.3
SS PULL–UP CURRENT (µA)

SUPPLY CURRENT (mA)
RUN THRESHOLD (V)
5.1
3 1.2
2 1.1
5.0
1 1.0
0 0.9 4.9
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
3777 G39 3777 G40 3777 G41
Rev A

LTC3777
TYPICAL PERFORMANCE CHARACTERISTICS – SWITCHING BIAS SUPPLY
Efficiency vs Load Current, Feedback Comparator Trip BRUN and BOV Comparator
BVOUT = 12V Threshold vs Temperature Threshold vs Temperature
100 802
1.24
BRUN OR BOV THRESHOLD VOLTAGE (V)

92
1.22 RISING
BVFB THRESHOLD VOLTAGE (V)

84
801 1.20
76
EFFICIENCY (%)
1.18
68
800 1.16
60
52 1.14
44 1.12
BISET OPEN 799 FALLING
36 1.10
BVIN = 36V
28 BVIN = 72V 1.08
BVIN = 150V
20 798 1.06
0.1 1 10 100 –55 –25 5 35 65 95 125 155 –55 –25 5 35 65 95 125 155
LOAD CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C)
3777 G42 3777 G43 3777 G44
Quiescent Supply Current Quiescent Supply Current

vs Input Voltage vs Temperature Load Step Transient Response
15 30
BVIN = 150V
OUTPUT
25 VOLTAGE
SLEEP
BVIN SUPPLY CURRENT (µA)
BVIN SUPPLY CURRENT (µA)
50mV/DIV
10 20
LOAD
CURRENT
15 SLEEP 50mA/DIV
3777 G47
5 10 BVIN = 48V 200µs/DIV
BVOUT = 3.3V
1mA TO 100mA LOAD STEP
SHUTDOWN 5 FIGURE 18 CIRCUIT
SHUTDOWN
0 0
0 30 60 90 120 150 –55 –25 5 35 65 95 125 155
BVIN VOLTAGE (V) TEMPERATURE (°C)
3777 G45
3777 G46
Operating Waveforms, BVIN = 48V Operating Waveforms, BVIN = 150V Short-Circuit and Recovery
OUTPUT OUTPUT
VOLTAGE VOLTAGE
OUTPUT
50mV/DIV 100mV/DIV
VOLTAGE
SWITCH 1V/DIV
VOLTAGE
SWITCH
20V/DIV
VOLTAGE INDUCTOR
INDUCTOR 50V/DIV CURRENT
CURRENT 100mA/DIV
200mA/DIV
INDUCTOR 3777 G50
BVIN = 48V 10µs/DIV 3777 G48
CURRENT 500µs/DIV
BVOUT = 3.3V 200mA/DIV FIGURE 18 CIRCUIT
BIOUT = 100mA 3777 G49
FIGURE 18 CIRCUIT 50µs/DIV
BVIN = 150V
BVOUT = 12V
BIOUT = 50mA
Rev A

LTC3777
PIN FUNCTIONS
BRUN (Pin 1): Bias Supply Run Control Input. A voltage SENSEN (Pin 14): The negative input to the differential
on this pin above 1.21V enables normal operation. current sense comparator. This pin is normally connected
Forcing this pin below 0.7V shuts down the switching to the ground side of the sense resistor.
bias supply, reducing quiescent current to approximately
ITH (Pin 15): Error Amplifier Output. The current
1.4µA. Optionally, connect to the input supply through a
comparator trip threshold increases with the ITH control
resistor divider to set the undervoltage lockout.
voltage. The ITH pin is also used for compensating the
BSW (Pin 3): Bias Supply Switch Node Connection to control loop of the converter.
Inductor. This pin connects to the drains of the internal
SGND (Pin 16): Signal ground. All feedback and soft-start
power MOSFET switches.
connections should return to SGND. For optimum load
BVIN (Pin 5): Bias Supply Main Supply Pin. A ceramic regulation, the SGND pin should be Kelvin connected to
bypass capacitor should be tied between this pin and the PCB location between the negative terminals of the
GND. output capacitors.
BOV (Pin 7): Bias Supply Overvoltage Lockout Input. MODE (Pin 17): Mode Selection pin. Tying this pin to
Connect to the input supply through a resistor divider SGND or below 0.8V enables forced continuous mode.
to set the overvoltage lockout level. A voltage on this Tying it to V5 enables pulse-skipping mode.
pin above 1.21V disables the internal MOSFET switches.
Normal operation resumes when the voltage on this pin PLLIN (Pin 18): External Synchronization Input to Phase
decreases below 1.10V. Exceeding the OVLO lockout Detector. For external sync, apply a clock signal to this pin
threshold triggers a soft-start reset, resulting in a graceful and the internal PLL will synchronize the internal oscillator
recovery from an input supply transient. Tie this pin to to the clock. The PLL compensation network is integrated
ground if the overvoltage is not used. into the IC. When synchronized to an external clock, the
regulator can operate either in forced continuous or pulse-
BFBO (Pin 8): Bias Supply Feedback Comparator Output. skipping mode. The mode of operation is controlled by
The typical pull-up current is 20µA. The typical pull-down the setting on the MODE pin.
impedance is 70Ω. This output signal can be used to
synchronize other ICs. FREQ (Pin 19): The frequency control pin for the internal
VCO. Frequencies between 40kHz and 500kHz can be
BGND (Pin 10): Ground. programmed by using a resistor between FREQ and
BISET (Pin 11): Bias Supply Peak Current Set Input. Leave SGND. The resistor and an internal 20µA source current
floating for the maximum peak current (230mA typical) or create a voltage used by the internal oscillator to set the
short to ground for minimum peak current (25mA typical). frequency.
The maximum output current is one-half the peak current. PGOOD (Pin 20): Fault indicator Output. Open-drain
BVFB (Pin 12): Bias Supply Output Voltage Feedback. output that pulls to ground when the voltage on the VFB
Connect to an external resistive divider to divide the output pin is not within ±10% of its set point.
voltage down for comparison to the 0.8V reference.
BG1/BG2 (Pins 41 and 21): Bottom Gate Driver Outputs.
SENSEP (Pin 13): The positive input to the differential This pin drives the gate(s) of the bottom N-Channel
current comparator. This pin is normally connected to a MOSFET between PGND to DRVCC.
sense resistor at the source of the power MOSFET. The ITH
SW1, SW2 (Pins 39 and 23): Switch Node Connections
pin voltage and controlled offsets between the SENSEP
to the Inductors.
and SENSEN pins, in conjunction with RSENSE , set the
current trip threshold.
Rev A

LTC3777
PIN FUNCTIONS
TG1, TG2 (Pin 38 and 24): High Current Gate Drives threshold triggers a soft-start reset, resulting in a graceful
for Top N-Channel MOSFETs. These are the outputs of recovery from an input supply transient. Tie this pin to
floating high side drivers with a voltage swing equal to ground if the overvoltage function is not used.
DRVCC superimposed on the switch node voltage SW. DRVSET (Pin 43): Sets the regulated output voltage of the
BOOST1. BOOST2 (Pin 37 and 25): Boosted Floating DRVCC linear regulator from 6V to 10V in 1V increments.
Driver Supplies. The (+) terminal of the bootstrap Tying this pin to SGND sets DRVCC to 6V, tying it to
capacitor connects to this pin. This pin swings from a 1/4 • V5 sets DRVCC to 7V, while floating this pin sets
diode drop below DRVCC up to VIN + DRVCC. DRVCC to 8V, tying it to 3/4 •V5 sets DRVCC to 9V, and
RUN (Pin 27): Enable Control Input. A voltage above 1.2V tying it to V5 sets DRVCC to 10V.
turns on the IC. There is a 2.5µA pull-up current on this EXTVCC (Pin 44): External Power Input to an Internal
pin. Once the RUN pin rises above the 1.2V threshold the LDO Connected to DRVCC. When the voltage on this pin
pull-up current increases to 6.5µA. Forcing this pin below is greater than the DRVCC LDO setting minus 500mV, this
1.1V shuts down the controller. This pin can be tied to VIN LDO bypasses the internal LDO powered from VIN. Tie this
for always-on operation. Do not float this pin. pin to ground if the EXTVCC is not used.
IAVGSNSP (Pin 29): The positive input to the Input / Output DRVCC (Pin 45): Output of the Internal or External Low
Average Current Sense Amplifier. Dropout Regulator. The gate drivers are powered from
this voltage source. The DRVCC voltage is set by the
IAVGSNSN (Pin 30): The negative input to the Input / Output
DRVSET pin. A low ESR 4.7µF (X5R or better) ceramic
Average Current Sense Amplifier. Short IAVGSNSP and
bypass capacitor should be connected between DRVCC
IAVGSNSN pins together, and tie them to V5, if this average
and PGND, as close as possible to the IC. Do not use the
current loop function is not used.
DRVCC pin for any other purpose.
VOUTSNS (Pin 32): VOUT Sense Input to the Buck-Boost
V5 (Pin 46): Output of the Internal 5.5V Low Dropout
Transition comparator. Connect this pin to the drain of
Regulator. The control circuits are powered from this
the top N-channel MOSFET on the output side through
a 1kΩ resistor. voltage. Bypass this pin to SGND with a minimum of
2.2µF low ESR tantalum or ceramic capacitor, as close
VINSNS (Pin 34): VIN Sense Input to the Buck-Boost as possible to the IC.
Transition comparator. Connect this pin to the drain of
SS (Pin 47): Soft-Start Input. The voltage ramp rate at this
the top N-channel MOSFET on the input side.
pin sets the voltage ramp rate of the regulated voltage.
VIN (Pin 36): Main Supply Pin. A bypass capacitor should This pin has a 5μA pull-up current. A capacitor to ground
be tied between this pin and the PGND pin. at this pin sets the ramp time to final regulated output
VINOV (Pin 42): Connect to the input supply through a voltage.
resistor divider to set the over-voltage lockout level. A VFB (Pin 48): Error Amplifier Input. The FB pin should be
voltage on this pin above 1.28V disables all switching, connected through a resistive divider network to VOUT to
and the top GATE pins are held low, the bottom GATE pins set the output voltage.
are held high, and VOUT is disconnected from VIN. DRVCC
PGND (Exposed Pad Pin 49): Driver Power Ground.
and V5 regulation is maintained during an over-voltage
Connects to the (–) terminal of CIN, COUT and RSENSE.
event. Normal operation resumes when the voltage on this
The exposed pad must be soldered to PCB ground for
pin decreases below 1.23V. Exceeding the VINOV lockout
electrical contact and rated thermal performance.
Rev A

LTC3777
BLOCK DIAGRAM
DRVCC VIN
VINOV
42 + VOUT /BOOST2
CHARGE BOOST1
DA
OV CONTROL
– VIN /BOOST1 BOOST2 BOOST1 CIN
1.2V 37 CA
– FCB
TG1
FET A
SHDN 38
+ IDREV
2.5µA CCM/DCM D1
RUN
VIN + BUCK
SW1
39
27 LOGIC DRVCC
34
VINSNS SW1 – BG1
41
BUCK/BOOST FET B
TRANSITION BBT
VOUTSNS PGND
32 DETECTOR IREV 49 L1
+ RSENSE
CCM BG2
MODE MODE 21
17
SELECT DCM – FCB
200k BOOST DRVCC
SW2
VFLD LOGIC 23
FET D FET C
PLLIN TG2 D2
ICMP 24
18 PHASE DET
+ CB
200k BOOST2
25
20µA
– OV/SHDN DB
FREQ DRVCC
19 IAVGSNSP
+ 29
OSCILLATOR
A1 RSENSE2
IAVGSNSN
SLOPE – 30 VOUT
+
IOS COUT
BVIN
VIN 5 –
EA VFB R1
1
BRUN – 48
+ 1.2V SS
5µA + 47 R2
L2 BSW
VBVOUT 3
R3 ITH
BVFB LOW IQ
12 15
SWITCHING
R4 BIAS
BOV SUPPLY
7 SENSEP
13
BGND
10 SENSEN
14
BFBO
8
1.32V + PGOOD
BISET 20
11 –
DRVCC LDO VFB
VIN CONTROL –
36
1.08V +
+ +
DRVSET
– –
VIN LDO EXTVCC LDO +
–
DRVCC
45
4R
CDRVCC V5
V5
UVLO LDO
1R UVLO
16 SGND
EXTVCC DRVSET V5
44 43 46
3777 BD
CV5
Rev A

LTC3777
OPERATION
MAIN CONTROL LOOP Most of the internal circuitry is powered from the V5
rail that is generated by an internal linear regulator from
The LTC3777 is a 150V synchronous buck-boost
controller with an integrated 150V, 85mA, high efficiency DRVCC. The V5 pin needs to be bypassed with a 1µF to
10µF external capacitor between V5 and SGND. This pin
synchronous switching bias supply. The 150V switching
provides a 5.5V output that can supply up to 20mA of
bias supply draws only 12µA typical DC supply current
current. See the Applications Information section for more
while maintaining a regulated output voltage at no load.
details.
The 150V synchronous buck-boost is a current mode
controller that provides an output voltage above, equal Top MOSFET DRIVER and Internal Charge Path
to or below the input voltage. The ADI proprietary Each of the two top MOSFET drivers is biased from its
topology and control architecture employs a current- floating bootstrap capacitor, which is normally recharged
sensing resistor. The inductor current is controlled by the by DRVCC through an external diode when the top MOSFET
voltage on the ITH pin, which is the output of the error is turned off and when SW goes low. When the LTC3777
amplifier EA. The VFB pin receives the voltage feedback operates exclusively in the buck or boost regions, one
signal, which is compared to the internal reference voltage of the top MOSFETs is constantly on. An internal charge
by the EA. If the input/output current regulation loop is
path, from VOUT and BOOST2 to B00ST1 or from VIN and
implemented, the sensed inductor current is controlled
B00ST1 to B00ST2, charges the bootstrap capacitor so
by either the sensed feedback voltage or the input/output
that the top MOSFET can be kept on. However, if a high
current. leakage external diode is used such that the internal charge
path cannot provide sufficient charge to the external
DRVCC /EXTVCC / V5 Power
bootstrap capacitor, an internal UVLO comparator, which
Power for the top and bottom MOSFET drivers is derived constantly monitors the drop across the capacitor, will
from the DRVCC pin. The DRVCC supply voltage can be sense the (BOOST – SW) voltage when it is below the
programmed from 6V to 10V in 1V steps using the boost capacitor refresh threshold. This will turn off its top
DRVSET pin. The internal VIN LDO (low dropout linear MOSFET for about one-twelfth of the clock period every
regulator) can provide power from VIN to DRVCC. The four cycles to allow the bootstrap capacitor to recharge.
internal VIN LDO uses an internal P-channel pass device The boost capacitor refresh threshold varies with the
between the VIN and DRVCC pins. To prevent high on-chip DRVSET pin setting.
power dissipation in high input voltage applications, the
LTC3777 also includes an integrated 150V, low IQ 85mA Shutdown and Start-Up
synchronous step-down regulator to bias the buck-boost
The LTC3777 can be shut down by pulling the RUN pin
controller. See Integrated Switching Bias Supply in the low. Pulling RUN below 1.1V shuts down the main control
Operation section for more information. loop for the controller and most internal circuits, including
When the EXTVCC pin is tied to a voltage below its the DRVCC and V5 regulators. Releasing RUN allows an
switchover voltage (DRVCC – 500mV), the VIN LDO internal 2.5µA current to pull-up the pin and enable the
is enabled and supplies power from VIN to DRVCC. If controller. When RUN is above the accurate threshold of
EXTVCC is taken above its switchover voltage, the VIN 1.2V, the internal LDO will power up DRVCC. At the same
LDO is turned off and an EXTVCC LDO is turned on. Once time, a 6.5µA pull-up current will kick in to provide more
enabled, the EXTVCC LDO supplies power from EXTVCC RUN pin hysteresis. The RUN pin may be externally pulled
to DRVCC. Using the EXTVCC pin allows the DRVCC power up or driven directly by logic. The RUN pin can tolerate up
to be derived from a high efficiency supply such as the to 150V (absolute maximum), so it can be conveniently
low IQ integrated step-down regulator bias supply or the tied to VIN in always-on applications where the controller
LTC3777 switching regulator output if the output voltage is enabled continuously and never shut down. The RUN
is less than 36V.
Rev A

LTC3777
OPERATION
pin will have no internal pull-up current when externally VIN VOUT
driven to a voltage above 4V. TG1 A D TG2

L
SW1 SW2
Soft-Start
BG1 B C BG2
The start-up of the controller’s output voltage VOUT is
controlled by the voltage on the SS pin. When the voltage RSENSE
on the SS pin is less than the 1.2V internal reference, 3777 F01
the LTC3777 regulates the VFB voltage to the SS voltage

instead of the 1.2V reference. This allows the SS pin to Figure 1. Simplified Diagram of the Output Switches
be used to program soft-start by connecting an external
capacitor from the SS pin to SGND. An internal 5µA DCMAX
BOOST
pull-up current charges this capacitor, creating a voltage A ON, B OFF
BOOST REGION
ramp on the SS pin. As the SS voltage rises linearly from PWM C, D SWITCHES
DCMIN
0V to 1.2V (and beyond), the output voltage VOUT rises BOOST
FOUR SWITCH PWM BUCK/BOOST REGION
smoothly from zero to its final value. When RUN is pulled DCMAX
BUCK
low to disable the controller, or during an overvoltage D ON, C OFF
BUCK REGION
event on the VIN input supply or during an overtemperature DCMIN
PWM A, B SWITCHES
shutdown event, or when V5 drops below its undervoltage BUCK 3777 F02
lockout threshold of 3.85V, the SS pin is pulled low by Figure 2. Operating Region vs Duty Cycle
an internal MOSFET. When in undervoltage lockout, the
controller is disabled and the external MOSFETs are held Buck Region (VIN >> VOUT)
off.
When VIN is significantly higher than VOUT, the part will run
Certain applications can require the start-up of the in the buck region. In this region switch C is always off. At
converter into a non-zero load voltage, where residual the start of every cycle, synchronous switch B is turned on
charge is stored on the VOUT capacitor at the onset of first. Inductor current is sensed when synchronous switch
converter switching. In order to prevent the VOUT from B is turned on. After the sensed inductor valley current
discharging under these conditions, the part will be forced falls below a reference voltage, which is proportional to
into discontinuous mode of operation until the SS voltage VITH, synchronous switch B is turned off and switch A
crosses VFB or 1.32V, whichever is lower. is turned on for the remainder of the cycle. Switches A
and B will alternate, behaving like a typical synchronous
Power Switch Control buck regulator. The duty cycle of Switch A increases
Figure 1 shows a simplified diagram of how the four until the maximum duty cycle of the converter reaches
power switches are connected to the inductor, VIN, VOUT DC(MAX_BUCK), given by:
and GND. Figure 2 shows the regions of operation for ⎛ 1⎞
the LTC3777 as a function of VOUT – VIN or switch duty DC(MAX,BUCK) = ⎜ 1− ⎟ • 100% = 91.67%
⎝ 12 ⎠
cycle, DC. The power switches are properly controlled so
the transfer between regions is continuous. Hysteresis is Figure 3 shows the typical buck region waveforms. If VIN
added to prevent chattering when transitioning between approaches VOUT, the buck-boost region is reached.
regions.
Rev A

LTC3777
OPERATION
CLOCK
A and C on, the controller first operates as a boost, until
ICMP trips and switch D is turned on. At 120°, switch B is
SWITCH A
turned on, making it operate as a buck. Then, ICMP trips,
SWITCH B turning switch B off and switch A on for the remainder of
SWITCH C
LOW the clock period.
HIGH
SWITCH D
Boost Region (VIN << VOUT)
IL
3777 F03
Switch A is always on and synchronous switch B is always
Figure 3. Buck Region (VIN >> VOUT) off in the boost region. In every cycle, switch C is turned
on first. Inductor current is sensed when synchronous
Buck-Boost Region (VIN ≈ VOUT) switch C is turned on. After the sensed inductor peak
When VIN is close to VOUT, the controller enters the buck- current exceeds what the reference voltage demands,
boost region. Figure 4 shows the typical waveforms in this which is proportional to VITH, switch C is turned off and
region. At the beginning of a clock cycle, if the controller synchronous switch D is turned on for the remainder of
starts with B and D on, the controller first operates as if in the cycle. Switches C and D will alternate, behaving like a
the buck region. When ICMP trips, switch B is turned off, typical synchronous boost regulator.
and switch A is turned on. At 120° clock phase, switch C is The duty cycle of switch C decreases until the minimum
turned on. The LTC3777 starts to operate as a boost until duty cycle of the converter reaches DC(MIN,BOOST), given
ICMP trips. Then, switch D is turned on for the remainder by:
of the clock period. If the controller starts with switches
⎛ 1⎞
DC(MIN,BOOST) = ⎜ ⎟ • 100% = 8.33%
⎝ 12 ⎠
CLOCK
SWITCH A Figure 5 shows typical boost region waveforms. If VIN

SWITCH B approaches VOUT, the buck-boost region is reached.
SWITCH C
CLOCK
SWITCH D HIGH
SWITCH A
IL LOW
SWITCH B
3777 F04a
SWITCH C
(4a) Buck-Boost Region (VIN ≥ VOUT)
SWITCH D
CLOCK IL
3777 F05
SWITCH A
Figure 5. Boost Region (VIN << VOUT)
SWITCH B
SWITCH C
Light Load Current Operation (MODE Pin)
SWITCH D
The LTC3777 can be enabled to enter pulse-skipping
IL
mode or forced continuous conduction mode. To select
3777 F04b
forced continuous operation, tie the MODE pin to a DC
(4b) Buck-Boost Region (VIN ≤ VOUT) voltage below 0.8V (e.g., SGND). To select pulse-skipping
mode of operation, tie the MODE pin to V5.
Figure 4. Buck-Boost Region
Rev A

LTC3777
OPERATION
Pulse-Skipping Mode: When the LTC3777 enters pulse- it, current sunk into the input through switch A is limited
skipping or discontinuous mode, in the boost region, to approximately 40mV/ RDS(ON) of switch A. If this level
synchronous switch D is held off whenever reverse is reached, switching will stop and the output will rise. In
current through switch A is detected. At very light loads, pulse-skipping mode, and in the narrow continuous buck
the current comparator, ICMP, may remain tripped for region that adjoins the buck/ boost region, current sunk
several cycles and force switch C to stay off for the same into the input through RSENSE is limited to approximately
number of cycles (i.e., skipping pulses). In the buck 40mV/RSENSE.
region, the inductor current is not allowed to reverse.
Synchronous switch B is held off whenever reverse Voltage Regulation Loop
current on the inductor is detected. At very light loads, The LTC3777 provides a constant-voltage regulation
the current comparator, ICMP, may remain untripped for loop, for regulating the output voltage. A resistor divider
several cycles, holding switch A off for the same number between VOUT, VFB and GND senses the output voltage.
of cycles. Synchronous switch B also remains off for the As with traditional voltage regulators, when VFB rises near
skipped cycles. In the buck-boost region, the controller or above the reference voltage of EA (1.2V typical, see
operates alternatively in boost and buck regions in one Block Diagram), the ITH voltage is reduced to command
clock cycle, as in continuous operation. A small amount the amount of current that keeps VOUT regulated to the
of reverse current is allowed, to minimize ripple. For the desired voltage.
same reason, a narrow band of continuous buck and
boost operation is allowed on the high and low line ends Constant-Current Regulation (IAVGSNSP and
of the buck-boost region. IAVGSNSN Pins)
Forced Continuous Mode: The forced continuous The LTC3777 provides a constant-current regulation
mode allows the inductor current to reverse directions loop for either input or output current. A sensing resistor
without any switches being forced “off” to prevent this close to the input or output capacitor will sense the
from happening. At very light load currents the inductor input or output current. When the current exceeds the
current will swing positive and negative as the appropriate programmed current limit, the voltage on the ITH pin
average current is delivered to the output. During soft- will be pulled down to maintain the desired maximum
start, if the SS pin is lower than VFB, the part will be forced input or output current. The input current limit function
into discontinuous mode to prevent pulling current from prevents overloading the DC input source, while the
the output to the input. After SS voltage crosses VFB or output current limit provides a building block for battery
1.32V, whichever is lower, forced continuous mode will charger or LED driver applications. It can also serve as
be enabled. an extra current limit protection for a constant-voltage
regulation application. The input or output current limit
Output Overvoltage function has an operating voltage range of GND to the
If the output voltage is higher than the value commanded absolute maximum VIN or VOUT, respectively.
by the VFB resistor divider, the LTC3777 will respond
according to the mode and region of operation. In Frequency Selection and Phase-Locked Loop (FREQ
continuous conduction mode, the LTC3777 will sink and PLLIN Pins)
current into the input. If the input supply is capable of The selection of switching frequency is a trade-off
sinking current, the LTC3777 will allow up to about 80mV/ between efficiency and component size. Low frequency
RSENSE to be sunk into the input. In pulse-skipping mode operation increases efficiency by reducing MOSFET
and in the buck or boost regions, switching will stop switching losses, but requires larger inductance and/or
and the output will be allowed to remain high. In pulse- capacitance to maintain low output ripple voltage. The
skipping mode, and in the buck-boost region as well as the switching frequency of the LTC3777’s controllers can be
narrow band of continuous boost operation that adjoins selected using the FREQ pin. If the SYNC pin is not being
Rev A

LTC3777
OPERATION
driven by an external clock source, the FREQ pin can be The LTC3777 includes current foldback to help limit load
used to program the controller’s operating frequency current when the output is shorted to ground. If the output
from 50kHz to 600kHz. falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from
Switching frequency is determined by the voltage on
its maximum value to one-third of the maximum value.
the FREQ pin. Since there is a precision 20µA current
Foldback current limiting is disabled during the soft-start.
flowing out of the FREQ pin, the user can program the
Under short-circuit conditions, the LTC3777 will limit the
controller’s switching frequency with a single resistor to
current by operating as a buck with very low duty cycles,
SGND. Figure 9 in the Applications Information section
and by skipping cycles. In this situation, synchronous
shows the relationship between the FREQ pin resistor
switch B will dissipate most of the power (but less than
value and the switching frequency.
in normal operation).
A phase-locked loop (PLL) is integrated on the LTC3777
to synchronize the internal oscillator to an external clock Thermal Shutdown
source driving the PLLIN pin. While LTC3777 is being The LTC3777 has a temperature sensor integrated on
synchronized to an external clock source, depending on the IC, to sense the die temperature near the gate driver
the voltage of the MODE pin, it can be enabled to enter circuits. When the die temperature exceeds 175°C, all
pulse-skipping mode or forced continuous conduction switching actions stop, the top GATE pins are held low,
mode. The PLL filter network is integrated inside the and the bottom GATE pins are held high, and VOUT is
LTC3777. disconnected from VIN. At the same time, the SS pin is
The PLL is capable of locking to any frequency within the pulled low by an internal MOSFET. When the temperature
range of 50kHz to 600kHz. The frequency setting resistor drops 10°C below the trip threshold, the part goes through
should always be present to set the controller’s initial a SS reset cycle and normal operation resumes.
switching frequency before locking to the external clock.
Input Undervoltage and Overvoltage Lockout
Power Good (PGOOD) Pins The LTC3777 implements a protection feature that
The PGOOD pin is connected to the open drain of an inhibits switching when the input voltage rises above a
internal N-channel MOSFET. When VFB is not within ±10% programmable operating range. By using a resistor divider
of the 1.2V reference voltage, the PGOOD pin is pulled from the input supply to ground, the RUN and VINOV pins
low. The PGOOD pin is also pulled low when RUN is below serve as a precise input supply voltage monitor. Switching
1.1V or when the LTC3777 is in the soft-start phase. There is disabled when either the RUN pin falls below 1.1V or the
is an internal 125µs power good or bad mask when VFB VINOV pin rises above 1.28V, which can be configured to
goes in or out of the ±10% window. The PGOOD pin is limit switching to a specific range of input supply voltage.
allowed to be pulled up by an external resistor to V5 or When switching is disabled, the LTC3777 can safely
an external source of up to 6V. sustain input voltages on the RUN pin up to the absolute
maximum rating of 150V. Input supply undervoltage or
Short-Circuit Protection, Current Limit and Current
overvoltage events trigger a soft-start reset, which results
Limit Foldback
in a graceful recovery from an input supply transient.
The maximum current threshold of the controller is limited
by a voltage clamp on the ITH pin. In every boost cycle, Integrated Switching Bias Supply
the sensed maximum peak voltage is limited to 140mV.
The switching bias supply is a synchronous step-down
In every buck cycle, the sensed maximum valley voltage
DC/DC regulator with internal power switches that uses
is limited to 90mV. In the buck-boost region, only peak Burst Mode® control, combining low quiescent current
sensed voltage is limited by the same threshold as in the with high switching frequency, which results in high
boost region.
Rev A

LTC3777
OPERATION
efficiency across a wide range of load currents. Burst The peak current comparator has a maximum current
Mode operation functions by using short “burst” cycles limit of at least 170mA, which guarantees a maximum
to switch the inductor current through the internal power average current of 85mA. Shorting the BISET pin to ground
MOSFETs, followed by a sleep cycle where the power programs the current limit to 25mA, and leaving it floating
switches are off and the load current is supplied by the sets the current limit to the maximum value of 240mA.
output capacitor. During the sleep cycle, it draws only Input undervoltage and overvoltage lockout protection
12µA of supply current. At light loads, the burst cycles are features will inhibit switching when the input voltage
a small percentage of the total cycle time which minimizes is not within a programmable operating range. By use
the average supply current, greatly improving efficiency. of a resistive divider from the input supply to ground,
If the voltage on the BRUN pin is less than 0.7V, the the BRUN and BOV pins serve as a precise input supply
switching bias supply enters a shutdown mode in which voltage monitor. Switching is disabled when either the
all internal circuitry is disabled, reducing the DC supply BRUN pin falls below 1.1V or the BOV pin rises above
current to 1.4µA. When the voltage on the BRUN pin 1.21V, which can be configured to limit switching to a
exceeds 1.21V, normal operation of the main control specific range of input supply voltage. Furthermore, if the
loop is enabled. The BRUN pin comparator has 110mV input voltage falls below 3.5V typical (3.8V maximum), an
of internal hysteresis, and therefore must fall below 1.1V internal undervoltage detector disables switching.
to disable the main control loop. Input supply undervoltage or overvoltage events trigger a
An internal 1ms soft-start function limits the ramp rate of soft-start reset, which results in a graceful recovery from
the output voltage on start-up to prevent excessive input an input supply transient.
supply droop. The internal soft-start function is reset on
start-up and after an undervoltage or overvoltage event
on the input supply.
Rev A

LTC3777
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic LTC3777 resistance in the buck region, RSENSE(MAX,BUCK). The
application circuit. External component selection is driven selected RSENSE resistance must be smaller than both.
by the load requirement, and begins with the selection of Figure 6 shows how ILOAD(MAX) • RSENSE varies with input
RSENSE and the inductor value. Next, the power MOSFETs and output voltage.
are selected. Finally, CIN and COUT are selected. This circuit
can be configured for operation up to an input voltage of 160
150V. 150
ILOAD(MAX) • RSENSE (mV)

Inductor Current Sensing and Slope Compensation 140
The LTC3777 operates using inductor current mode 130
control. The LTC3777 measures the peak of the inductor 120

current waveform in the boost region and the valley of
110
the inductor current waveform in the buck region. The
inductor current is sensed across the RSENSE resistor with 100
pins SENSEP and SENSEN. During any given cycle, the 90

0.1 1 10
peak (boost region) or valley (buck region) of the inductor VIN /VOUT (V)
current is controlled by the ITH pin voltage. 3777 F06
Figure 6. Load Current vs VIN /VOUT

Slope compensation provides stability in constant
frequency architectures by preventing subharmonic
oscillations at high duty cycles in boost operation and at Boost Region: In the boost region, the maximum output
low duty cycles in buck operation. This is accomplished current capability is the least when VIN is at its minimum
internally by adding a compensating ramp to the inductor and VOUT is at its maximum. Therefore RSENSE must be
current signal at duty cycles in excess of 40% in the boost chosen to meet the output current requirements under
region, or subtracting a ramp from the inductor current these conditions.
signal at lower than 40% duty cycles in the buck region.
Normally, this results in a reduction of maximum inductor Start by finding the boost region duty cycle when VIN is
peak current for duty cycles >40% in the boost region, minimum and VOUT is maximum using:
or an increase of maximum inductor current for duty ⎛ VIN(MIN) ⎞
cycles <40% in the buck region. However, the LTC3777 DC(MAX,C,BOOST) ≅ ⎜ 1– ⎟ •100%
uses a scheme that counteracts this compensating ramp, ⎝ VOUT(MAX) ⎠
which allows the maximum inductor current to remain
unaffected throughout all duty cycles. For example, an application with a VIN range of 12V to
48V and VOUT set to 36V will have:
RSENSE Selection and Maximum Output Current ⎛ 12V ⎞
DC(MAX,C,BOOST) ≅ ⎜ 1– •100% = 67%
The RSENSE resistance must be chosen properly to achieve ⎝ 36V ⎟⎠
the desired amount of output current. Too much resistance
can limit the output current below the application Next, the inductor ripple current in the boost region must
requirements. Start by determining the maximum allowed be determined. If the main inductor L is not known, the
RSENSE resistance in the boost region, RSENSE(MAX,BOOST). maximum ripple current ∆IL(MAX,BOOST) can be estimated
Follow this by finding the maximum allowed RSENSE
Rev A

LTC3777
by choosing ∆IL(MAX,BOOST) to be 30% to 50% of the Using values from the previous examples:
maximum inductor current in the boost region as follows: 2 •140mV •12
RSENSE(MAX,BOOST) = = 18.66mΩ
VOUT(MAX) •IOUT(MAX,BOOST) (2 • 2A • 36V ) + (3A •12V )
∆IL(MAX,BOOST) ≅ A
⎛ 100% ⎞
VIN(MIN) • ⎜ – 0.5⎟ Buck Region: The duty cycle for buck operation can be
⎝ %Ripple ⎠
calculated using:
where: ⎛ VOUT(MIN) ⎞
DC(MAX,B,BUCK) ≅ ⎜ 1− • 100%
IOUT(MAX,BOOST) is the maximum output load current ⎝ VIN(MAX) ⎟⎠
required in the boost region
%Ripple is 30% to 50% Before calculating the maximum RSENSE resistance,
however, the inductor ripple current must be determined.
For example, using VOUT(MAX) = 36V, VIN(MIN) = 12V, If the main inductor L is not known, the ripple current
IOUT(MAX,BOOST) = 2A and %Ripple = 40% we can estimate: ∆IL(MIN,BUCK) can be estimated by choosing ∆IL(MIN,BUCK)
36V • 2A to be 10% of the maximum inductor current in the buck
∆ IL(MAX,BOOST) ≅ = 3A region as follows:
⎛ 100% ⎞
12V • ⎜ – 0.5⎟
⎝ 40% ⎠ IOUT(MAX,BUCK)
∆IL(MIN,BUCK) ≅ A
Otherwise, if the inductor value is already known then ⎛ 100% ⎞
⎜⎝ – 0.5⎟
10% ⎠
∆IL(MAX,BOOST) can be more accurately calculated as
follows:
where:
⎛ DC(MAX,C,BOOST) ⎞ IOUT(MAX,BUCK) is the maximum output load current
⎜⎝ 100% ⎟⎠ • VIN(MIN) required in the buck region.
∆IL(MAX,BOOST) = A
f •L If the inductor value is already known then ∆IL(MIN,BUCK)
where: can be calculated as follows:
DC(MAX,C,BOOST) is the maximum duty cycle percentage ⎛ DC(MIN,B,BUCK) ⎞

in the boost region as calculated previously. ⎜⎝ 100% ⎟⎠ • VOUT(MIN)
∆IL(MIN,BUCK ) = A
f is the switching frequency f •L
L is the inductance of the main inductor where:
After the maximum ripple current is known, the maximum DC(MIN,B,BUCK) is the minimum duty cycle percentage
allowed RSENSE in the boost region can be calculated as in the buck region as calculated previously.
follows:
f is the switching frequency
RSENSE(MAX,BOOST) =
L is the inductance of the main inductor
2 • VRSENSE(MAX,BOOST,MAXDC) • VIN(MIN)
Ω After the inductor ripple current is known, the maximum
( )(
2 •IOUT(MAX,BOOST) • VOUT(MIN) + ∆IL(MAX,BOOST) • VIN(MIN) ) allowed RSENSE in the buck region can be calculated as
follows:
where VRSENSE(MAX, BOOST,MAXDC) is the maximum
2 • VRSENSE(MAX,BUCK,MINDC)
inductor current sense voltage as discussed in the RSENSE(MAX,BUCK) = Ω
previous section. (2 •IOUT(MAX,BUCK) ) – ∆IL(MIN,BUCK)
Rev A

LTC3777
Programming Input/Output Current Limit accordingly. For example, if the IAVGSNSP branch has a
100Ω resistor, the 1.50mV across it can be replicated in
As shown in Figure 7 and Figure 8, input/output current
sense resistor RSENSE2 should be placed between the bulk the IAVGSNSN branch by using a 150Ω resistor.
capacitor for VIN or VOUT and the decoupling capacitor. When the IAVGSNS common mode voltage falls below
A lowpass filter formed by RF and CF is recommended to ~4V, the IAVGSNS current decreases linearly; it reaches
reduce the switching noise and stabilize the current loop. approximately –300µA at zero volts. The maximum
The input/output current limit is set internally to 50mV. If current sinking can vary by 20% to 30% due to process
input/output current limit is not desired, the IAVGSNSP and variation. Ensure that IAVGSNS common mode voltage
IAVGSNSN pins should be shorted together to V5. never exceeds its absolute maximum of –10V below
ground. Pay special attention to short-circuit conditions
TO DRAIN OF
RSENSE2
TO
in high power applications.
SWITCH D
RF CF RF + SYSTEM
VOUT
100Ω 100Ω Phase-Locked Loop and Frequency Synchronization
2 1 The LTC3777 has a phase-locked loop (PLL) comprised of
IAVGSNSP IAVGSNSN an internal voltage-controlled oscillator (VCO) and a phase
LTC3777
detector. This allows the turn-on of the bottom MOSFET of
3777 F07
the controller to be locked to the rising edge of an external
Figure 7. Programming Output Current Limit clock signal applied to the PLLIN pin. The phase detector
is an edge sensitive digital type that provides zero degrees
RSENSE2
phase shift between the external and internal oscillators.
FROM DC TO DRAIN OF
POWER INPUT + SWITCH A This type of phase detector does not exhibit false locking
RF CF RF
100Ω 100Ω to harmonics of the external clock.
2 1
The output of the phase detector is a pair of complementary
IAVGSNSP IAVGSNSN current sources that charge or discharge the internal filter
LTC3777 network. There is a precision 20µA of current flowing out
3777 F08
of the FREQ pin. This allows a single resistor to SGND
Figure 8. Programming Input Current Limit to set the switching frequency when no external clock
is applied to the PLLIN pin. The internal switch between
FREQ and the integrated PLL filter network is on, allowing
With the typical 100Ω resistors shown here, the value the filter network to be pre-charged at the same voltage as
of capacitor CF should be 1µF to 4.7µF. The current the FREQ pin. The relationship between the voltage on the
loop’s transfer function should approximate that of the FREQ pin and operating frequency is shown in Figure 9
voltage loop. Crossover frequency should be one-tenth and specified in the Electrical Characteristics table. If an
the switching frequency, and gain should decrease by external clock is detected on the PLLIN pin, the internal
20dB/decade. Similar current and voltage loop transfer switch previously mentioned will turn off and isolate the
functions will ensure overall system stability. influence of the FREQ pin.
When the IAVGSNS common mode voltage is above ~4V,
the IAVGSNSN pin sources 10µA. The IAVGSNSP pin, however,
sources 15µA, when a constant current is being regulated.
The error introduced by this mismatch can be offset to a
first order by scaling the IAVGSNSP and IAVGSNSN resistors
Rev A

LTC3777
Note that the LTC3777 can only be synchronized to an adjusted until the phase and frequency of the internal and
external clock whose frequency is within range of the external oscillators are identical. At the stable operating
LTC3777’s internal VCO. This is guaranteed to be between point, the phase detector output is high impedance and
50kHz and 600kHz. A simplified block diagram is shown the filter capacitor holds the voltage.
in Figure 10.
Typically, the external clock (on the PLLIN pin) input high
threshold is 2V, while the input low threshold is 1.2V.
250
The operating frequency of the LTC3777 can be
200 approximated using the following formula:
RFREQ = 0.000115(fOSC)2 + 0.174 (fOSC) + 18.5
150
RFREQ (kΩ)
where fOSC is in kHz and RFREQ is in kΩ.

100
Inductor Selection
50
The operating frequency and inductor selection are
interrelated in that higher operating frequencies allow the
0
0 100 200 300 400 500 600 700 800 use of smaller inductor and capacitor values. The inductor
FREQUENCY (kHz)
3777 F09
value has a direct effect on ripple current. The inductor
Figure 9. FREQ Pin Resistor Value vs Frequency
current ripple ∆IL is typically set to 20% to 40% of the
maximum inductor current in the boost region at VIN(MIN).
5.5V 5.5V
For a given ripple the inductance terms in continuous
RSET mode are as follows:
20µA
FREQ
LBOOST >
VIN(MIN) 2
( )
• VOUT − VIN(MIN) • 100
H,
MODE/ 2
PLLIN DIGITAL SYNC
f •IOUT(MAX) • %Ripple • VOUT
( )
EXTERNAL PHASE/
OSCILLATOR FREQUENCY VCO VOUT • VIN(MAX) − VOUT • 100
DETECTOR LBUCK > H
f •IOUT(MAX) • %Ripple • VIN(MAX)
where:
3777 F10
f is operating frequency, Hz
Figure 10. Phase-Locked Loop Block Diagram
% Ripple is allowable inductor current ripple
VIN(MIN) is minimum input voltage, V
If the external clock frequency is greater than the internal VIN(MAX) is maximum input voltage, V
oscillator’s frequency, fOSC, then current is sourced VOUT is output voltage, V
continuously from the phase detector output, pulling up IOUT(MAX) is maximum output load current, A
the filter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down For high efficiency, choose an inductor with low core loss,
the filter network. If the external and internal frequencies such as ferrite. Also, the inductor should have low DC
are the same but exhibit a phase difference, the current resistance to reduce the I2R losses, and must be able to
sources turn on for the amount of time corresponding to handle the peak inductor current without saturating. To
the phase difference. The voltage on the filter network is minimize radiated noise, use a toroid, pot core or shielded
bobbin inductor.
Rev A

LTC3777
Inductor Core Selection for a given output ripple voltage. The steady ripple due to
Once the inductance value is determined, the type of charging and discharging the bulk capacitance is given by:
inductor must be selected. Core loss is independent of
core size for a fixed inductor value, but it is very dependent ΔVRIPPLE(BOOST,CAP) =
(
IOUT(MAX) • VOUT − VIN(MIN) )V
on inductance selected. As inductance increases, core COUT • VOUT • f
losses go down. Unfortunately, increased inductance where COUT is the output filter capacitor.
requires more turns of wire and therefore copper losses
will increase. The steady ripple due to the voltage drop across the ESR
is given by:
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can ∆V(BOOST,ESR) = IOUT(MAX,BOOST) • ESR
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
In buck mode, VOUT ripple is given by:
inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase ⎛ 1 ⎞
ΔVOUT ≤ ΔIL ⎜ ESR +
in inductor ripple current and consequent output voltage ⎝ 8 • f • COUT ⎟⎠
ripple. Do not allow the core to saturate!
Multiple capacitors placed in parallel may be needed to
CIN and COUT Selection meet the ESR and RMS current handling requirements.
In the boost region, input current is continuous. In the Aluminum electrolytic and ceramic capacitors are available
buck region, input current is discontinuous. In the buck in surface mount packages. Ceramic capacitors have
region, the selection of input capacitor CIN is driven by excellent low ESR characteristics but can have a high
the need to filter the input square wave current. Use a low voltage coefficient. Bulk capacitors are now available with
ESR capacitor sized to handle the maximum RMS current. low ESR and high ripple current ratings, such as OSCON and
For buck operation, the input RMS current is given by: aluminum electrolytics with hybrid conductive polymers.
VOUT VIN Power MOSFET Selection and Efficiency
IRMS ≈ IOUT(MAX) • • −1
VIN VOUT Considerations
The LTC3777 requires four external N-channel power
This formula has a maximum at VIN = 2VOUT, where
MOSFETs, two for the top switches (switches A and
IRMS = IOUT(MAX) / 2. This simple worst-case condition
D, shown in Figure 1) and two for the bottom switches
is commonly used for design because even significant
(switches B and C, shown in Figure 1). Important
deviations do not offer much relief. Note that ripple
parameters for the power MOSFETs are the breakdown
current ratings from capacitor manufacturers are often
voltage VBR,DSS, threshold voltage VGS,TH, on-resistance
based on only 2000 hours of life which makes it advisable
RDS(ON), reverse transfer capacitance CRSS and maximum
to derate the capacitor.
current IDS(MAX).
In the boost region, the discontinuous current shifts
The peak-to-peak drive levels are set by the DRVCC
from the input to the output, so COUT must be capable
voltage. This voltage can range from 6V to 10V depending
of reducing the output voltage ripple. The effects of ESR
on the DRVSET pin setting. Therefore, both logic-level
(equivalent series resistance) and the bulk capacitance
and standard-level threshold MOSFETs can be used in
must be considered when choosing the right capacitor
Rev A

LTC3777
most applications, depending on the programmed DRVCC Switch B operates in the buck region as the synchronous
voltage. Pay close attention to the BVDSS specification for rectifier. Its power dissipation at maximum output current
the MOSFETs as well. is given by:
The LTC3777’s ability to adjust the gate drive level between VIN VOUT
PB,BUCK = •IOUT(MAX)2 • • RDS(ON)
6V to 10V allows an application circuit to be precisely VIN
optimized for efficiency. When adjusting the gate drive level,
the final arbiter is the total input current for the regulator. Switch C operates in the boost region as the control switch.
If a change is made and the input current decreases, then Its power dissipation at maximum current is given by:
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency. PC,BOOST =
( VOUT VIN ) VOUT
•IOUT(MAX)2 •
2
VIN
In order to select the power MOSFETs, the power
dissipated by the device must be known. For switch A, IOUT(MAX)
•RDS(ON) + k • VOUT 3 • • CRSS • f
the maximum power dissipation happens in the boost VIN
region, when it remains on all the time. Its maximum
power dissipation at maximum output current is given by: where CRSS is usually specified by the MOSFET
2 manufacturers. The constant k, which accounts for the
⎛V ⎞ loss caused by reverse recovery current, is inversely
PA,BOOST = ⎜ OUT •IOUT(MAX) ⎟ • ρτ • RDS(ON)
⎝ VIN ⎠ proportional to the gate drive current and has an empirical
value of 1.7.
where ρt is a normalization factor (unity at 25°C)
For switch D, the maximum power dissipation happens
accounting for the significant variation in on-resistance
in the boost region, when its duty cycle is higher than
with temperature, typically about 0.4%/°C, as shown in
50%. Its maximum power dissipation at maximum output
Figure 11. For a maximum junction temperature of 125°C,
current is given by:
using a value ρt = 1.5 is reasonable.
2
V ⎛V ⎞
PD,BOOST = IN • ⎜ OUT •IOUT(MAX) ⎟ • ρτ • RDS(ON)
2.0 VOUT ⎝ VIN ⎠
ρT NORMALIZED ON-RESISTANCE (Ω)
1.5 For the same output voltage and current, switch A has the
highest power dissipation and switch B has the lowest
power dissipation unless a short occurs at the output.
1.0
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
0.5
formula:
TJ = TA + P • RTH(JA)
0
–50 0 50 100 150
JUNCTION TEMPERATURE (°C)
The RTH(JA) to be used in the equation normally includes
3777 F11 the RTH(JC) for the device plus the thermal resistance from
Figure 11. Normalized RDS(ON) vs Temperature the case to the ambient temperature (RTH(JC)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
Rev A

LTC3777
Schottky Diode (D1, D2) Selection DRVCC and V5 LDOs. In this state the LTC3777 draws only
40μA of quiescent current. Releasing the RUN pin allows
The Schottky diodes, D1 and D2, shown in the Block
an internal 2.5µA current to pull-up the pin and enable the
Diagram, conduct during the dead time between the
controller. The RUN comparator itself has about 100mV
conduction of the power MOSFET switches. They are
of hysteresis. When the voltage on the RUN pin exceeds
intended to prevent the body diode of synchronous
switches B and D from turning on and storing charge 1.2V, the current sourced into the RUN pin is switched
from 2.5µA to 6.5µA current. The user can therefore
during the dead time. In particular, D2 significantly
program both the rising threshold and the amount of
reduces reverse recovery current between switch D
hysteresis using an external resistive divider.
turn-off and switch C turn-on, which improves converter
efficiency and reduces switch C voltage stress. In order The RUN pin is high impedance above 3V and must be
for the diode to be effective, the inductance between it externally pulled up/down or driven directly by logic, as
and the synchronous switch must be as small as possible, shown in Figure 13. The RUN pin can tolerate up to 150V
mandating that these components be placed adjacently. (absolute maximum), so it can be conveniently tied to VIN
in always-on applications where the controller is enabled
Setting Output Voltage continuously and never shut down.
The LTC3777 output voltage is set by two external The RUN and VINOV pins can alternatively be configured as
feedback resistive dividers carefully placed across the undervoltage (UVLO) and overvoltage (OVLO) lockouts on
output, as shown in Figure 12. The regulated output the VIN supply with a resistor divider from VIN to ground. A
voltage is determined by: simple resistor divider can be used as shown in Figure 14
VOUT = 1.2V • (1 + RB /RA) to meet specific VIN voltage requirements. One can
program additional hysteresis for the RUN comparator
To improve the frequency response, a feed forward by adjusting the values of the resistive divider.
capacitor, CFF, may be used. Great care should be taken
to route the VFB line away from noise sources, such as
the inductor or the SW line. VIN
SUPPLY
LTC3777 4.7M LTC3777
VOUT RUN RUN
RB CFF 3777 F13

LTC3777
VFB
Figure 13. RUN Pin Interface to Logic
RA
3777 F12
Figure 12. Setting Output Voltage VIN
R3
RUN Pin and Overvoltage /Undervoltage Lockout RUN
R4 LTC3777
The LTC3777 is enabled using the RUN pin. It has a rising VINOV
threshold of 1.2V with 100mV of hysteresis. Pulling the R5 3777 F14
RUN pin below 1.1V shuts down the main control loop
for the controller and most internal circuits, including the
Figure 14. Adjustable UV and OV Lockout
Rev A

LTC3777
The current that flows through the R3-R4-R5 divider will Soft-Start
directly add to the shutdown and active current of the The start-up of VOUT is controlled by the voltage on the SS
LTC3777, and care should be taken to minimize the impact pin. If its RUN pin voltage is below 1.1V the controller is in
of this current on the overall efficiency of the application the shutdown state; its SS pin is actively pulled to ground
circuit. Resistor values in the megohm range may be in this shutdown state. If the RUN pin voltage is above
required to keep the impact on quiescent shutdown 1.2V, the controller powers up. A soft-start current of
current low. To pick resistor values, the sum total of R3 5μA then starts to charge the SS soft-start capacitor. Note
+ R4 + R5 (RTOTAL) should be chosen first based on the that soft-start is achieved not by limiting the maximum
allowable DC current that can be drawn from VIN. output current of the controller but by controlling the
The individual values of R3, R4 and R5 can then be output ramp voltage according to the ramp rate on the
calculated from the following equations: SS pin. When the voltage on the SS pin is less than the
internal 1.2V reference, the LTC3777 regulates the VFB pin
⎛ 1.2V ⎞ voltage to the voltage on the SS pin instead of the internal
R5 = RTOTAL • ⎜
⎝ Rising VIN OVLO Threshold ⎟⎠ reference. Current foldback is disabled during this phase.
⎛ ⎞ The soft-start range is defined to be the voltage range
1.2V
R4 = RTOTAL • ⎜ − R5 from 0V to 1.2V on the SS pin. The total soft-start time
⎝ Rising VIN UVLO Threshold ⎟⎠ can be calculated as:
R3 = RTOTAL − R4 − R5
⎛ 1.2V ⎞
tSS = CSS • ⎜
For applications that do not need a precise external OVLO, ⎝ 5µA ⎟⎠
the VINOV pin should be tied directly to ground. The RUN
pin in this type of application can be used as an external DRVCC Regulator
UVLO using the following equations with R5 = 0Ω.
In addition to the switching bias supply, the LTC3777
⎛ R3 ⎞ features two separate low dropout linear regulators (LDO)
VIN(ON) = 1.2V ⎜ 1+ ⎟ − 2.5µ • R3
⎝ R4 ⎠ that can supply power at the DRVCC pin. The internal VIN
LDO uses an internal P-channel pass device between the
⎛ R3 ⎞
VIN(OFF) = 1.1V ⎜ 1+ ⎟ − 6.5µ • R3 VIN and DRVCC pins. The internal EXTVCC LDO uses an
⎝ R4 ⎠
internal P-channel pass device between the EXTVCC and
DRVCC pins.
Similarly, for applications that do not require a precise
UVLO, the RUN pin can be tied to VIN. In this configuration, The DRVCC supply is regulated between 6V to 10V,
the UVLO threshold is limited to the internal VIN UVLO depending on the DRVSET pin setting. The internal VIN
thresholds as shown in the Electrical Characteristics table. and EXTVCC LDOs can supply a peak current of at least
The resistor values for the OVLO can be computed using 50mA. The DRVCC pin must be bypassed to ground with
the previous equations with R3 = 0Ω. a minimum of 4.7μF ceramic capacitor. Good bypassing is
needed to supply the high transient currents required by
Be aware that the VINOV pin cannot be allowed to exceed
the MOSFET gate drivers. The DRVSET pin programs the
its absolute maximum rating of 6V. To keep the voltage on
DRVCC supply voltage and selects the appropriate EXTVCC
the VINOV pin from exceeding 6V, the following relation
switchover threshold voltages as shown in the Electrical
should be satisfied:
Characteristics table. The DRVSET pin has five logic level
⎛ R5 ⎞ states. When DRVSET is either grounded, floated or tied to
VIN(MAX) • ⎜ < 6V
⎝ R3 + R4 + R5 ⎟⎠
Rev A

LTC3777
V5, the typical value for the DRVCC voltage will be 6V, 8V dropout and the DRVCC voltage is approximately equal to
and 10V respectively. Use the 10V setting with careful PCB EXTVCC. When EXTVCC is greater than the programmed
layout. This is because any overshoot between BOOST voltage, up to an absolute maximum of 36V, DRVCC is
and SW would exceed the absolute maximum voltage of regulated to the programmed voltage.
11V for the floating driver. Set DRVSET to one-fourth of Using the EXTVCC LDO allows the MOSFET driver and
V5 and three-fourths of V5 for 7V and 9V DRVCC voltages. control power to be derived from the LTC3777’s switching
Please note that the DRVSET pin has an internal 200k regulator output (5.7V ≤ VOUT ≤ 36V) during normal
pull-down to SGND and a 200k pull-up to V5. The EXTVCC operation and from the VIN LDO when the output is out
turn on threshold is the selected DRVCC regulation voltage
of regulation (e.g., start-up, short-circuit).
minus 500mV. The turn off threshold is 500mV below the
turn on threshold. Significant efficiency and thermal gains can be realized by
powering DRVCC from the output, since the VIN current
High input voltage applications in which large MOSFETs resulting from the driver and control currents will be
are being driven at high frequencies may cause the scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
maximum junction temperature rating for the LTC3777 to
be exceeded. The DRVCC current, which is dominated by For 5.5V to 36V regulator outputs, this means connecting
the gate charge current, may be supplied by the VIN LDO, the EXTVCC pin directly to VOUT. Tying the EXTVCC pin
or the EXTVCC LDO. When the voltage on the EXTVCC pin to a 12V supply reduces the junction temperature in the
is less than its switchover threshold (as determined by the previous example from 125°C to:
DRVSET pin), the VIN LDO is enabled. Power dissipation
TJ = 70°C + 38mA • (12V) ( 36°C / W ) = 86°C
in this case is highest and is equal to VIN • IDRVCC. This
power is dissipated inside the IC. The gate charge current While using the EXTVCC LDO there is an VIN under voltage
is dependent on operating frequency as discussed in the detection circuit that disables the EXTVCC LDO if the VIN
Efficiency Considerations section. voltage is less that the DRVCC voltage that is set by the
The junction temperature can be estimated by using the DRVSET pin.
equations given in Note 2 of the Electrical Characteristics For applications where the minimum VIN voltage of
table. For example, if DRVCC is set to 6V, the DRVCC current LTC3777 needs to be less than 4.5V, the EXTVCC pin can
is limited to less than 38mA from a 40V supply when not be used to power the VIN of LTC3777. The VIN under
using the EXTVCC LDO at a 70°C ambient temperature: voltage detection circuit is disabled when DRVSET is set
TJ = 70°C + (38mA)(40V)(36°C/W) = 125°C to three-fourths of V5, for 9V DRVCC voltage. Under this
condition the DRVCC voltage can be higher than the VIN
To prevent the maximum junction temperature from being of LTC3777 and an external blocking diode should be
exceeded, the VIN supply current must be checked while connected from the VIN pin of LTC3777 to the external
operating in forced continuous mode (MODE = SGND) at VIN supply, to avoid back feeding the VIN supply.
maximum VIN.
The following list summarizes the four possible
When the voltage applied to EXTVCC rises above its connections for EXTVCC:
switchover threshold, the VIN LDO is turned off and the
EXTVCC LDO is enabled. The EXTVCC LDO remains on as 1. EXTVCC grounded. This will cause DRVCC to be
long as the voltage applied to EXTVCC remains above the powered from the internal VIN LDO resulting in an
switchover threshold minus the comparator hysteresis. efficiency penalty of up to 10% at high input voltages.
The EXTVCC LDO attempts to regulate the DRVCC voltage 2. EXTVCC connected directly to the regulator output.
to the voltage as programmed by the DRVSET pin, so This is the normal connection for a 5.5V to 36V
while EXTVCC is less than this voltage, the LDO is in regulator and provides the highest efficiency.
Rev A

LTC3777
3. EXTVCC connected to BVOUT the integrated switching 2. It can also be used as a standalone bias to power
bias supply output. other supply rails in the system.
For most applications, the design process to configure the
V5 Regulator
switching bias supply is simple, summarized as follows:
An additional P-channel LDO supplies power at the V5
1. In Table 1 find the row that has the desired input
pin from the DRVCC pin. Whereas DRVCC powers the
voltage and output voltage.
gate drivers, V5 powers much of the LTC3777’s internal
circuitry. The V5 LDO regulates the voltage at the V5 pin 2. Apply the recommended CIN, COUT, L, R1 and R2.
to 5.5V when DRVCC is at least 6V. The LDO can supply 3. Connect the BVOUT to the EXTVCC pin to bias the buck-
a peak current of 20mA and must be bypassed to ground boost controller.
with a minimum of 4.7μF ceramic capacitor or low
ESR electrolytic capacitor. No matter what type of bulk The output voltage is set by an external resistive divider
capacitor is used, an additional 0.1μF ceramic capacitor according to the following equation:
placed directly adjacent to the V5 and SGND pins is highly ⎛ R1⎞
recommended. V5 is also used as a pull-up to bias other BVOUT = 0.8V • ⎜ 1+ ⎟
⎝ R2 ⎠
pins, such as MODE, DRVSET and SS.
The resistive divider allows the BVFB pin to sense a fraction
Integrated Switching Bias Supply
of the output voltage as shown in Figure 15. The output
The integrated switching bias is a 150V high efficiency voltage can range from 0.8V to VIN. Be careful to keep the
step-down regulator with internal high side and divider resistors very close to the BVFB pin to minimize
synchronous power switches that can supply up to 85mA noise pick-up on the sensitive BVFB trace.
load current. The 150V switching bias draws only 12µA
typical DC supply current while maintaining a regulated
BVOUT
output voltage at no load. Using the integrated bias for
LTC3777
high VIN application increases the overall efficiency of the 0.8V
R1
system, and reduces power dissipation. BVFB

R2
The switching bias supply of LTC3777 can be used for 3777 F15
the following purposes:

Figure 15. Setting the Switching Bias Supply
1. If the output voltage of the buck-boost controller Output Voltage
is higher than 36V, which exceeds the absolute
maximum voltage rating of the EXTVCC pin, then
the integrated switching bias supply can be used to
provide a 12V bias to power the buck-boost controller.
Table 1. Switching Bias Supply Recommended Component Values and Configuration

BVIN BVOUT CIN COUT L R1 R2
12V to 150V 12V 1µF TDK C5750X7R2E105K 2 × 22µF AVX 12103D226KAT2A 220µH SUMIDA CDRH105RNP-221NC 715k 51.1k
5V to 150V 5V 1µF TDK C5750X7R2E105K 10µF TDK C3216X7R1C106M 1000µH TDK SLF12555T-102MR34 422k 80.6k
4V to 150V 3.3V 1µF TDK C5750X7R2E105K 22µF AVX 12103D226KAT2A 150µH Coilcraft LPS6235-154ML 309k 97.6k
Rev A

LTC3777
To minimize the no-load supply current, resistor values in The current that flows through the R3-R4-R5 divider
the megohm range may be used; however, large resistor will directly add to the shutdown, sleep, and active
values should be used with caution. The feedback divider current of the switching bias supply, and care should
is the only load current when in shutdown. If PCB leakage be taken to minimize the impact of this current on the
current to the output node or switch node exceeds the load overall efficiency of the application circuit. Resistor
current, the output voltage will be pulled up. In normal values in the megohm range may be required to keep
operation, this is generally a minor concern since the load the impact on quiescent shutdown and sleep currents
current is much greater than the leakage. low. To pick resistor values, the sum total of R3 + R4
+ R5 (RTOTAL) should be chosen first based on the
The switching bias supply has a low power shutdown
mode controlled by the BRUN pin. Pulling the BRUN pin allowable DC current that can be drawn from BVIN.
below 0.7V puts the switching bias supply into a low The individual values of R3, R4 and R5 can then be
calculated from the following equations:
quiescent current shutdown mode (IQ ~ 1.4µA). When
the BRUN pin is greater than 1.21V, switching is enabled. 1.21V
R5 = R TOTAL •
Figure 16 shows examples of configurations for driving Rising BVIN OVLO Threshold
the BRUN pin from logic.
1.21V
The BRUN and BOV pins can alternatively be configured R4 = R TOTAL • –R5
as precise undervoltage (UVLO) and overvoltage (OVLO) Rising BVIN UVLO Threshold
lockouts on the BVIN supply with a resistive divider from R3 = R TOTAL –R5 –R4
BVIN to ground. A simple resistive divider can be used
as shown in Figure 17 to meet specific BVIN voltage For applications that do not need a precise external OVLO,
requirements. the BOV pin should be tied directly to ground. The BRUN
pin in this type of application can be used as an external
BVIN UVLO using the previous equations with R5 = 0Ω.
SUPPLY
LTC3777 4.7M LTC3777 Similarly, for applications that do not require a precise
BRUN BRUN UVLO, the BRUN pin can be tied to BVIN. In this
configuration, the UVLO threshold is limited to the
3777 F16 internal BVIN UVLO thresholds as shown in the Electrical
Characteristics table. The resistor values for the BOV can
Figure 16. BRUN Pin Interface to Logic be computed using the previous equations with R3 = 0Ω.
Be aware that the BOV pin cannot be allowed to exceed
BVIN its absolute maximum rating of 6V. To keep the voltage
on the BOV pin from exceeding 6V, the following relation
R3
should be satisfied:
BRUN
R4 LTC3777 ⎛ R5 ⎞
BVIN(MAX) • ⎜ < 6V
BOV
⎝ R3+R4+R5 ⎟⎠
R5 3777 F17
Figure 17. Switching Bias Supply Adjustable UV and OV Lockout
Rev A

LTC3777
Pre-Biased Output Start-Up In the buck region, maximum sense voltage and the sense
resistance determine the maximum allowed inductor
There may be situations that require the power supply to
valley current, which is:
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that 90mV
IL(MAX,BUCK) =
output pre-bias. The LTC3777 can safely power up into a R SENSE
pre-biased output without discharging it.
If the voltage on the SS pin is lower than VFB, to prevent To further limit current in the event of a short circuit to
pulling current from the output to the input, the LTC3777 ground, the LTC3777 includes foldback current limiting.
forces the part into discontinuous mode of operation If the output falls by more than 50%, then the maximum
irrespective of the status of the MODE pin. If VFB is sense voltage is progressively lowered to about one-third
>1.12V, or when the SS voltage crosses VFB or 1.32V, of its full value.
whichever event happens first, then the MODE pin setting
Efficiency Considerations
determines the mode of operation.
The percent efficiency of a switching regulator is equal to
Topside MOSFET Driver Supply the output power divided by the input power times 100%.
In the Block Diagram, the external bootstrap capacitors It is often useful to analyze individual losses to determine
CA and CB, connected to the BOOST1 and BOOST2 pins, what is limiting the efficiency and which change would
supply the gate drive voltage for the topside MOSFET produce the most improvement. Percent efficiency can
switches A and D. When the top switch A turns on, the be expressed as:
switch node SW1 rises to VIN and the BOOST1 pin rises % Efficiency = 100% – (L1 + L2 + L3 + ...)
to approximately VIN + DRVCC. When the bottom switch
where L1, L2, etc. a e the individual losses as a percentage
B turns on, the switch node SW1 is low and the boost
of input power.
capacitor CA is charged through DA from DRVCC. When
the top switch D turns on, the switch node SW2 rises to Although all dissipative elements in the circuit produce
VOUT and the BOOST2 pin rises to approximately VOUT + losses, four main sources usually account for most of the
DRVCC. When the bottom switch C turns on, switch node losses in LTC3777 circuits: 1) IC VIN current, 2) MOSFET
SW2 is low and the boost capacitor CB is charged through driver current, 3) I2R losses, 4) topside MOSFET transition
DB from DRVCC. The boost capacitors CA and CB need to losses.
store about 100 times the gate charge required by the top 1. The VIN current is the DC supply current given in the
switches A and D. In most applications, a 0.1µF to 0.47µF, Electrical Characteristics table. VIN current typically
X5R or X7R dielectric capacitor is adequate. results in a small (<0.1%) loss.
Fault Conditions: Current Limit and Current Foldback 2. The MOSFET driver current results from switching the
gate capacitance of the power MOSFETs. Each time
The maximum inductor current is inherently limited in a
a MOSFET gate is switched from low to high to low
current mode controller by the maximum sense voltage. In
again, a packet of charge dQ moves from the driver
the boost region, maximum sense voltage and the sense
supply to ground. The resulting dQ/dt is a current
resistance determine the maximum allowed inductor peak
out of the driver supply that is typically much larger
current, which is:
than the control circuit current. In continuous mode,
140mV IGATECHG = f(QT + QB), where QT and QB are the gate
IL(MAX,BOOST) =
R SENSE charges of the topside and bottom side MOSFETs.
Rev A

LTC3777
3. I2R losses are predicted from the DC resistances of Checking Transient Response
the fuse (if used), MOSFET, inductor and current sense The regulator loop response can be checked by looking at
resistor. In continuous mode, the average output the load current transient response. Switching regulators
current flows through L and RSENSE, but is chopped take several cycles to respond to a step in DC (resistive)
between the topside MOSFET and the synchronous load current. When a load step occurs, VOUT shifts by an
MOSFET. If the two MOSFETs have approximately the amount equal to ∆ILOAD • ESR, where ESR is the effective
same RDS(ON), then the resistance of one MOSFET series resistance of COUT. ∆ILOAD also begins to charge or
can simply be summed with the resistances of L and discharge COUT generating the feedback error signal that
RSENSE to obtain I2R losses. For example, if each forces the regulator to adapt to the current change and
RDS(ON) = 10mΩ, RL = 10mΩ, RSENSE = 5mΩ, then return VOUT to its steady-state value. During this recovery
the total resistance is 25mΩ. This results in losses time VOUT can be monitored for excessive overshoot or
ranging from 0.6% to 2% as the output current ringing, which would indicate a stability problem. The
increases from 3A to 15A for a 12V output. availability of the ITH pin not only allows optimization of
Efficiency varies as the inverse square of VOUT for control loop behavior but also provides a DC-coupled and
the same external components and output power AC-filtered closed-loop response test point. The DC step,
level. The combined effects of increasingly lower rise time and settling at this test point truly reflects the
output voltages and higher currents required by closed-loop response. Assuming a predominantly second
high performance digital systems is not doubling order system, phase margin and/or damping factor can be
but quadrupling the importance of loss terms in the estimated using the percentage of overshoot seen at this
switching regulator system! pin. The bandwidth can also be estimated by examining
the rise time at the pin.
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high The ITH external components shown in the Typical
input voltages (typically 15V or greater). Transition Application circuit will provide an adequate starting point
losses can be estimated from: for most applications. The ITH series RC -CC filter sets the
dominant pole-zero loop compensation. The values can
Transition Loss = (1.7) VIN2 • IO(MAX) • CRSS • f be modified slightly (from 0.5 to 2 times their suggested
Other hidden losses such as copper trace and internal values) to optimize transient response once the final PC
battery resistances can account for an additional 5% layout is done and the particular output capacitor type
to 10% efficiency degradation in portable systems. It and value have been determined. The output capacitors
is very important to include these system level losses need to be selected because the various types and values
during the design phase. The internal battery and fuse determine the loop gain and phase. An output current
resistance losses can be minimized by making sure that pulse of 20% to 80% of full-load current having a rise
CIN has adequate charge storage and very low ESR at time of 1μs to 10μs will produce output voltage and ITH
the switching frequency. A 25W supply will typically pin waveforms that will give a sense of the overall loop
require a minimum of 20μF to 40μF of capacitance having stability without breaking the feedback loop.
a maximum of 20mΩ to 50mΩ of ESR. Other losses Placing a power MOSFET directly across the output
including Schottky conduction losses during dead time capacitor and driving the gate with an appropriate signal
and inductor core losses generally account for less than generator is a practical way to produce a realistic load step
2% total additional loss. condition. The initial output voltage step resulting from
the step change in output current may not be within the
Rev A

LTC3777
bandwidth of the feedback loop, so this signal cannot be 2. Does the LTC3777 VFB pin’s resistive divider connect
used to determine phase margin. This is why it is better to to the (+) terminal of COUT? The resistive divider must
look at the ITH pin signal which is in the feedback loop and be connected between the (+) terminal of COUT and
is the filtered and compensated control loop response. signal ground. The feedback resistor connections
The gain of the loop will be increased by increasing should not be along the high current input feeds from
RC and the bandwidth of the loop will be increased by the input capacitor(s).
decreasing CC. If RC is increased by the same factor 3. Are the SENSEN and SENSEP leads routed together
that CC is decreased, the zero frequency will be kept the with minimum PC trace spacing? The filter capacitor
same, thereby keeping the phase shift the same in the between SENSE+ and SENSE– should be as close as
most critical frequency range of the feedback loop. The possible to the IC. Ensure accurate current sensing
output voltage settling behavior is related to the stability with Kelvin connections at the SENSE resistor.
of the closed-loop system and will demonstrate the actual
4. Is the DRVCC and decoupling capacitor connected
overall supply performance.
close to the IC, between the DRVCC and the ground
A second, more severe transient is caused by switching pin? This capacitor carries the MOSFET drivers’
in loads with large (>1μF) supply bypass capacitors. The current peaks.
discharged bypass capacitors are effectively put in parallel
5. Keep the SW, TG, and BOOST nodes away from
with COUT, causing a rapid drop in VOUT. No regulator can
sensitive small-signal nodes. All of these nodes have
alter its delivery of current quickly enough to prevent this
very large and fast moving signals and therefore
sudden step change in output voltage if the load switch
should be kept on the output side of the LTC3777
resistance is low and it is driven quickly. If the ratio of
and occupy minimum PC trace area.
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited 6. The path formed by switch A, switch B, D1 and the
to approximately 25 • CLOAD. Thus a 10μF capacitor would CIN capacitor should have short leads and PC trace
require a 250μs rise time, limiting the charging current lengths. The path formed by switch C, switch D, D2
to about 200mA. and the COUT capacitor also should have short leads
and PC trace lengths.
PC Board Layout Checklist
7. Use a modified star ground technique: a low
When laying out the printed circuit board, the following impedance, large copper area central grounding point
checklist should be used to ensure proper operation of on the same side of the PC board as the input and
the IC. output capacitors with tie-ins for the bottom of the
1. Are the signal and power grounds kept separate? DRVCC decoupling capacitor, the bottom of the voltage
The combined IC signal ground pin and the ground feedback resistive divider and the GND pin of the IC.
return of CDRVCC must return to the combined COUT
Design Example
(–) terminals. The path formed by the top N-channel
MOSFET, bottom N-channel MOSFET and the CIN VIN = 6V to 100V
capacitor should have short leads and PC trace
VOUT = 12V
lengths. The output capacitor (–) terminals should
be connected as close as possible to the (–) terminals IOUT(MAX) = 5A
of the input capacitor by placing the capacitors next f = 200kHz
to each other. Maximum ambient temperature = 60°C
Rev A

LTC3777
Set the frequency at 200kHz by applying 1.11V on the Select RB as 110k. Both RA and RB should have a tolerance
FREQ pin (see Figure 9). The 20µA current flowing out of no more than 1%.
of the FREQ pin will give 1.11V across a 55.6k resistor
to GND. The inductance value is chosen first based on a Selecting MOSFET Switches
30% ripple current assumption. In the buck region, the The MOSFETs are selected based on voltage rating and
ripple current is: RDS(ON) value. It is important to ensure that the part is
VOUT ⎛ V ⎞ specified for operation with the available gate voltage
∆IL,BUCK = • ⎜ 1– OUT ⎟ amplitude. In this case, the amplitude is 10V and MOSFETs
f •L ⎝ VIN ⎠
with an RDS(ON) value specified at VGS = 4.5V can be used.
∆IL,BUCK • 100 Select QA and QB. With 100V maximum input voltage
IRIPPLE,BUCK = % MOSFETs with a rating of at least 150V are used. As we do
IOUT
not yet know the actual thermal resistance (circuit board
The highest value of ripple current occurs at the maximum design and airflow have a major impact) we assume that
the MOSFET thermal resistance from junction to ambient
input voltage. In the boost region, the ripple current is:
is 50°C/W.
VIN ⎛ V ⎞ If we design for a maximum junction temperature, TJ(MAX)
∆IL,BOOST = • ⎜ 1– IN ⎟
f •L ⎝ VOUT ⎠ = 125°C, the maximum RDS(ON) value can be calculated.
First, calculate the maximum power dissipation:
∆I L,BOOST • 100
IRIPPLE,BOOST = % ⎛ TJ(MAX) − TA(MAX) ⎞
I IN PD(MAX) = ⎜ ⎟
⎝ R(j−a) ⎠
The highest value of ripple current occurs at VIN = VOUT/2. (125 − 60)
PD(MAX) = = 1.3W
A 15µH inductor will produce 10% ripple in the boost 50
region (VIN = 6V) and 70% ripple in the buck region (VIN
= 100V). The maximum dissipation in QA occurs at minimum input
voltage when the circuit operates in the boost region and
The RSENSE resistor value can be calculated by using the
QA is on continuously. The input current is then:
maximum current sense voltage specification with some
accommodation for tolerances. VOUT • IOUT(MAX)
, or 10A
2 • 140mV • VIN(MIN) VIN(MIN)
RSENSE =
2 •IOUT(MAX,BOOST) • VOUT + ∆IL,BOOST • VIN(MIN)
We calculate a maximum value for RDS(ON):
= 13.3mΩ
PD(MAX)
RDS(ON) (125°C) <
Adding an additional 30% margin, choose RSENSE to be IIN(MAX) 2
13.3mΩ/1.3 = 10mΩ.
1.3W
Output voltage is 12V. Select RA as 12.1k. RB is: RDS(ON) (125°C) < = 0.013Ω
(10A)2
VOUT • RA
RB = – RA
1.2
Rev A

LTC3777
The Infineon BSC360N15NS3G has a typical RDS(ON) The dissipation in switch QD is:
of 0.036Ω at VGS = 10V. Two MOSFETs can be used in 2
parallel to handle the power dissipation. V ⎛V ⎞
P D,BOOST = IN • ⎜ OUT • IOUT(MAX) ⎟
The maximum dissipation in QB occurs at maximum input VOUT ⎝ VIN ⎠
voltage when the circuit is operating in the buck region. • ρτ • RDS(ON)
The dissipation is:
VIN − VOUT BSC050NE2LS is a possible choice for QC and QD. The
P B,BUCK = • IOUT(MAX) 2 • ρτ • RDS(ON) calculated power loss at 6V input voltage is then 0.392W
VIN
for QC and 0.375W for QD.
1.3W
R DS(ON)(125°C) < = 0.059Ω CIN is chosen to filter the square current in the buck
⎛ 100V − 12V ⎞ 2
⎜⎝ ⎟ • (5A) region. In this mode, the maximum input current peak is:
100V ⎠
⎛ 70% ⎞
IIN,PEAK(MAX,BUCK) = 5A • ⎜ 1+ = 6.75A
The Infineon BSC190N15NS3G with a typical RDS(ON) of ⎝ 2 • 100% ⎟⎠
19mΩ can be used.
A low ESR (10mΩ) capacitor is selected. Input voltage
Select QC and QD. With 12V output voltage we need ripple is 67.5mV (assuming ESR dominates the ripple).
MOSFETs with 20V or higher rating.
COUT is chosen to filter the square current in the boost
The highest dissipation occurs at minimum input voltage region. In this mode, the maximum output current peak is:
when the inductor current is highest. For switch QC the
dissipation is: 12 ⎛ 10% ⎞
IOUT,PEAK(MAX,BOOST) = • 5 • ⎜ 1+ = 10.5A
6 ⎝ 2 • 100% ⎟⎠
(VOUT − VIN )VOUT
PC,BOOST =
VIN 2 A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 53mV (assuming ESR
• IOUT(MAX) 2 • ρτ • RDS(ON) dominates the ripple).
IOUT(MAX)
+ k • VOUT 3 • • CRSS • f
VIN
where CRSS is usually specified by the MOSFET

manufacturers. The constant k, which accounts for the
loss caused by reverse recovery current, is inversely
proportional to the gate drive current and has an empirical
value of 1.7.
Rev A

VIN
6V TO 100V
D2
10µF 1µF
125V ×3 8mΩ VOUT
200V 12V
D1
5A
22µF 270µF
1k ×3 25V
5Ω VINSNS BOOST1 MTOPA 25V
MTOPD
×2
VIN 0.22µF
15µH
0.1µF DRVCC SW1
10µF
TG1
121k BG1 MBOTB MBOTC
VINOV
1.21k 110k
100Ω
SENSEP
BVIN 220pF R1
10mΩ
1µF BOV SENSEN
SGND 100Ω
BRUN LTC3777
PGND
BVOUT 150µH
3.3V BSW
BG2
85mA 22µF 2.5M
6.3V BVFB BOOST2
800k BGND 0.22µF
SW2
VOUT TG2
EXTVCC 100Ω
D1, D2: DFLS1200-7 1µF IAVGSNSP
MTOPA: BSC360N15NS3 G
MBOTB: BSC190N15NS3 G 4.7µF 100Ω
MTOPD: BSC050NE2LS 10k IAVGSNSN
MBOTC: BSC050NE2LS VIN RUN 1k
VOUTSNS
For more information www.analog.com

PGOOD
VFB
3777 F18
100k ITH
PINS NOT USED IN THIS V5 12.1k
CIRCUIT: BFBO, BISET, DRVSET 3.32k
2.2µF 100pF
SS
33nF
FREQ
0.1µF
56.2k
MODE
PLLIN
Figure 18. 97% Efficient 12V/5A Output Buck-Boost Converter with an Independent Always on 3.3V/ 85mA Output Switching Bias Supply
37
Rev A
LTC3777
LTC3777
PACKAGE DESCRIPTION
LXE Package
48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)
(Reference LTC DWG #05-08-1832 Rev D)
7.15 – 7.25
5.50 REF
48 37
1 36
0.50 BSC
C0.30
5.50 REF
7.15 – 7.25
0.20 – 0.30
3.60 ±0.05
3.60 ±0.05
e3
XXYY
Q_ _ _ _ _ _
12 25
LTCXXXX
PACKAGE OUTLINE
13 24
LX-ES
COMPONENT
PIN “A1”
1.30 MIN
TRAY PIN 1
RECOMMENDED SOLDER PAD LAYOUT BEVEL
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PACKAGE IN TRAY LOADING ORIENTATION
9.00 BSC
7.00 BSC 3.60 ±0.10
48 37 37 48
SEE NOTE: 3
1 36 36 1
C0.30
9.00 BSC
7.00 BSC
3.60 ±0.10
A A
12 25 25 12
C0.30 – 0.50
13 24 24 13
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
1.60
11° – 13° 1.35 – 1.45 MAX
R0.08 – 0.20 GAUGE PLANE
0.25
0° – 7°
LXE48 LQFP 0416 REV D

11° – 13°
0.50
0.09 – 0.20 0.17 – 0.27 0.05 – 0.15
1.00 REF BSC
SIDE VIEW
0.45 – 0.75
SECTION A – A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS 3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH 4. DRAWING IS NOT TO SCALE
SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND ON ANY
SIDE OF EXPOSED PAD, MAX 0.50mm (20 MILS) AT CORNER OF EXPOSED
PAD, IF PRESENT
Rev A

LTC3777
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 10/18 Changed Electrical Characteristics from VIN to BVIN 5
Added references to Note 9 5
Clarified PB,BUCK and PC,BOOST functions 25
Rev A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
For
subject to change without notice. No license is morebyinformation
granted implication orwww.analog.com
otherwise under any patent or patent rights of Analog Devices. 39
LTC3777
TYPICAL APPLICATION
VIN
16V TO 120V D2
10µF 1µF
×2 ×5 D1
125V 200V
1k VOUT
4mΩ
VINSNS 48V
5Ω
VIN 10µF 10A
0.1µF DRVCC ×3
50V 56µF
10µF MTOPA 63V
BOOST1 M TOPD
×2
133k
VINOV 15µH
LTC3777 0.22µF
1.21k
SW1
TG1
BVIN BG1 M BOTB M BOTC
1µF
BRUN 100Ω
BOV SENSEP
SENSEN R1
220pF 4mΩ
BVOUT 220µH 475k
SGND
12V BSW 100Ω
85mA 22µF 715k PGND
×2 BVFB
25V BG2
51.1k BGND
BOOST2
0.22µF
EXTVCC
SW2
1µF
TG2
10k
RUN IAVGSNSP
D1, D2: DFLS1200-7 4.7µF 100Ω 100Ω
PGOOD
MTOPA: BSC110N15NS5 IAVGSNSN
MBOTB: BSC093N15NS5 100k 1k
MTOPD: BSC028N06NS V5 VOUTSNS
MBOTC: BSC066N06NS VFB
2.2µF
SS ITH
12.1k
PINS NOT USED IN THIS FREQ 10k
CIRCUIT: BFBO, BISET, DRVSET 0.1µF 56.2k 100pF
MODE 10nF
PLLIN
3777 TA02
Figure 19. 99% Efficient 480W, 48V Output Buck-Boost Converter with Integrated Switching Bias Supply
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LT®8705A 80V VIN and VOUT Synchronous 4-Switch Buck-Boost 2.8V ≤ VIN ≤ 80V, Input and Output Current Monitor, 5mm × 7mm QFN-38
DC/DC Controller and TSSOP-38
LTC7813 60V Low IQ Synchronous Boost+Buck Controller Low EMI 4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, Boost VOUT Up to 60V,
and Low Input/Output Ripple 0.8V ≤ Buck VOUT ≤ 60V, IQ = 29µA, 5mm × 5mm QFN-32
LTC3899 60V, Triple Output, Buck/Buck/Boost Synchronous 4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, Buck VOUT
Controller with 29µA Burst Mode IQ Range: 0.8V to 60V, Boost VOUT Up to 60V
LTM®8056 58V Buck-Boost μModule Regulator, Adjustable Input and 5V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V 15mm × 15mm × 4.92mm BGA Package
Output Current Limiting
LTC3895/ 150V Low IQ, Synchronous Step-Down DC/DC Controller 4V ≤ VIN ≤ 140V, 150V Absolute Maximum, PLL Fixed Frequency 50kHz to
LTC7801 with 100% Duty Cycle 900kHz, 0.8V ≤ VOUT ≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 40µA
LTC3871 Bidirectional Multiphase DC/DC Synchronous Buck or VIN/VOUT Up to 100V, Ideal for High Power 48V/12V Automotive Battery
Boost On-Demand Controller Applications
LTC3638 140V High Efficiency 250mA Step-Down Regulator Integrated Power MOSFETs, 4V ≤ VIN ≤ 140V, 0.8V ≤ VOUT ≤ VIN, IQ = 12µA,
MSOP-16(12)
LTC7103 105V, 2.3A Low EMI Synchronous Step-Down Regulator 4.4V ≤ VIN ≤ 105V, 1V ≤ VOUT ≤ VIN, IQ = 2µA Fixed Frequency 200kHz to
2MHz, 5mm × 6mm QFN
Rev A
40
10/18
www.analog.com
For more information www.analog.com  ANALOG DEVICES, INC. 2018

LTC 3777

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LTC3777

150V VIN and VOUT Synchronous

1µF BOV SGND 96 18

2.2µF 100k VFB

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POWER LOSS (W)

POWER LOSS (W)

ILOAD ILOAD ILOAD

VOUT VOUT VOUT

3777 G03 3777 G04 3777 G05

ILOAD ILOAD ILOAD

VOUT VOUT VOUT

3777 G06 3777 G07 3777 G08

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SW1 SW1 SW1

Pulse-Skipping Mode Forced Continuous Mode Pulse-Skipping Mode

SW1 SW1 SW1

Start-Up from RUN

VOUT VOUT VOUT

3777 G15 3777 G16 3777 G17

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Shutdown from RUN Shutdown from RUN

SW2 SW2 ITH

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CURRENT LIMIT (SENSEP – SENSEN) (mV)

CURRENT LIMIT (SENSEP – SENSEN) (mV)

SW2 100 100

CURRENT LIMIT (SENSEP – SENSEN) (mV)

FEEDBACK VOLTAGE (mV)

–100 –150 1180

Undervoltage Lockout Threshold V5 Low Dropout Regulation

V5 LDO VOLTAGE (V)

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SWITCHING FREQUENCY (kHz)

DRVSET = 3/4 • V5, VIN = 10V

7 DRVSET = 1/4 • V5, VIN = 8V 19.8

Input Supply Current Soft-Start Pull-Up Current

SS PULL–UP CURRENT (µA)

RUN THRESHOLD (V)

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BRUN OR BOV THRESHOLD VOLTAGE (V)

BVFB THRESHOLD VOLTAGE (V)

Quiescent Supply Current Quiescent Supply Current

BVIN SUPPLY CURRENT (µA)

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driven to a voltage above 4V. TG1 A D TG2

the LTC3777 regulates the VFB voltage to the SS voltage

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SWITCH A Figure 5 shows typical boost region waveforms. If VIN

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ILOAD(MAX) • RSENSE (mV)