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CA-1 [EN-115]

CIRCUIT ANALYSIS I
[EN-115]
COURSE INSTRUCTOR:
DR BILAL ASLAM
ASSISTANT PROFESSOR, ELECTRONICS
ENGINEERING DEPARTMENT, UET TAXILA
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SUMMARY OF NODAL ANALYSIS PROCEDURE

 Count the number of nodes (N)


 Designate a reference node.
 Analysis is simplified if node with greatest number of connected
branches is selected as reference.

 Label the N-1 nodal voltages.

 Write a KCL equation for each of the non-reference nodes.


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SUMMARY OF NODAL ANALYSIS PROCEDURE

 Express any additional unknowns such as currents or voltages


other than nodal voltages in terms of appropriate nodal voltages.
 Organize the equations.

 Solve the system of equations for the N-1 nodal voltages.


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NODAL ANALYSIS WITH VOLTAGE SOURCE
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BETWEEN REFERENCE AND NON-REFERENCE NODES

 Simply set the voltage at the non-reference node equal to the


voltage of the voltage source.
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BETWEEN TWO NON-REFERENCE NODES

How to handle the 6 V source?


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SUPER NODE (1)

 A supernode is formed by enclosing a (dependent or


independent) voltage source connected between two non-
reference nodes and any elements connected in parallel with it.

Note: We analyze a circuit with supernodes using the


same three steps except that the supernodes are treated
differently
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SUPER NODE (2)

 Basic Steps
 Take off all voltage sources at supernodes and apply KCL to
supernodes
 Put voltage sources back to the nodes and apply KVL to
relative loops
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SUMMARY OF SUPERNODAL ANALYSIS PROCEDURE

 Count the number of nodes (N).


 Designate a reference node.
 Label the nodal voltages (there are N - 1 of them).
 If the circuit contains voltage sources, form a supernode
about each one.
 This is done by enclosing the source, its two terminals, and any other
elements connected between the two terminals
within a broken-line enclosure.
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SUMMARY OF SUPERNODAL ANALYSIS PROCEDURE

 Write a KCL equation for each non-reference node and for each
supernode that does not contain the reference node.
 Relate the voltage across each voltage source to nodal
voltages.
 This is accomplished by simple application of KVL; one such
equation is needed for each supernode defined.

 Express any additional unknowns such as currents or voltages


other than nodal voltages in terms of appropriate nodal voltages.
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SUMMARY OF SUPERNODAL ANALYSIS PROCEDURE

 Organize the equations.


 Solve the system of equations for the N-1 nodal voltages.
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EXAMPLE 1

 Find v and i in the circuit of Fig. below


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KCL at Suernode
13 𝐼 = 𝑖1 + 𝑖 + 𝑖2
14 − 𝑣 𝑣 𝑣1 𝑣1
= + +
4 3 2 6
7𝑣 + 8𝑣1 = 42 1

KVL at Suernode
−𝑣 + 6 + 𝑣1 = 0
𝑣1 = 𝑣 + 6 2

From [1] and [2]


𝑣 = −0.4 V
𝑣1 = 5.6 V 𝑖 = 2.8 A
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EXAMPLE 2

 Find v1, v2, and v3 in the circuit of Fig. below using nodal analysis.
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KCL at Supernode
𝑖 + 𝑖2 + 𝑖3 = 0
𝑣1 𝑣2 𝑣3
+ + =0
2 4 3
6𝑣1 + 3𝑣2 + 4𝑣3 = 0 [1]
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16 KVL at Loop 1
−𝑣1 + 25 + 𝑣2 = 0
−𝑣1 + 𝑣2 = −25 [2]
KVL at Loop 2
−𝑣2 − 5𝑖 + 𝑣3 = 0
−5𝑣1 − 2𝑣2 + 2𝑣3 = 0 [3]

𝛥1
𝑣1 = = 7.608 V
𝛥
𝛥2
𝑣2 = = −17.39 V
𝛥
𝛥3
𝑣3 = = 1.63 V
𝛥
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EXAMPLE 3

 Determine the voltage labelled v in the circuit of Fig. below.


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MESH ANALYSIS

 Powerful methodological approach for circuit analysis based on


KVL.
 Strictly speaking applicable to planar circuits.

 If it is possible to draw the diagram of a circuit on a plane surface


in such a way that no branch passes over or under any other
branch, then that circuit is said to be a planar circuit.
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A planar circuit with The same circuit redrawn


crossing branches with no crossing branches
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A nonplanar circuit.
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MESH ANALYSIS

 Mesh analysis provides another general procedure for analyzing


circuits, using mesh currents as the circuit variables.
 A loop is a closed path with no node passed more than once. A
mesh is a loop that does not contain any other loop within it.

A circuit with two meshes.


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MESH ANALYSIS

 Steps to determine mesh currents:


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CA-1 [EN-115]

25 EXAMPLE 4: CIRCUIT WITH INDEPENDENT VOLTAGE


SOURCE

 Calculate the mesh currents i1 and i2 of the circuit of Fig. below


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CA-1 [EN-115]

27 EXAMPLE 5: CIRCUIT WITH DEPENDENT VOLTAGE


SOURCE

 Using mesh analysis, find Io in the circuit of Fig. below


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