Electronic Circuits Experiment Department of Electrical Engineering

National Taiwan University

Laboratory Exercise 2

Introduction to Verilog/Testbench
I. Objectives
Verilog is a hardware description language that describes the behavior of circuits. In this
laboratory, we are aimed to introduce Verilog and give some examples as exercise.

II. Experiment Equipment

Equipment Quantity
Computer 1
USB with Vivado program 1
USB cable 1
EGO1 1

III. Introduction to Function

In this laboratory, we will implement a 4-bits ripple carry adder as exercise.
Function: Sum = a + b

sum ab

overflow

a (sw[7:4]) b (sw[3:0]) sel

1
 Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University

IV. Lab Work

Previous steps can be referenced by Lab1
Step0: Hardware Mode Setting
1. Use a USB cable to connect FPGA with your computer.
2. Turn on the power

Step1: Start Vivado & Create Project

1. Insert the USB we provide into your computer
2. Find the program in “F Disk/Vivado/2017.4/bin/vivado.bat”
3. Click twice to open Vivado
4. Create Project
5. Click Next

Step2: Enter project name and location

1. The Project location is set at will
2. Click Next

2
Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 3: Search xc7a35tlcsg324-2L
1. Click “Next” three times
2. Search “xc7a35tlcsg324-2L”
3. Click “Next” and “Finish”

Step 4: Copy Constraint and Source files to your project location.

Step 5: PROJECT MANAGER, Add Source

1. In this step, you will add your source file(.v) to Vivado
2. Click “Add Sources” under Project Manager

3
Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
3. Select “Add or create design sources” → “Next” → “ADD Files” → “Source”
→ ”dont touch” → “Seg_7_Display.v” and ” lib.v” → “OK”
4. “ADD Files” → “Source” → “FA.v” and ” adder4.v” → “OK” → “Finish”

2
3

Step 6: PROJECT MANAGER, Add Constraint File

1. In this step, you will add your constraint file(.xdc) to Vivado. Constraint files can
bridge your design to the I/O interface of FPGA
2. Click “Add Sources” under Project Manager
3. Select “Add or create constraints” → “Next” → “ADD Files” → “Constraint” →
..Select “EGO1.xdc” → “OK” → “Finish”.

4
 Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 7: PROJECT MANAGER, Add Simulation Source
1. In this step, you will add your simulation testbench file(.v) to Vivado. Simulation
Testbench files can test the correctness of your design
2. Click “Add Sources” under Project Manager
3. Select “Add or create simulation sources” → “Next” → “ADD Files” → “Source” →
.. → “dont touch”→ Select “tb_FA.v” → “OK” → “Finish”.

5
Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 8: Complete full adder.v (you only can use logic gates in lib.v)
1. Select “Hierarchy” under Sources -> “Design Sources” -> “f0:FA” under adder4
2. Complete FA.v by using verilog in gate-level
Reference your exercise C2. Just use logic gates to implement 1-bit full adder

Step 9: Use testbench to check your design

1. Select “Hierarchy” under Sources -> “Simulation Sources” -> “sim_1”
2. Right click “tb_FA” -> Choose “Set as Top”

6
Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
3. Click “Run Simulation” under SIMULATION -> Run Behavioral Simulation
(Some antivirus softwares will block this operation. If so, shut down the software)

4. Select “Untitled 1” to see waveform. You can press “zoom fit” to see the whole
waveform
5. If correct signal is 1, it means your design is correct. Then you can go to the next step;
otherwise, you have to modify your “FA.v”

zoom fit

7
Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 10: Complete 4-bit ripple carry adder
1. Select “Hierarchy” under Sources -> “Design Sources”
2. Right click “adder4.v” -> Select “Set as Top” (If adder4.v is already a Top design, you
don’t need to do this)

3. Complete “adder4.v”. Connect four 1-bit full adders to implement a 4-bits full adder

8
Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 11: Generate Bitstream
1. Click “Generate Bitstream” under PROGRAM AND DEBUG. This includes synthesis
and implementation.
2. Click “Yes” and “OK”. Wait for Vivado running Design Flow (It may take some time).

3. If design flow is completed, the status of Synthesis and Implementation will show
“Complete” , and then it will pops out “Bitstram Generation Completed” window
(You can ignore all warnings in this step)
4. Select “Open Hardware Manager”, and then press “OK”.

9
Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
Step 12: Program into FPGA
1. Press “Open Target”, and select “open new target”

2. Click “Next” twice

3. Find your FPGA device, and select “xc7a35t”. Click “Next” and “Finish”

10
Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University
4. Click “Program device”
5. Find your bit file. If no files, please find [Project_name].runs/impl_1/adder4.bit

6. Press “Program”.

Step 13: Test your design!

11
 Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University

V. Digital Logic Exercises

A. Full Adder
In this laboratory, a full adder (FA) module will be used. FA has three inputs and two
outputs. It computes the addition operation of binary numbers.

a b cinc cout
carry sum
sum 0 0 0 0 0
0 0 1 0 1
0 1 0 0 1

FA
0 1 1 1 0
cout cin 1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
a b

B. 4-bits ripple carry adder

By Concatenating one-bit adders, we can make an adder to add an arbitrary length binary
number. In this laboratory, we implement a four-bits ripple carry adder by four one-bit FAs.

C. Please finish a 4-bit adder with your own full adder:

P1.Boolean exrpession of FA
Please write down the boolean expression of Boolean algebras from the truth table
listed above.
Hint: K-map
Ans:
cout =

sum =

12
Electronic Circuits Experiment Department of Electrical Engineering
National Taiwan University

P2.Circuit diagram of FA
Use logic gates to draw a circuit that implements the function of the Boolean algebra you
write in problem 1. (Note: you can only use logic gates in lib.v )
Ans:

P3.Implement a one-bit FA
Implement a one-bit full adder in Verilog. (Finish Step 8 and paste your code in your
report)
P4.Plot waveform of your design
Use testbench and vivado to check the waveform of your design. (You can take a photo
in Step 9 to prove your design is correct!)
Ans:

P5.Implement a 4-bit ripple carry adder

Implement a 4-bit ripple carry adder by four one-bit FAs. (Finish Step 10 and paste
your code in your report)
P6.If you finish all the steps, please let TA check your result.

13