ISSCC 2023 / SESSION 8 / GHz-TO-MILLIMETER WAVE FREQUENCY GENERATION / 8.
1
8.1 An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset
Dual-Core Enhanced Class-F VCO with Common-Mode-Noise
Self-Cancellation and Isolation Technique
Qixiu Wu, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang,
Baoyong Chi
Tsinghua University, Beijing, China
The current 5G and future 6G high-speed mobile-Internet era puts forward stricter
requirements on the power consumption, silicon area, and phase noise specifications
for local oscillators (LOs) in mobile and portable devices, especially in battery-powered
mobile phones, notebook computers, and unmanned aerial vehicles (UAVs) used for
mobile base stations. Over the past few decades, intensive research to improve the power
efficiency of RF and millimeter-wave oscillators while maintaining required phase-noise
characteristic has been carried out. As represented in Fig. 8.1.1, the authors in [1]
reported a BiCMOS series-resonance VCO with the lowest phase noise among silicon-
based oscillators identified in [1] at the cost of high power consumption (600mW), which
is not feasible for energy-efficient applications. In addition to the series resonance
2023 IEEE International Solid- State Circuits Conference (ISSCC) | 978-1-6654-9016-0/23/$31.00 ©2023 IEEE | DOI: 10.1109/ISSCC42615.2023.10067672
technique, the commonly used method to reduce the phase noise is to introduce a high
resistance at the second harmonic frequency. However, the head filter in [2] that
generates the high resistance occupies additional area and cannot prevent noise current
injection at the GND. Although separate filters are added at the VDD and GND, as reported
in [3], the noise current passing through the head common-mode inductance is coupled
in the same phase to the noise current of the bottom inductance, which increases the
total injected noise to some extent. To solve the problem of the additional area for the
common-mode resonator, the authors in [4] merged the common-mode filter with the
differential-mode resonator at the cost of the reduced switching speed of the gate and
worsened phase noise and the ability to cut off the noise-injection path from the VDD
coupled to the gate. In order to overcome the above-mentioned issues, a 11.5-to-
14.3GHz dual-core Class-F VCO with common-mode-noise self-cancellation and isolation
technique is proposed in this paper. Without occupying additional area, the injection
noise of the VDD and the GND is cancelled inherently at the same time, and the noise
path from the drain to gate is isolated. The measurement results indicate that the
proposed common-mode-noise self-cancellation and isolation VCO achieves
-119.2dBc/Hz phase noise at 1MHz offset from a carrier of 11.8GHz, which translates to
an FoM of 192.8dBc/Hz. The reported FoM is competitive among VCOs operating in a
nearby frequency range.
As shown in Fig. 8.1.2, the head-to-tail-coupling common-mode-noise self-cancelling
technique is proposed to improve the impedance from the power/ground node to the
VCO. By adding the common-mode coupling between LD and the tail inductor LS, the
direction of the noise current generated at LD after coupling is opposite to that injected
by the ground node, which reduces the total noise current injected into the VCO,
equivalent to an increased impedance. Calculations and simulation results show that the
impedance after adding the common-mode coupling is increased by 2dB compared with
the traditional discrete head/tail LC-tank filter structure. Moreover, the inductor LD is
multiplexed as the head filter and the differential mode resonant inductor, which reduces
the silicon area. The common-mode-noise isolation transformer is proposed to further
eliminate the path of the VDD noise injected to the gate via feedback. The gate coil LG is
split into 4 sections, each section is alternately coupled with the positive and negative
half circles of the drain coil LD, the differential-mode current can be coupled and output
normally. The common-mode induced current is in the opposite direction in the half coil
of LG, and the total current is 0, which eliminates the common-mode coupling from LD
to LG and cuts off the noise injection path from the VDD to the gate. The gate coil LG is
constructed as an even-numbered circle structure, and the noise injected by VDD is
inversely phased in the noise-coupling current of the adjacent circle, resulting in a self-
cancelling and isolating effect. The EM simulation results show kDG,comm<0.001 at 2×f0.
On this basis, a Class-F VCO based on the common-mode-noise cancellation and
isolation technique is proposed. The simulation results show that the load impedance
from the drain has fundamental and third-order peaks, and the load impedance from the
gate has a fundamental peak. The transient simulation results show that the source node
has a second-order harmonic component of 20mV, and the peak-to-peak value of the
gate is 1.75V with drain-to-gate voltage gain of 6.4dB, which is beneficial to further
reduce the phase noise in a Class-F manner.
To fold the tail filter below the differential-mode resonator to achieve kDS,comm and to
further reduce the area without the loss of the differential-mode Q-factor (i.e., phase
noise), the dual-core coupling structure is utilized. As shown in Fig. 8.1.3, by constructing
a dual-core coupled-VCO structure, the drain inductor LD forms a parallel figure-8 coil in
the differential-mode, and the tail inductors of the two cores can be combined into a
closed coil. The total magnetic flux passing through the closed coil is zero ideally when
the resonator works in the differential mode, achieving the decoupling of the two coils.
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146 • 2023 IEEE International Solid-State Circuits Conference
Meanwhile, the magnetic fields of the two parallel half-turns strengthen each other,
improving the quality factor and phase-noise performance. In the common mode, the
noise current injected from the power-supply node flows to the transistor through LD,
and then from the source to the ground through LS. The two currents generate opposite
magnetic fluxes, reducing the equivalent noise current injected into the VCO. The EM
simulation results show QLD=16.8 boosted by 34% at f0. The LD/LG is 288/530pH,
respectively.
For VCOs, there is room for optimization in the active transistor layout. For the RF
transistor of the PDK model, the top layer of the gate is connected to only one circle of
M3 metal, and there are few through vias connected to the poly, resulting in a large
parasitic resistance. In a custom transistor layout, a stack structure is used, whereby
the poly of the S-shaped trace is directly connected and M1/M2 traces are laid on the
top of the poly. The vias are placed regularly and the most compact DRC is used, so that
the total number of vias from M3 to poly can be increased by 100%. The parasitic RGate
is halved, and the introduced parasitic capacitance is approximately negligible. To reduce
source parasitic resistance, the vias are treated in the same way and increased by 50%.
Simulations show that after increasing the number of vias, the phase noise introduced
by RGate is negligible.
The proposed common-mode-noise self-cancellation and isolation VCO was designed
and fabricated in a 65nm CMOS technology. Figure 8.1.7 shows the die micrograph. The
core area is 0.065mm2 excluding the output buffers and pads. The phase noise of the
VCO is measured using an R&S phase noise analyzer FSWP50. Figure 8.1.4 shows the
measured phase noise is -119.2/-117.1dBc/Hz at a 1MHz frequency offset from the
carrier of 11.53/12.63GHz, respectively. Figure 8.1.5 shows the phase noise and FoM
variation within the tuning range. The peak FoM of 192.8dBc/Hz is achieved at 11.8GHz
with a 4dB range. The measured phase noise at a 1MHz offset frequency varies from
-119.2 to -115.7dBc/Hz. The measured frequency-tuning range is 21.7%, which ranges
from 11.5 to 14.3GHz. The oscillator consumes 5.6-to-10mW depending on the output
frequencies.
Figure 8.1.6 shows the comparison with other VCOs operating between 10 and 18GHz.
Thanks to the proposed common-mode-noise self-cancellation and isolation technique,
the peak FoM and FoMA/T surpass other works in Fig. 8.1.6 while achieving the smallest
power consumption and improving the phase-noise performance, showing the superior
3D comprehensive optimization of phase noise, power consumption, and area. This VCO
can meet the needs of mobile communication terminals that require compact, low-power,
low-phase-noise VCOs.
Acknowledgement:
This work was partly supported by the National Key R&D Program of China
(No.2020YFB1805004), the Tsinghua-Samsung Joint Research Project, and Beijing
Advanced Innovation Center for Integrated Circuits.
References:
[1] A. Franceschin et al., “Series-Resonance BiCMOS VCO with Phase Noise of
-138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM,” ISSCC, pp. 1-2, Feb.
2022.
[2] H. Guo et al., “A 5.0-to-6.36GHz Wide-band-Harmonic-Shaping VCO Achieving
196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f3 PN Corner Without Harmonic Tuning,”
ISSCC, pp. 294-295, Feb. 2021.
[3] M. Garampazzi et al., “Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-
B Oscillator with Transformer-Based Tail Filtering,” IEEE JSSC, vol. 50, no. 7, pp.
1657-1668, July 2015.
[4] D. Murphy et al., “Implicit Common-Mode Resonance in LC Oscillators,” IEEE JSSC,
vol. 52, no. 3, pp. 812-821, Mar. 2017.
[5] F. Padovan et al., “A Quad-Core 15GHz BiCMOS VCO with −124dBc/Hz Phase Noise
at 1MHz Offset, −189dBc/Hz FOM, and Robust to Multimode Concurrent Oscillations,”
ISSCC, pp. 376-377, Feb. 2018.
[6] S. Veni et al., “Analysis and Design of a 17-GHz All-NPN Push-Pull Class-C VCO,”
IEEE JSSC, vol. 55, no. 9, pp. 2345-2355, Sept. 2020.
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 ISSCC 2023 / February 21, 2023 / 8:30 AM

Figure 8.1.1: Comparison of area, power consumption, and phase noise between Figure 8.1.2: Conceptual diagram of the proposed common-mode-noise cancellation
previous arts and this work. and isolation scheme

Figure 8.1.3: Detailed circuit schematic of the proposed VCO. Figure 8.1.4: Measured phase noise at 11.53 and 12.63GHz.

Figure 8.1.5: Measured phase noise, FoM, frequency-tuning range, and spectrum. Figure 8.1.6: Performance comparison table.
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Figure 8.1.7: Die micrograph.

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• 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE