Micron Confidential

MOBILE +91-9908351435
Shiva Kumar Masalthi
Citizenship: INDIAN DOB: 08-03-1992 Gender: Male EMAIL shivagkumar005@gmail.com

Profile:
• Competent and aspirational professional with ~6.5 years’ experience in verification.
• Key competences: Skilled in test bench architecture plan, development, and verification sign-off.
• Career objective: Dedicated professional who wants to meet the challenges posed platform, to develop
knowledge and skills and to do best with self-satisfaction.

Educational Qualifications:
Grade School / College Board / University Duration % / CGPA
10th Zilla Parishad High School, APSSC 2006-2007 78.5 %
Kunsi.
Diploma Government Polytechnic SBTET-AP 2007-2010 71.65 %
(EEE) college, Mahabubnagar
B. Tech Vidyajyothi Institute of Jawaharlal Nehru Technological 2010-2013 83.20 %
(EEE) Technology University, Hyderabad, AP

M. Tech Manipal Institute of Manipal University 2014-2016 7.71

(Digital Technology CGPA
Electronics &
Comm.)

Industry Work Experience:

6 years 5 months (5 years 5 months + 1-year Internship).

(From June 2019)

• Senior Design Verification Engineer at Micron Technology, Inc., Hyderabad.

(July 2016- June 2019)

• Design Verification Engineer at HYSOC Technologies, Hyderabad.
o (March 2017 - June 2019): Contractor at Xilinx India, Hyderabad.
o (July 2016 - March 2017): Contractor at Redpine Signals Inc., Hyderabad.

(July 2015 – June 2016)

• Design Verification Intern at CVC Private Limited, Bangalore.

Skill Sets
Languages HDL Verilog, SystemVerilog
HVL SystemVerilog, SystemVerilog Assertions, C, Perl Script.
Methodology UVM.
Synopsys VCS & Verdi, Riviera-Pro, Cadence JasperGold, QuestaSim 10.0, Xilinx ISE,
Tools
Microwind.
Operating System Windows and Linux

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Professional Skills:
• Hands on experience in test bench architecture planning, development, and verification sign-off with
100% coverage metrics.
• Hands on delivering efficient block verification at IP level.
• Involved in SoC/Subsystem level verification.
• Hands on experience in AMBA (AXI, AHB and APB) protocols.
• Hands on experience in testbench development using UVM methodology.

Projects Handled:
• Verification of LBAT IP:
o LBAT converts logical address into physical address. Supports Single and Two-level memory access to get the
physical address. It has buffer cache to reduce read access on DRAM lines.
o It supports multiple features like write, read, conditional write, lock and unlock.
o Added setup for testcases development.
o Planned and added scoreboard.

• MIM Master and Slave VIP development:

o MIM is a Microns internal protocol, it provides high throughput and high-speed transfers.
o Developed both master, slave agents plan and test bench architecture plan.
o Developed everything from scratch.
o Verified both VIPs by connecting in loop-back.
o Guided team members on assertions, coverage, and APIs developments for master VIP.

• Nand Flash Controller (NFC) Sub-system PHY IF Verification:

o Verified PHY Interface block which will communicate with processor, DMA and PHY block and
checking the data/timing integrity between ONFI and PHY-IF block register configuration.

• Axi2SMEM IP verification:
o AXI2SMEM is a bridge between axi interface and memory.
o Developed verification and test bench architecture plans.
o Developed single test bench to support for 4 different design (RTL) flavors.
o Developed everything from scratch, APIs, tests, scoreboard, assertion checks and coverage.

• GenQ IP verification:
o GenQ is a communicating medium between two blocks to drive/receive massage without another
block’s permission. Driving side, it reduces the time to wait for source/destination massage block
driving response and receiving side reduces polling time between the chunk data in a full massage.
o Developed verification plan.
o Developed single test bench to support for 4 different design (RTL) flavors along with APIs,
Checkers.
o Guided team member on tests and coverage developments.

• Verification of Slave Boot Interface (SBI).

o SBI module allows the external masters to send data based on boot mode pin selection in fact data
contains the boot header and boot image. Processor is responsible for executing the firmware
instructions and checking data availability in the SBI followed by enables DMA to load data into
memories.

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• Verification of Interrupt Controller.
o Verified a set of interrupts available in the PMC sub-system.

Achievements
• Recognized and received bravo points 3 times in Micron.
• Recognized and received spot award for client project delivery at HySoC Technologies.
• Qualified in OCES/DGFS-2013 exam conducted by Bhabha Atomic Research Centre (BARC).
• GATE-2014 QUALIFIED with 94.56 percentile.
• Secured College 5th rank (EEE Department) and along with 1st rank in 2-1 and 3-1 Semesters of B.Tech.
• Secured mandal Third rank in SSC exams.

The above information provided by me is true and have all the relevant documents to authenticate the same.
M Shiva Kumar

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