1034
7, JULY 2000
Brief Papers_______________________________________________________________________________
A 2-GHz Low-Phase-Noise Integrated LC-VCO Set with Flicker-Noise
Upconversion Minimization
Bram De Muer, M. Borremans, M. Steyaert, and G. Li Puma
Abstract—A fully integrated 2-GHz very low-phase-noise
LC-tank voltage-controlled oscillator (VCO) set with flicker noise
upconversion minimization is presented. Using only integrated
planar inductors, the measured phase noise is as low as 125.1
dBc/Hz at 600-kHz offset and 138 dBc/Hz at 3 MHz. The
excellent phase-noise performance is achieved by means of an
in-house-developed integrated inductor simulator-optimizer.
To minimize the upconversion of flicker noise to 1/ 3 phase
noise, a flicker-noise upconversion factor is defined, which can
easily be extracted from circuit simulation. The technique is
applied to demonstrate the relationship between the flicker-noise
upconversion and the overdrive level of the oscillators’ MOS
cross-coupled pair and to develop circuit balancing techniques
to even further reduce the flicker-noise upconversion. The 1/ 3
phase-noise corner is minimized to be less than 15 kHz. The
VCO’s are implemented in a three-metal layer, 0.65- m BiCMOS
process, using only MOS active devices.
Index Terms—Analog integrated circuits, flicker-noise upcon-
version, phase noise, voltage controlled oscillators.
I. INTRODUCTION
T HE explosive growth of today’s telecommunication
market has brought an increasing demand for high-per-
formance radio-frequency circuits in low-cost technologies.
A major challenge in the design of single-chip transceiver
systems is the design of the voltage-controlled oscillator (VCO)
that generates the local oscillator (LO) carrier signal. The
phase noise of the VCO is one of the most critical parameters
for the quality and reliability of the information transfer. To
achieve the low-phase-noise specifications, integrated passive
LC-VCO’s tend to be the best choice. The design of a passive
LC-VCO relies on the integration of a high-quality LC-tank [1].
The 1 -shaped part of the phase-noise spectrum is mainly
upconverted white noise generated by the tank’s parasitic
resistance.
In addition, flicker noise is upconverted to 1 -shaped phase
noise close to the carrier [2]. When the oscillator is not carefully
designed, flicker noise can deteriorate the phase noise at higher
offset frequencies important for communication systems, e.g.,
600 kHz, by several decibels. This is especially true in MOS
Manuscript received November 16, 1999; revised January 24, 2000.
B. De Muer, M. Borremans, and M. Steyaert are with the Department Elek-
trotechniek, Katholieke Universiteit Leuven, Heverlee B-3001 Belgium.
G. Li Puma is with the Infineon Technologies AG, Düsseldorf 740489 Ger-
many.
Publisher Item Identifier S 0018-9200(00)03870-1.
0018–9200/00$10.00 © 2000 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO.
VCO’s because of the higher flicker noise of MOS transistors
compared to bipolar transistors.
II. INTEGRATED SPIRAL INDUCTOR
The key to the design of low-phase-noise LC-oscillators is
the design of a high-quality inductor. This is reflected in the
equations for the phase noise and the power consumption [1]
(1)
and
(2)
where is the single-sideband spectral noise density
at an offset from the oscillation frequency is the
transconductance calculated from the Barkhausen criterion, is
a term that includes the excess noise of the oscillator’s negative
resistance, is the differential output amplitude, and
the LC-tank’s effective resistance, which is mainly determined
is
by the inductor. As shown in (1) and (2), the inductor’s series
resistance must be low so as to lower the phase noise as well as
the power consumption.
For mass production, fully integrated spiral inductors on sil-
icon substrates without extra postprocessing steps are required.
The quality of these inductors is limited by the parasitic effects,
such as skin effect, eddy currents in the substrate, etc. A com-
plete electromagnetic simulation has to be performed to accu-
rately model all the parasitic losses. Many planar inductor sim-
ulation tools and their results can be found in the literature [3],
[4]. Due to the long simulation times or the limited accuracy of
most of these tools, performing an accurate optimization is out
of the question. To be able to find an optimal inductor design,
a simulator-optimizer for planar inductors on silicon substrates
has been developed [5]. The fast three-dimensional inductance
extraction program FastHenry [6] is implemented in a very fast
simulated reannealing [7] loop. The full simulation-optimiza-
tion process takes from a few hours to one night, depending on
the desired accuracy. The result is an optimal coil geometry pa-
rameter set for a given technology, VCO circuit, and phase-noise
specification.
The simulator-optimizer has been used to find an optimal
inductor solution for a low-phase-noise specification. Based on
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000 1035

TABLE I
PARAMETERS OF THE INTEGRATED INDUCTOR

the simulations, a three-terminal balanced octagonal inductor is

implemented in a 0.65- m BiCMOS process. The technology’s
substrate resistivity is 8 cm, which is moderate compared to
most modern deep submicrometer CMOS technologies. The
three available metal layers are laid out in parallel to minimize
the dc series resistance. The inductor parameters, which are
obtained from optimization, are listed in Table I. In the model,
the shunt capacitance of the inductor (dashed) is omitted
because it is negligible for balanced inductors.

III. FLICKER-NOISE UPCONVERSION

A. Flicker-Noise Upconversion Mechanism
Compared to bipolar transistors, MOS transistors generate
more flicker noise. In oscillators, flicker noise is upconverted
to 1 phase noise. Consequently, the 1 phase noise will
be much higher in MOS oscillators than in bipolar oscillators
and becomes an effect that has to be taken into account. The
1 phase noise corner does not coincide with the flicker-noise
corner of the technology but depends on the quality of the de-
sign.
The mechanism of flicker-noise upconversion can be ex- Fig. 1. Circuit schematic of (a) VC01 and (b) VC02.
plained as follows. Flicker noise from the tail current source
that enters the LC-tank will be upconverted due to the mixing ideal, a small amount of the NMOS transistor flicker noise will
action of the VCO circuit. Additionally, when the single be upconverted.
differential oscillator circuit of Fig. 1(a) is unbalanced, the
common-mode node of the current source will oscillate at twice B. Flicker-Noise Upconversion Factor
the oscillator center frequency, 2 , because the current source
In the above section, it is shown that upconversion is highly
will be pulled every time one of the NMOS transistors switches
dependent on the symmetry of the output waveform. The rela-
on. Through channel length modulation, the noise of the tail
tion between noise upconversion and symmetry is confirmed by
current source is upconverted to 2 The upconverted noise
[9], which state that flicker-noise upconversion is minimal for
enters the LC-tank and is mixed with the fundamental oscillator
waveforms with half-wave symmetry
frequency, resulting in phase-noise sidebands at the oscillator
with the waveform period), i.e., for waveforms with no even
frequency. Therefore, to minimize the upconversion of flicker
harmonics.
noise from the tail current source, all even harmonics must be
In this paper, a flicker-noise upconversion factor is de-
suppressed, meaning that the circuit must be as symmetric as
fined, which is the difference between the minimum and max-
possible. Odd harmonics have little importance for flicker-noise
imum of the derivative of the VCO output waveform
upconversion because they do not affect the symmetry, and
noise at odd harmonics does not result in sidebands around the (3)
fundamental frequency when mixed. Flicker noise from the
tail current source will be the main contributor to 1 phase These values are proportional to the rising and the falling
noise. The contribution of the NMOS gm-transistors is small slopes of the waveform. The difference between the slopes indi-
due to the switching of the oscillator. Flicker noise is correlated cates the asymmetry of the waveform and thus its sensitivity to
noise and can only exist in systems with memory. When low-frequency noise upconversion. The extremes of the deriva-
transistors are ideally switched, all memory and consequently tive occur at the zero crossings where the oscillator is most sen-
the flicker noise is removed [8]. When the switching is not sitive to noise-induced phase errors.
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1036 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000

To determine the white noise upconversion the method pre-

sented in [10] is used. The impulse sensitivity function (ISF),
which describes the sensitivity of an oscillator to phase pertur-
bations due to fluctuations produced by noise in the oscillator,
is extracted from Hspice simulations. The ISF is defined as fol-
lows:

(4)

where which is the average value of the ISF, accounts for the
upconversion of low-frequency noise (flicker noise) and for
the upconversion of white noise at multiples of the carrier fre-
quency The rms value of the ISF, is proportional to the
total upconverted white noise. can be extracted by calculating
the average value of the derivative of the simulated output wave-
form. Since the presented oscillators are balanced circuits (see
Section IV), their output waveform is quite symmetrical, and
consequently, the dc value of the derivative will be very small.
As a result, the accuracy of when extracted from Hspice
simulations, will be highly sensitive to the accuracy (number of
points, number of periods) of the simulation and choice of the
start and end points of the simulated waveform, which must be
exactly the same to obtain good results. is less sensitive to
simulation inaccuracy and is fast and easy to extract from sim-
ulations. Therefore, it is applied as the measure for the flicker
noise upconversion instead of
Based on the ratio of flicker noise and white noise upconver- Fig. 2. (a) Simulated 1=f phase-noise corner factor . (b) Simulated
differential amplitude versus the NMOS cross-coupled pair overdrive voltage.
sion factor, a factor proportional to the 1 phase-noise
corner frequency can be calculated, The
developed method provides a fast way to examine different de- transient simulations, keeping the gm of the NMOS transistors
sign tradeoffs to minimize flicker-noise upconversion based on constant. A minimum exists for the 1 phase-noise corner
Hspice simulations. It will be used in the next section to deter- factor at 0.35 V. However, at that bias point, the differential
mine the bias point for minimal 1 phase noise of VCO’s and amplitude [see Fig. 2(b)] is only moderate. As a tradeoff, a
to evaluate further flicker-noise upconversion minimization by of 0.375 V was chosen.
balancing circuit techniques. As stated in Section III, the main source of upconverted
flicker noise is the current source. Therefore, a PMOS transistor
IV. DESIGN OF THE VCO’S was chosen for the tail current source because of its inherently
lower flicker noise (approximately 10 dB), compared to NMOS
The two integrated VCO circuits are shown in Fig. 1. Both
transistors. The area of the PMOS transistor is increased, by
VCO’s are designed for 2-GHz operation. For low power-supply
designing the transistor length larger than the minimum length,
voltage, the single differential NMOS topology is chosen over
to further minimize the flicker-noise contribution.
the complementary differential topology to enable the oscilla- In VCO2, additional circuit techniques are applied to further
tors to operate in the current limited region, i.e., the amplitude
minimize the flicker-noise upconversion. A capacitance and a
is not limited by the power supply. On the other hand, the com- cascode transistor are added to the common-mode node of the
plementary differential topology can enhance the symmetry of
tail current source to suppress all common-mode node varia-
the circuit, when the PMOS and NMOS cross-coupled pairs are
tions. As a result, noise upconversion due to channel length
properly sized, and hence further minimize the flicker-noise up- modulation by higher (and especially the second) order har-
conversion. The tuning of the VCO is done by variable capaci-
monics is suppressed. The capacitor of 60 pF provides a
tances, consisting of two p n-well diode junctions. low impedance path to ac ground for higher harmonics. The
The circuits of VCO1 [11] and VCO2 are shown in Fig. 1(a).
cascode transistor increases the output resistance with an extra
The most important parameter of the VCO circuit design is
further reducing the common-mode node variations.
the overdrive voltage, the of the NMOS transistors. The resulting 1 phase-noise upconversion factor and differ-
The choice of the determines the output amplitude,
ential amplitude versus overdrive voltage are shown in Fig. 2.
the power consumption, the added parasitic capacitance of the At lower and higher overdrive voltages, the flicker-noise upcon-
NMOS transistors, and the flicker-noise upconversion. The
version is substantially smaller due to the balancing circuit tech-
transconductance of the NMOS transistors is a constant for
niques. The lower amplitude [see Fig. 2(b)] can be explained by
the oscillator design, when the LC-tank parameters and the (5)
wanted safety for startup are known. Fig. 2 shows the 1
corner factor and the output amplitude versus the NMOS
overdrive voltage. The values where extracted from Hspice (5)
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000 1037

with the differential amplitude, the parallel parasitic

tank resistance, the tail current, and the amplitude factor.
In a linear VCO, the current through the tank will be a perfect
sine wave and will be equal to one. When the VCO circuit is
ideally switched, the current will be a square wave and will be
4 (the fast Fourier transform coefficient of the fundamental
component of a square wave). The effect of the balancing cir-
cuit techniques is a more linear VCO, resulting in an amplitude
factor closer to one ( ) for VCO2 when compared to
VCO1 ( ). At high amplitudes (high overdrive volt-
ages), both VCO’s operate in the voltage-limited region, where
the amplitude is limited by the available power supply voltage.
Due to its overall lower output amplitude, VCO2 will have a
worse phase-noise performance than VCO1 at higher offset fre-
quencies.

V. EXPERIMENTAL RESULTS
The maximum oscillation frequency of the VCO’s is 2 GHz.
The tuning range is 11%, 1.79–2 GHz for a tuning voltage range
of 1.1–1.8 V. Microphotographs of both VCO circuits are pre-
sented in Fig. 3. All phase-noise measurements were performed
with a dedicated phase-noise measurement system, using the
delay-line method. Due to the delay line, the measurement ac-
curacy degrades for offset frequency higher than 5 MHz.
Fig. 5 shows the measured phase-noise spectrum of VCO1
(black curve). The phase noise is measured to be 125.1
dBc/Hz at 600 kHz and 138 dBc/Hz at 3 MHz. The measured
phase noise exceeds the most stringent specifications for
DCS-1800 systems [ETS(I) 300 910, GSM 05.05 version 5.4.1
p. 22 5.2 & p. 25 6.2]. The excellent phase-noise performance
was achieved at a power consumption of 19 mA from a 1.8-V
power supply. To show the dependence of the phase noise
on the NMOS transistor overdrive voltage, both VCO’s were
measured at different tail currents [see Fig. 4(a)]. The phase
noise gets better for higher overdrive voltage due to the higher
amplitude, as long as the oscillators operate in the current
limited region. At values higher than 0.4 V, the
oscillators enter the voltage limited region. At 0.475 V, the
measured phase noise of VCO1 is even as low as 127.5
dBc/Hz, with a 60-mW power consumption.
The phase-noise difference between the two VCO’s is larger
than predicted by simulated amplitude differences, and VCO2
enters the voltage-limited region earlier than expected. Both ef-
fects can be explained by the fact that changing the bias current
changes the gm of the NMOS transistors. When the bias current
is increased, the resulting amplitudes will be higher than simu- Fig. 3. Microphotographs of (a) VCO1 and (b) VCO2.
lated. Due to the balancing circuit techniques, this effect will be
less pronounced in VCO2. VCO2 will enter the voltage limited
region sooner than expected because of the higher amplitude simulations. The 1 phase-noise corner differences are rather
and the large saturation voltage, needed to keep the cascode cur- small, because both VCO’s are already optimized, so that addi-
rent source in the saturation region. At overdrive levels, smaller tional circuit techniques can only have a small impact.
than 0.3 V, the VCO’s fail to oscillate because of the too-low To show that the technology cannot explain the good flicker-
transconductance. noise upconversion results, the phase-noise performance of the
Fig. 4(b) shows the measured 1 phase-noise corner versus VCO in [5] (gray curve) is presented in Fig. 5, together with
the overdrive voltage. VCO1 has a phase-noise corner of 15 VCO1. The VCO operates at 1.3 GHz, and its phase noise is
kHz, measured at the same bias point as in the previous section. scaled to 2 GHz for comparison. The VCO is implemented in the
The flicker-noise upconversion is smaller for VCO2, especially same BiCMOS technology, but its measured 1 phase-noise
at the highest and lowest overdrive voltages, as shown in the corner is around 200 kHz.
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1038 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 7, JULY 2000

TABLE II
COMPARISON OF DIFFERENT (Bi)CMOS VCO’s WITH
INTEGRATED INDUCTORS. PHASE NOISE IS RECALCULATED
TO 1.8 GHz AND AT 600 kHz

as 125.1 dBc/Hz at 600-kHz offset and 138 dBc/Hz at 3

MHz. The excellent phase-noise performance is achieved by
means of an in-house-developed simulator-optimizer. The up-
conversion of flicker noise to 1 phase noise is explained and
minimized by defining a flicker-noise upconversion factor. The
factor is used to find the optimal overdrive voltage for the MOS
cross-coupled pair, resulting in a 1 phase-noise corner of
only 15 kHz. Circuit balancing techniques are shown to even
further reduce the 1 phase-noise corner. While consuming
19 mA from a 1.8-V power supply, the measured phase-noise
performance exceeds the stringent DCS-1800 phase-noise spec-
ifications.

Fig. 4. Measured phase noise at 600-kHz offset (a) measured 1=f
phase-noise corner (b) versus the NMOS cross-coupled pair overdrive voltage
for both VCO’s.
Fig. 5. Phase-noise measurements of VCO1 and the VCO presented in [5].
In Table II, the measured phase noise and the measured 1
phase-noise corner frequency are compared with some of the
best published (Bi)CMOS VCO’s with integrated inductors. For
comparison, the phase noise of the VCO’s is recalculated to 1.8
GHz at 600-kHz offset. As can be seen in Table II, the presented
VCO has the best phase-noise performance and the lowest 1
phase-noise corner frequency.
VI. CONCLUSIONS
A fully integrated 2-GHz very low-phase-noise LC-tank VCO
set with flicker-noise upconversion minimization is integrated in
a three-metal-layer 0.65- m BiCMOS process. Using only in-
tegrated planar inductors, the measured phase noise is as low
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