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Module 5 dsdv notes new

Digital System Design using verilog (Visvesvaraya Technological University)

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Digital System Design using Verilog

Module-5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential
Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1).
(Section 3.1 to 3.4 (only Verilog) of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of
structural description, Structural description of ripple carry adder. (Section 4.1 to 4.2 of Text
3)

Behavioral Description Highlights

The behavioral description is a powerful tool to describe systems for which digital logic
structures are not known or are hard to generate. Examples of such systems are complex
arithmetic units, computer control units, and biological mechanisms that describe the
physiological action of certain organs such as the kidney or heart.
Facts
• The behavioral description describes the system by showing how outputs behave with
the changes in inputs.
• In this description, details of the logic diagram of the system are not needed; what is
needed is how the output behaves in response to a change in the input.
• In Verilog, the major behavioral-description statements are always and initial.In
Verilog, all statements are concurrent

Structure of the HDL Behavioral Description

Listing 3.1 shows a simple example of HDL code describing a system (half_add) using
behavioral description. Usually sequential statements such as IF or Case are used to describe
the change of the output, Boolean functions are used to describe the change. This is done here
to explain how the HDL executes signal-assignment statements written inside always or initial
(Verilog). The code in Listing 3.1 mainly consists of signal-assignment statements.

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Digital System Design using Verilog

Referring to the Verilog code in Listing 3.1, always is the Verilog behavioural statement all
Verilog statements inside always are treated as concurrent, the same as in the data-flow
description . Also, here any signal that is declared as an output or appears at the left-hand side
of a signal-assignment statement should be declared as a register (reg) if it appears inside
always. In Listing 3.1, O1 and O2 are declared outputs, so they should also be declared as reg.
LISTING 3.1 Example of an HDL Behavioral Description

Verilog Description
module half_add (I1, I2, O1, O2);
input I1, I2;
output O1, O2;
reg O1, O2;
/* Since O1 and O2 are outputs and they are written inside “always,” they should be declared
as reg */
always @(I1, I2)
begin
#10 O1 = I1 ^ I2; // statement 1.
#10 O2 = I1 & I2; // statement 2.
/*The above two statements are signal-assignment statements with 10 simulation screen units
delay*/
/*Other behavioral (sequential) statements can be added here*/
end
endmodule
Sequential Statements
There are several statements associated with behavioral descriptions. These statements have to
appear inside always or initial in Verilog. The following sections discuss some of these
statements.
IF Statement
IF is a sequential statement that appears inside always or initial in Verilog. It has several
formats, some of which are as follows:
Verilog IF-Else Formats
if (Boolean Expression)
begin
statement 1; /* if only one statement, begin and end can be omitted */
statement 2;
statement 3;
.......
end
else
begin
statement a; /* if only one statement, begin and end can be omitted */
statement b;
statement c;
.......
end

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Digital System Design using Verilog

The execution of IF statement is controlled by the Boolean expression. If the Boolean

expression is true, then statements 1, 2, and 3 are executed. If the expression is false, statements
a, b, and c are executed.

EXAMPLE 3.1 BOOLEAN EXPRESSION AND EXECUTION OF IF

Verilog
if (clk == 1’b1)
// 1’b1 means 1-bit binary number of value 1.
temp = s1;
else
temp = s2;
In Example 3.1, if clk is high (1), the value of s1 is assigned to the variable temp. Otherwise,
s2 is assigned to the variable temp. The else statement can be eliminated, and in this case, the
IF statement simulates a latch, as shown in Example 3.2.
EXAMPLE 3.2 EXECUTION OF IF AS A LATCH
Verilog
if (clk == 1)
begin
temp = s1;
end
If clk is high, the value of s1 is assigned to temp. If clk is not high, temp retains its current
value, thus simulating a latch. Another format for the IF statement is Else-IF.

EXAMPLE 3.3 EXECUTION OF IF AS ELSE-IF

Verilog
if (Boolean Expression1)
begin
statement1; statement 2;.....
end
else if (Boolean expression2)
begin
statementi; statementii;.....
end
else
begin
statementa; statement b;....
end

EXAMPLE 3.4 IMPLEMENTING ELSE-IF

Verilog
if (signal1 == 1’b1)
temp = s1;
else if (signal2 == 1’b1)
temp = s2;
else
temp = s3;
After execution of the above IF statement, temp acquires the values shown in Table 3.1.

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Digital System Design using Verilog

TABLE 3.1 Output Signals (temp) for Else-IF Statements in Example 3.4

The Boolean expression may specify other relational operations such as inequality or greater
than or less than. To illustrate the difference between signal- and variable-assignment
statements in VHDL code, the behavioral description of a D-latch is written in Example 3.5. A
process is written based on signal-assignment statements, and another process is written based
on variable-assignment statements. A comparison of the simulation waveforms of the two
processes will highlight the differences between the two assignment statements.
EXAMPLE 3.5 BEHAVIORAL DESCRIPTION OF A LATCH USING VARIABLE
AND SIGNAL ASSIGNMENTS
The functionality of a D-latch can be explained as follows: if the enable (E) is active, the output
of the latch (Q) follows the input (d); otherwise, the outputs remain unchanged. Also, Qb, the
invert output, is always the invert of Q. Figure 3.3a shows the logic symbol of a D-latch. A
flowchart that illustrates this functionality is shown in Figure 3.3b.

LISTING 3.4 Verilog Code for Behavioral Description of a D-Latch

module D_latch (d, E, Q, Qb);
input d, E;
output Q, Qb;
reg Q, Qb;
always @ (d, E)
begin
if (E == 1)
begin
Q = d;
Qb = ~ Q;
end
end
endmodule

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Digital System Design using Verilog

EXAMPLE 3.6 BEHAVIORAL DESCRIPTION OF A 2x1 MULTIPLEXER WITH

TRI-STATE OUTPUT
To describe the behavior of the output of a multiplexer with the change in the input, a flowchart
is developed. Figure 3.6a shows the logic symbol of the multiplexer, and Figure 3.6b shows
diagram a flowchart describing the functionality of the multiplexer. The flowchart shows how
the output behaves with the input. The output is high impedance if the enable (Gbar) is high.
When the enable is low, the output is equal to input B if select is high; otherwise, the output is
equal to A. The logic diagram of the multiplexer is not needed to write the HDL behavioral
description. Although the flowchart here represents a 2x1 multiplexer, it can represent any
other applications that have the same behavior; these applications may come from a variety of
fields such as electrical engineering, computer engineering, science, business, biomedical
engineering, and many other fields. In this example, for simplicity, the propagation delays
between the input and the output are not considered. Listing 3.5 shows the HDL description of
the multiplexer using the IF-Else statement, and Listing 3.6 shows the HDL description with
the Else-IF statement. The VHDL code uses variable-assignment statements to declare the
variable temp; this variable is treated as if it is the output. After calculation of its value, the
variable is assigned to the output Y. VHDL executes variable-assignment statements, as does
C language; no delay time is involved in the execution. The signal-assignment statements Y
<= ‘Z’; in VHDL and Y = 1’bz; in Verilog assign high impedance to the singlebit Y. If Y is a
three-bit signal, then the two statements in VHDL and Verilog are Y <= “ZZZ”; and Y =
3’bzzz;, respectively. Figure 3.7 shows the simulation waveform of the multiplexer.

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Digital System Design using Verilog

Verilog Description
module mux2x1 (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
reg Y;
always @ (SEL, A, B, Gbar)
begin
if (Gbar == 1)
Y = 1’bz;
else
begin
if (SEL)
Y = B;
else
Y = A;
end
end
end module

LISTING 3.6 HDL Description of a 2x1 Multiplexer Using Else-IF

Verilog Description
module MUXBH (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
reg Y; /* since Y is an output and appears inside always, Y has to be declared as reg( register)
*/
always @ (SEL, A, B, Gbar)
begin
if (Gbar == 0 & SEL == 1)
begin
Y = B;
end
else if (Gbar == 0 & SEL == 0)
Y = A;
else
Y = 1’bz; //Y is assigned to high impedance
end
endmodule

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Digital System Design using Verilog

The case Statement

The case statement is a sequential control statement. It has the following format:
Verilog Case Format
case (control-expression)
test value1 : begin statements1; end
test value2 : begin statements2; end
test value3 : begin statements3; end
default : begin default statements end
endcase
If, for example, test value1 is true (i.e., it is equal to the value of the control expression),
statements1 is executed. The case statement must include all possible conditions (values) of
the control-expression. The statement when default (Verilog) can be used to guarantee that all
conditions are covered. The case resembles IF except the correct condition in case is
determined directly, not serially as in IF statements. The begin and end are not needed in
Verilog if only a single statement is specified for a certain test value. The case statement can
be used to describe data listed into tables.
EXAMPLE 3.7 THE CASE STATEMENT
Verilog
case sel
2’b00 : temp = I1;
2’b01 : temp = I2;
2’b10 : temp = I3;
default : temp = I4;
endcase
In Example 3.7, the control is sel. If sel = 00, then temp = I1, if sel = 01, then temp = I2, if sel
= 10, then temp = I3, if sel = 11 (default), then temp = I4. All four test values have the same
priority; it means that if sel = 10, for example, then the third statement (temp := I3) is executed
directly without checking the first and second expressions (00 and 01).

EXAMPLE 3.8 BEHAVIORAL DESCRIPTION OF A POSITIVE EDGE-TRIGGERED

JK FLIP-FLOP USING THE CASE STATEMENT
Edge-triggered flip-flops are sequential circuits. Flip-flops are triggered by the edge of the
clock, in contrast to latches where the level of the clock (enable) is the trigger. Positive
(negative) edge-triggered flip-flops sample the input only at the positive (negative) edges of
the clock; any change in the input that does not occur at the edges is not sampled by the output.
Figures 3.8a and 3.8b show the logic symbol and the state diagrams of a positive edge-triggered
JK flip-flop, respectively.

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Table 3.2 shows the excitation table of the JK flip-flop. It conveys the same information as the
state diagram. The state diagram (Figure 3.8b) shows the possible states (two in this case: q
can take 0 or 1), state 0 and state 1. The transition between these states has to occur only at the
positive edges of the clock. If the current state is 0 (q = 0), then the next state is 0(1) if JK =
0x(1x), where x is “don’t care.” If the current state is 1 (q = 1), then the next state is 1(0) if JK
= x0(x1). Table 3.2 shows the same results as the state diagram. For example, a transition from
0 to 1, according to the excitation table, can occur if JK = 10 or JK = 11, which is JK = 1x.

Listing 3.7 shows the HDL code for a positive edge-triggered JK flipflop using the case
statement. In the Listing, rising_edge (VHDL) and posedge (Verilog) are predefined words
called attributes. They represent the positive edge of the clock (clk). If the positive edge is
present, the attribute yields to true. For VHDL, the clk has to be in std_logic to use this attribute.
Other attributes are covered in Chapters 4, 6, and 7. Any of the four case statements can be
replaced with default(Verilog).
For example:
2’d3 : q =~ q; // Verilog
can be replaced by:
default : q =~ q; // Verilog
The waveform of the flip-flop is shown in Figure 3.9.

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Digital System Design using Verilog

LISTING 3.7 HDL Code for a Positive Edge-Triggered JK Flip-Flop Using the caseStatement
Verilog Description
module JK_FF (JK, clk, q, qb);
input [1:0] JK;
input clk; output
q, qb;reg q, qb;
always @ (posedge clk)
begin
case (JK) 2’d0 : q
= q;
2’d1 : q = 0;
2’d2 : q = 1;
2’d3 : q =~ q;
endcase
qb =~ q; end
endmodule

EXAMPLE 3.9 BEHAVIORAL DESCRIPTION OF A THREE-BIT BINARY

COUNTER WITH ACTIVE HIGH SYNCHRONOUS CLEAR
Counters are sequential circuits. For count-up counters (or simply up counters), the next state is
the increment of the present state. For example, if the present state is 101, then the next stateis 110.
For down-count counters (or simply down counters), the next state is the decrement of the present
state. For example, if the present state is 101, then the next state is 100. A three-bit binary up
counter counts from 0 to 7 (Mod 8). Decade counters count from 0 to 9 (Mod10). Synchronous
clear means that clear resets the counter when the clock is active; in contrast, asynchronous clear
resets the counter instantaneously. The counter can be depicted by a flowchart showing its
function (see Figure 3.10). Although the flowchart here represents a counter, it could have
represented any other system with the same behavior. The excitation table for the three-bit binary
counter is as shown in Table 3.3. The logic symbol is shown in Figure 3.10a.

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Digital System Design using Verilog

The most efficient approach to describe the above counter is to use the fact that the next state is
the increment of the present for upward counting. The goal here, however, is to use the case
statement. Table 3.3 is treated as a look-up table. Listing 3.8 shows the HDL code for the counter.
To assign initial values, such as 101, to the count at the start of simulation in Verilog, the
procedural initial is used as follows:
initial
begin
q = 3’b101;
end
The begin and end can be omitted if there is a single initial statement Figure 3.11 shows the
simulation waveform of the counter.
LISTING 3.8 HDL Code for a Three-Bit Binary Counter Using the case Statement
Verilog Description
module CT_CASE (clk, clr, q);
input clk, clr;
output [2:0] q;
reg [2:0] q;
initial
/* The above initial statement is to force the counter to start from initial count q=110 */q =
3’b101;
always @ (posedge clk)
begin
if (clr == 0)
begin
case (q)
3’d0 : q = 3’d1;
3’d1 : q = 3’d2;
3’d2 : q = 3’d3;
3’d3 : q = 3’d4;
3’d4 : q = 3’d5;
3’d5 : q = 3’d6;
3’d6 : q = 3’d7;
3’d7 : q = 3’d0;
endcaseend
else
q = 3’b000;
end endmodule

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Digital System Design using Verilog

Verilog casex and casez

Verilog has another two variations of case: casex and casez. casex ignores the “don’t care” values
of the control expression, and casez ignores the high impedance in the control expression. For
example, in the code
casex (a)
4’bxxx1: b = 4’d1;
4’bxx10: b = 4’d2;
………………..
endcase;
all occurrences of x are ignored; b = 1 if and only if the least significant bit of a (bit order 0) is 1,
regardless of the value of the higher order bits of a, and b = 2 if the bits of order 0 and 1 are 10,
regardless of the value of all other bits. For the Verilog variation casez, all high-impedance values
(z) in control expressions are ignored. For example:
casez (a)
4’bzzz1 : b = 4’d1;
4’bzz10 : b = 4’d2;
………………..
endcase;
b = 1 if and only if the least significant bit (bit of order 0) of a = 1, and b = 2 if bit 0 of a = 0and
bit 1 of a = 1.
EXAMPLE 3.11 VERILOG DESCRIPTION OF A PRIORITY ENCODER USINGCASEX
A priority encoder encodes the inputs according to a priority set by the user, such as when theinput
represents interrupt requests. If two or more interrupt requests are issued at the same time by the
devices needing service, and the central processing unit (CPU) can only serve one device at a time,
then one of these requests should be given priority over the others and be served first. A priority
encoder can handle this task. The input to the encoder is the interrupt requests, and the output of
the encoder can be memory addresses where the service routine is located or an address leading to
the actual address of the routines. Table 3.5 shows the truth table of a four- bit encoder; bit 0 of
input a has the highest priority. Listing 3.11 shows the Verilog description for a four-bit priority
encoder. Figure 3.14 shows the simulation waveform of Listing 3.11.

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Digital System Design using Verilog

LISTING 3.11 Verilog Description for a Four-Bit Priority Encoder Using casex
module Encoder_4 (Int_req, Rout_addrs);
input [3:0] Int_req;
output [3:0] Rout_addrs;
reg [3:0] Rout_addrs;
always @ (Int_req) begin
casex (Int_req)
4’bxxx1 : Rout_addrs=4’d1;
4’bxx10 : Rout_addrs=4’d2;
4’bx100 : Rout_addrs=4’d4;
4’b1000 : Rout_addrs= 4’d8;
default : Rout_addrs=4’d0;
endcase
end endmodule

The wait-for Statement

The wait statement has several formats; in this section, only wait for a time period is discussed. For
example:
Verilog # 10;
The wait statement can be implemented to generate clocks, as it is usually common in bench
marks. Listing 3.12 shows an example of using the wait-for statement to generate three different
clocks: a with a period of 20 ns, b with a period of 40 ns, and c with a period of 80 ns. Note that if
always (Verilog) does not have a sensitivity list, this always will run indefinitely. Figure 3.15
shows the waveform of Listing 2.12.
LISTING 3.12 Implementation of the wait-for Statement to Generate Clocks
Verilog
module waitstatement(a,b,c);
output a,b,c;
reg a,b,c;
initial
begin
// Initialize Inputsa =
0;
b = 0;
c = 0;
end always
begin #10 ;
a = ~ a;end

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Digital System Design using Verilog

always
begin #20 ;
b = ~ b;end
always
begin #40 ;
c = ~ c; end
endmodule

The Loop Statement

Loop is a sequential statement that has to appear inside always or initial in Verilog. Loop is used
to repeat the execution of statements written inside its body. The number of repetitions iscontrolled
by the range of an index parameter. The loop allows the code to be compressed; instead of writing
a block of code as individual statements, it can be written as one general statement that, if
repeated, reproduces all statements in the block. There are several ways to construct a loop. Some
of those ways are discussed here.
For-Loop
The HDL general format for a For-Loop is:
for <lower index value> <upper index value> <step>
statements1; statement2; statement3; ….
end loop
If the value of index is between lower and upper, all statements written inside the body of the loop
are executed. For each cycle, the index is modified at the end loop according to the step. If the
value of index is not between the lower and upper values, the loop is terminated.
EXAMPLE 3.12 FOR-LOOP: VERILOG
Verilog For-Loop
for (i = 0; i <= 2; i = i + 1)
begin
if (temp[i] == 1’b1)
begin
result = result + 2**i;end
end
statement1; statement2; ....
The index is i, the lower value is 0, the upper value is 2, and the step is 1. All statements between
the for statement and end loop are executed until the index i goes out of range. At the very
beginning of the loop, i takes the value of 0, and the statements if and result are executedas:
if temp(0) = ‘1’ then result
:= result + 2**0;
When the program encounters the end of the loop, it increments i by 1. If i is less than or equalto 2,
the loop is repeated; otherwise, the program exits the loop and executes statement1, statement2,
and so on. In Verilog, ‘I’ has to be declared. If the loop statement is stated without range, the loop
will run indefinitely.

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While-Loop
The general format of the While-Loop is:
while (condition)
Statement1;
Statement2;
…………end
As long as the condition is true, all statements written before the end of the loop are executed.
Otherwise, the program exits the loop.

EXAMPLE 3.13 WHILE-LOOP: VERILOG

Verilog While-Loop
while (i < x)
begin
i = i + 1; z = i
* z;end
In the above example, the condition is (i < x). As long as i is less than x, i is incremented, and the
product i * z (i multiplied by z) is calculated and assigned to z.
Verilog repeat
In Verilog, the sequential statement repeat causes the execution of statements between its begin and
end to be repeated a fixed number of times; no condition is allowed in repeat.

EXAMPLE 3.14 VERILOG REPEAT

repeat (32)
begin
#100 i = i + 1;
end
In the above example, i is incremented 32 times with a delay of 100 screen time units. This
describes a five-bit binary counter with a clock period of 100 screen time units.
Verilog forever
The statement forever in Verilog repeats the loop endlessly. One common use for forever is to
generate clocks in code-oriented test benches. The following code describes a clock with a period
of 20 screen time units:
initial
begin
Clk = 1’b0;
forever #20 clk = ~clk;end

EXAMPLE 3.16 BEHAVIORAL DESCRIPTION OF A FOUR-BIT POSITIVE EDGE-

TRIGGERED SYNCHRONOUS UP COUNTER

In this example, the Loop statement is used to convert values between binary and integer and use
this conversion to describe a binary up counter. The HDL package is assumed to not contain
predefined functions that will increment a binary input or convert values between binary and
integer. In addition, the current and next state are expressed in binary rather than integer.
Describing a counter using the above binary-to-integer conversion is not the most efficient way;
the main goal here is to demonstrate the implementation of the Loop statement.

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The next state of a binary counter is generated by incrementing the current state. Because, in this
example, a binary value cannot be incremented directly by the HDL code, it is first converted to an
integer. HDL packages can easily increment integers. We increment the integer and convert it back
to binary. To convert an integer to binary, the predefined operator % in Verilog is used. For
example: (X MOD 2) equals 1 if X is 1 (odd) or equals 0 if X is 0 (even, divisible by 2). By
successively dividing the integer by 2 and recording the remainder from theoutcome of the MOD2,
the integer is converted to binary. To convert a binary to integer, multiply each bit by its weight
and accumulate the products: 10112 = (1 × 1) + (1 × 2) + (0 × 4) + (1 × 8) = 1110. If the bit is
equal to 0, it can be ignored. Listing 3.13 shows the HDL code of the counter. The simulation
waveform is the same as that shown in Figure 3.11, except the count here is from 0 to 15 rather
than from 0 to 7 as in the figure.

LISTING 3.13 HDL Code for a Four-Bit Counter With Synchronous Clear: Verilog
Verilog Description
module CNTR_LOP (clk, clr, q);
input clk, clr;
output [3:0] q;
reg [3:0] q; integer i, j,
result;initial
begin
q = 4’b0000; //initialize the count to 0
end
always @ (posedge clk)
begin
if (clr == 0)
begin
result = 0;
//change binary to integerfor (i
= 0; i < 4; i = i + 1) begin
if (q[i] == 1) result =
result + 2end i;
result = result + 1;
for (j = 0; j < 4; j = j + 1)
begin
if (result %2 == 1)
q[j] = 1;
else
q[j] = 0;
result = result/2;end
end
else q = 4’b0000;end
endmodule
A more efficient approach to describe a binary counter is to directly increment the current state. As
mentioned before, the approach implemented in Listing 3.13 is not the most efficient way to
describe a counter. To write an efficient code for a four-bit counter, direct increment of the current
state is used. The following Verilog code describes a four-bit binary counter using direct
increment of the current state:

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Digital System Design using Verilog

module countr_direct (clk, Z);

input clk;
output [3:0] Z;
reg [3:0] Z;
initial
Z = 4’b0000;
/*This initialization is needed if we want to start counting from 0000 */
always @ (posedge clk)
Z = Z + 1;
endmodule

EXAMPLE 3.17 BEHAVIORAL DESCRIPTION OF A FOUR-BIT COUNTER WITH

SYNCHRONOUS HOLD USING THE LOOP STATEMENT
To write the code for the counter, binary-integer conversion is used. As mentioned in Example3.16,
this approach is not the most efficient way to describe a counter, but it will be implemented here
to demonstrate the use of Loop and the Exit statements. The hold signal in a counter, when active,
retains the value of the output and keeps it unchanged until the hold is inactivated. The flowchart
of the counter is shown in Figure 3.16. In VHDL, an exit statementis used to exit the loop when the
hold is active. Verilog, however, does not have an explicit exit statement, but the loop can be exited
by assigning the index a value higher than its upper value. Listing 3.14 shows the HDL code for the
counter. Figure 3.17 shows the simulation waveformof the counter.

LISTING 3.14 HDL Code for a Four-Bit Counter with Synchronous Hold:Verilog
Verilog 4-Bit Counter with Synchronous Hold Description
module CT_HOLD (clk, hold, q);
input clk, hold;
output [3:0] q;
reg [3:0] q; integer i,
result;initial
begin
q = 4’b0000; //initialize the count to 0
end
always @ (posedge clk)
begin
result = 0;

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//change binary to integer for (i

= 0; i <= 3; i = i + 1)begin
if (q[i] == 1) result =
result + 2end i;
result = result + 1;
for (i = 0; i <= 3; i = i + 1)
begin
if (hold == 1)
i = 4; //4 is out of range, exit.else
begin
if (result %2 == 1)
q[i] = 1;
else
q[i] = 0;
result = result/2;end
endend
endmodule

EXAMPLE 3.18 SHIFT REGISTERS DESCRIPTION USING THE LOOP

STATEMENT
The main function of a general-purpose register is to store data. The data can be retrieved, or it
can be stored indefinitely. The data in the register can be manipulated by several actions such as
shift. The data can be shifted right or left logically , where zeros are used to fill the vacant bits
after shifting; in this shift, some data can be lost. The data can also be shifted arithmatically, where if
shifted right, the sign of the data (the most significant bit) is preserved. The data in the register can
also be rotated left or right (Figure 3.18); here no data are lost. Shift operation is widely used in
many areas of digital design such as arithmetic units and serial communications. Shift registers
may have an external input bit that replaces the vacant bit after shift. Other registers may have load
and bidirectional shifts; these registers are called universalshift registers .

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Listing 3.15 shows a HDL code for describing a logical shift, as shown in Figure 3.18, using the
Loop statement. The code shifts register q n bits right or left logically. The number of bits to be
shifted is determined by user-selected parameter N. The code resembles the preserved statement
sll and slr in VHDL and ( << and >>) in Verilog. $display statement in Listing 3.15 is one of
Verilog’s system tasks that displays values of objects on the console of the simulator.The statement
$display (“ i= %d”, i);
will display a printout of the text between the quotation marks ( i = ) excluding the %d, which
determines that the object should be displayed in decimal. The i after the comma is the object to be
displayed. The $display is a tool that can be used to display objects that are not listed as an output.
Several other formats can be selected for display such as:
%b for binary
%o for octal
$d for decimal
%h for hexadecimal
%t for time
%e or %f or %g for real
%c for character
%s for string
%v for binary and strength

LISTING 3.15 HDL Code for Logical Shifting of a Register Using the Loop Statement
Verilog Description
module shft_regVerilog(start,shft, N,q);
input start,shft;
input [7:1] N;
//N is number of requested shifts
output [7:0]q;
reg [7:0]q;
integer i,j;
initial
q = 8’b01100110;
/*initial values for the vector is selected to be 1100110 */
always @ (posedge start)
begin
lop2: for (j= 1; j <= N; j = j +1)
begin
lop1: for (i= 0; i <= 6; i = i +1)
begin
if (shft == 1’b0 )
/*shft = 0 is logical right shift; =1 logical left Shift */
begin
$display (“ shft = %d”, shft);/ This is a system taskto
display The value of shift on the console’s
screen of the simulator /

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$display (“ i= %d”, i);

$display (“q[i] = %b”, q[i]);
$display (“q[i+1] = %b”, q[i+1]);q[i]
= q[i+1];
q[7] =1’b0; $display (“ q = %b”, q);endelse
begin q[7-i] = q[6-i];q[0]
= 1’b0; end
$display (“ shft = %d”, shft);end
endend
Highlights of Structural Description
Structural description is best implemented when the digital logic of the details of hardware
components of the system are known. An example of such a system is a 2x1 multiplexer. The
components of the system are known: AND, OR, and NOT gates. Structural description can easily
describe these components. On the other hand, it is hard to describe the digital logic of hormone
secretion in the blood; therefore, another description such as behavioral or mixed may be
implemented. Structural description is very close to schematic simulation.

Facts
• Structural description simulates the system by describing its logical components. The
components can be gate level (such as AND gates, OR gates, or NOT gates), or components
can be in a higher logical level, such as register-transfer level (RTL) or processor level.
• It is more convenient to use structural description than behavioural description for systems
that require specific design constraints. Consider, for example, a system performing the
operation A + B = C. In behavioural description, the addition can be written as C = A + B with
no choice in selecting the type of adders used to perform this addition. In structural description,
the type of adder, such as look-ahead adders, can be selected.
• ll statements in structural description are concurrent. At any simulation time, all statements that
have an event are executed concurrently.
• A major difference between VHDL and Verilog structural description is the availability of
components (especially primitive gates) to the user. Verilog recognizes all the primitive gates
such as AND, OR, XOR, NOT, and XNOR gates. Basic VHDL packages do not recognize any
gates unless the package is linked to one or more libraries, packages, or modules that have the
gate description.
•
Organization of Structural Description
Listing 4.1 shows an example of HDL code that describes a half adder under the name of system
using structural description. The module (Verilog) name is system; there are two inputs, a and b,
and two outputs, sum and cout. The module declaration is the same as in other description styles
previously covered (data flow and behavioral).
Verilog has a large number of built-in gates. For example, the statement:xor
X1 (sum, a, b);

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describes a two-input XOR gate. The inputs are a and b, and the output is sum. X1 is an optional
identifier for the gate; the identifier can be omitted as:
xor (sum, a, b);
Verilog has a complete list of built-in primitive gates. The output of the gate sum has to be listed
before the inputs a and b. Accordingly, the Verilog code in Listing 4.1 is a complete structural
description of a half adder. Figure 4.1 shows a list of gates and their code in Verilog. As in
structural Verilog statements are concurrent; the order of appearance of statements in the module is
irrelevant.

LISTING 4.1 HDL Structural Description

Verilog Description
module system (a, b, sum, cout);
input a, b;
output sum, cout; xor
X1 (sum, a, b);
/* X1 is an optional identifier; it can be omitted.*/
and a1 (cout, a, b);
/* a1 is optional identifier; it can be omitted.8/
endmodule
EXAMPLE 4.1 HDL STRUCTURAL DESCRIPTION OF A HALF ADDER
Listing 4.2 shows the HDL structural code for the half adder.
LISTING 4.2 HDL Code of Half Adder: VHDL and Verilog
Verilog Description
Module system (a, b, sum, cout);
input a, b;
output sum, cout; xor
X1 (sum, a, b);
/* X1 is an optional identifier; it can be omitted.*/
and a1 (cout, a, b);
/* a1 is optional identifier; it can be omitted.*/
Endmodule

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The VHDL code looks much longer than the Verilog code. This is due to the assumption that the
basic VHDL packages do not have built-in libraries or packages for logical gates. The binding
method above becomes impractical when the number of gates becomes large. Every time a new
description is written, the entities of all gates used must also be written.

STRUCTURAL DESCRIPTION OF A THREE-BIT RIPPLE-CARRY ADDER

In this example, a three-bit ripple-carry adder is described. The logic diagram of the adder is as

shown. Listing 4.14 shows the structural description of the three-bit ripple-carry adder.

LISTING 4.14 HDL Description of a Three-Bit Ripple-Carry Adder: Verilog

Verilog Description
module three_bit_adder (x, y, cin, sum, cout);
input [2:0] x, y;
input cin;
output [2:0] sum;
output cout;
wire [1:0] carry;
FULL_ADDER M0 (x[0], y[0], cin, sum[0], carry[0]);
FULL_ADDER M1 (x[1], y[1], carry[0], sum[1], carry[1]);

FULL_ADDER M2 (x[2], y[2], carry[1], sum[2], cout);

/* It is assumed that the module FULL_ADDER (Listing 4.13) is attached by the simulator tothe
module three_bit_adder so, no need to rewrite the module FULL_ADDER.*/
Endmodule
Inspection of the code in Listing 4.14 shows that there may be lag time between the steady state of
each of the adders and the carryout (cout). This lag time produces transient states before the values
of the sum and carryout settle. For example, if the inputs to the adder are 101 and 001, and the
previous output of the adder is 1001, some transient states can be 0100 and 1010 before the output
settles at 0110. The appearance of these transient states is called hazards. These transient states,
however, have short duration and may not be noticed.

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CALCULATING THE FACTORIAL USING BEHAVIORAL DESCRIPTION WITH WHILE-LOOP

In this example, a HDL behavioral description is written to find the factorial of a positive number
N. The factorial of N is (N!) = Nx(N-1)x(N- 2)x(N-3)x ….x1. For example, 4!=4×34×24×1=24. In
VHDL, N and the output z are declared as natural; this restricts the values that N and z can assume to
positive integers. If N and z are declared as std_logic, the mul- tiplication operator ( ) cannot be used
directly; they must be converted to integers before multiplication or an external library should be
attached. In VHDL, be sure to include all the necessary libraries. If the appropriate libraries are not
included in the code, the simulator will not accept the dec- laration and will report it as undefined.
In Verilog, the default declaration of inputs and outputs allows for the direct use of arithmetic
operators such as multiplication. Listing 3.16 shows the HDL code for calculating the factorial.
LISTING 3.16 HDL Code for Calculating the Factorial of Positive Integers: VHDL and Verilog
VHDL Description.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--The above library statements can be omitted;
--however no error if it is not omitted.
--The basic VHDL has type “natural.”
entity factr is
port(N : in natural; z : out natural);
end
factr;
architecture factorl of factr
begin
process (N)
variable y, i : natural;
begin
y := 1;
i := 0;
while (i < N) loop i := i + 1;
y := y i;
end loop; z <= y;
end process; end factorl;
Verilog Description module factr (N, z); input [5:0] N;
output [15:0] z;
reg [15:0] z;
/ Since z is an output, and it will appear inside “always,” then Z has to be declared “reg” /
integer i; always @ (N) begin
z = 16’d1; i = 0;
while (i < N) begin
i = i + 1; z = i z;
end
end
endmodule
***-----***
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