IET Power Electronics

Research Article

Fast voltage detection method for grid-tied ISSN 1755-4535

Received on 14th September 2016
Revised 10th April 2017
renewable energy generation systems under Accepted on 25th April 2017
E-First on 24th July 2017
distorted grid voltage conditions doi: 10.1049/iet-pel.2016.0738
www.ietdl.org

Furong Xiao1, Lei Dong1 , Li Li2, Xiaozhong Liao1

1School of Automation, Beijing Institute of Technology, Beijing, People's Republic of China
2Faculty of Engineering and Information Technology, University of Technology, Sydney, Australia
E-mail: correspondent_dong@163.com

Abstract: A fast voltage detection method to assist with the low-voltage ride-through operation of grid-tied renewable energy
generation systems is proposed in this study. It is designed to detect every phase voltage, so that it can be applied in both three-
phase and single-phase applications. The whole voltage detection approach consists of two stages, the pre-filtering stage and
the voltage detection stage. In the pre-filtering stage, a cascaded delayed signal cancellation (CDSC) module and a low-pass
filter are connected in series to filter low-order harmonics and high-frequency noises. For eliminating the low-order harmonics of
interest, different types of CDSC methods are studied in detail. Subsequently, a new orthogonal signal generator is built to
calculate the voltage amplitude in the voltage detection stage. Finally, the proposed voltage detection method is verified by
experimental results.

1 Introduction Since the grid-tied converter is required to respond according to

Along with the increasing penetration of distributed renewable
energy generation systems, the grid stability and reliability are now
facing significant challenges [1]. Especially, during the grid fault
period, the behaviours of grid-tied converters have a significant
impact on the grid stability. For instance, sudden disconnection of
massive renewable power plants from the grid during voltage sag
faults may trigger more severe problems than the initial event such
as power outage and voltage flicker [2, 3]. Hence, many countries
have enacted their grid codes to guide the operation of grid-tied
renewable power systems [4, 5]. These new grid codes require
grid-tied converters be capable of low-voltage ride-through
(LVRT) when suffering grid voltage sag.
Fig. 1a shows the Chinese LVRT standard for large-capacity
grid-tied photovoltaic (PV) inverters. As shown, PV inverters
should stay connected to the grid in the shaded area. Besides, they
are also required to provide reactive power for dynamic network
support during the fault period and in the recovery process [6]. The
E.ON code shown in Fig. 1b defines the amount of the reactive
current injected to the grid during LVRT. The injection of reactive
power should be sufficiently fast, e.g. the PV system should deliver
the required reactive power within 30 ms [7]. Moreover, faster
detection of the voltage sag means that the grid-tied converter has
more response time, which is beneficial for the converter safety.
Therefore, the voltage variation ratio should be detected as fast as
possible.
the variation of either line voltage or phase voltage [7], the adopted
voltage detection method should have the capability of detecting
each phase voltage. Consequently, conventional voltage detection
approaches based on three-phase phase-locked loop (PLL) such as
D axis and Q axis (DQ) transformation method [8] cannot satisfy
the new requirements. Several other voltage detection methods
have been proposed in the literature, e.g. the root mean square
(RMS) voltage detection [9], the peak voltage detection [10], and
the discrete Fourier transform [11–13], whose detection speed is
too slow for LVRT operation. The peak voltage detection method
maximally introduces half grid cycle delay, whereas both the RMS
and fast Fourier transform (FFT) related methods induce one grid
cycle delay [14]. Furthermore, for ensuring an accurate detection of
the grid voltage under distorted conditions, the low-order
harmonics and unbalanced variations of the grid voltage should be
considered during the design. The current solutions are to either
insert a digital filter into the PLLs [15–17], or use the positive and
negative component separation methods [18, 19] to extract the
fundamental voltage component for calculating the grid voltage.
Note that detecting each phase voltage separately with three
independent single-phase PLLs is also valid for unbalanced voltage
variations. However, as a matter of fact, the settling time of PLL-
related methods generally cannot be less than one grid cycle, so
that PLLs are not suitable for detecting the grid voltage variation
ratio during LVRT operation. Ma et al. [14] present a new

Fig. 1 LVRT requirements

(a) China: company and grid state grid (Q/GDW) 617–2011, (b) E.ON code for LVRT

IET Power Electron., 2017, Vol. 10 Iss. 12, pp. 1487-1493 1487
© The Institution of Engineering and Technology 2017

Fig. 2 Phase voltage of the three-phase power grid
(a) Voltage detection approach for three-phase systems, (b) Proposed voltage detection method for each phase
detection method which is to detect both the maximum and zero
voltage points. Its response time is affected by the position at
which the voltage variation occurs, and the largest time delay is
10.1 ms.
In light of the above-mentioned issues, a new voltage detection
scheme, which can provide fast detection speed and also high
accuracy, is proposed in this paper. The presented method is not
only applicable to single-phase power systems, but also can be
used for detecting every phase voltage of the three-phase power
grid as shown in Fig. 2. In this manner, the magnitude of each
phase voltage can be accurately obtained even if unbalanced grid
faults happen in three-phase power systems.
To facilitate the magnitude estimation of the single-phase
voltage, an extra orthogonal signal to the original single-phase
voltage is generally generated. In the literature, the second-order
generalised integrator (SOGI) [20], the quarter-cycle delay [21],
and the first-order differential method [22, 23] are the most popular
orthogonal signal generator (OSG) methods. SOGI provides low
computation burden and strong filtering capability. However, it
exhibits a settling time of more than half of the fundamental period
[24]. Although the quarter-cycle delay technique is easy to
implement and also fast, it still introduces a time delay of one
fourth of the fundamental period. Comparatively, the first-order
differential method may be the fastest OSG. However, higher
accuracy of the first-order differential method requires higher
sampling frequency, yet the high-frequency noise in the sampling
process will be further amplified inevitably. To deal with these
issues, a new OSG, which can provide fast dynamic response,
high-noise immunity, and also high accuracy, is first presented in
this paper.
Nowadays, with more and more non-linear loads are connected
to modern power systems, low-order harmonics are inevitably
present in the grid voltage, especially in a weak power grid. To
extend the developed OSG to distorted conditions, the delayed
signal cancellation (DSC) technique, which has the advantages of
easy implementation and less computational burden [25–27], is
used as a pre-filter for common odd harmonics rejection
consideration. To be specific, a cascaded DSC (CDSC) module and
a low-pass filter are designed in the pre-filtering stage to eliminate
the concerned low-order odd harmonics and high-frequency noise,
respectively. Different from previous DSC operators, a new DSC
operator, which can be designed more flexibly and has the potential
to reduce the involved time delays, is introduced in this paper. With
V a(t) + V a(t − T 1) V ap sin(ωt) + V ap sin(ωt − ωT 1)
V 1(t) = = = V ap sin(ωt − 0.5ωT 1)
λ1
V a(t) − V a(t − T 1) V ap sin(ωt) − V ap sin(ωt − ωT 1)
V 2(t) = = = V ap cos(ωt − 0.5ωT 1)
λ2
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the help of the proposed OSG and also the new DSC operators, the
grid voltage can be fast and accurately detected in this paper.
2 Proposed voltage detection method under ideal
conditions
Given the same detection principle of each phase voltage in Fig. 2,
only the phase a V a(t) = V ap sin(ωt), where V ap is the voltage
amplitude and ω is the angular frequency, is used for illustration in
this paper. Generally, an orthogonal signal V β(t) with respect to the
original voltage signal V a(t) can be generated, so that the
magnitude of the single-phase grid voltage can be given by
V ap = V a2 + V β2 . To achieve this goal, a new OSG algorithm with
high-noise immunity and high accuracy in a wide range of
sampling frequencies is proposed in this section and can be
expressed as (see (1)) in which T 1 is a predetermined delay time,
and λ1 and λ2 are functions of T 1 and the grid angular frequency ω.
Different from previous OSGs, the developed OSG creates an
orthogonal frame of V ap sin(ωt − 0.5ωT 1) and V ap cos(ωt − 0.5ωT 1)
instead of V ap sin(ωt) and V ap cos(ωt). It is worth noting that (1) is
obtained by rigorous mathematical deduction without any
approximation, so that the accuracy of the proposed OSG is
independent of the sampling frequency (see Fig. 3). From (1), the
magnitude of the grid voltage can be achieved as V ap = V 12 + V 22.
Note that T 1 is the only parameter which needs to be tuned in
the proposed OSG. In what follows, the design considerations of T 1
are derived from the viewpoint of high-frequency noise
consideration. Considering the high-frequency random noise V x in
~
the sampling process as V a(t) = V a(t) + V x(t), (1) can be rewritten
as (see (2))
The physical quantities with superscript ∼ in this paper indicate
the existence of random noise. In (2) (see (3)) where k1 and k2 are
the possible maximal noise amplification factors of the developed
OSG in the worst condition. Since T 1 is designed below 0.25 grid
periods for the sake of fast dynamic response, k1 is smaller than k2,
so that k2 is mainly considered during the tuning of T 1. Obviously,
k2 decreases remarkably and the response time increases linearly
with the increased T 1. Consequently, it is necessary to find a good
compromise between noise reduction and response speed.
Industrial experience suggests that a noise amplification factor of
10 can fully meet the precision requirement in most cases [28].
2 cos(0.5ωT 1)
(1)
2 sin(0.5ωT 1)
IET Power Electron., 2017, Vol. 10 Iss. 12, pp. 1487-1493
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mentioned voltage detection. In practise, the allowable variation
range of the grid frequency is generally small in the normal
operation mode such as 0.2 Hz in China, which has negligible
influence on the accuracy of the developed voltage detection
method. Hence, this paper mainly focuses on the grid voltage
variation cases.

3 Proposed voltage detection method under

distorted conditions
To accurately detect the magnitude of grid voltage regardless of
low-order harmonics, a CDSC module-based pre-filtering stage is
used for filtering the sampled grid voltage signal before sending it
to the above-mentioned OSG. Similar to [14, 29], the low-order
harmonics 5th, 7th, 11th, and 13th are considered in this paper
because they are generally the dominant low-order harmonics in
the power grid. Although the developed pre-filtering stage is
designed for rejecting the low-order harmonics 5th, 7th, 11th, and
13th, it is not restrictive and can be easily extended to more
harmonics. In what follows, three different CDSC methods are
discussed and compared.

3.1 CDSC method I

Fig. 3 Orthogonal signals constructed by the proposed OSG under
different sampling frequencies
(a) Generated Signal V 1, (b) Generated signal V 2
Considering the required fast detection of voltage sags during
LVRT applications, T 1 is set as 1 ms, so that k1 = 1.01 and
k2 = 6.39. Namely, the response time of the designed OSG is 1 ms
in this work. The possible high-frequency noises can be rejected by
a low-pass filter with 1 kHz cut-off frequency in the pre-filtering
stage as shown in Fig. 2b. In addition to the above-mentioned high-
frequency noise, the rejection of the possible low-order voltage
harmonics is also our concern. In this work, the proposed OSG is
mainly designed for fast generating the required orthogonal signals,
while the rejection of low-order harmonics is conducted in the pre-
filtering stage.
Note that (1) is derived on the premise of known grid frequency
ω. Generally, the grid frequency is often measured with a PLL in
grid-tied power converters. Therefore, it is reasonable to assume
the grid frequency is known for implementing the proposed OSG.
The frequency ω for calculating λ1 and λ2 should only update after
the PLL settles to a new steady state. Consequently, the dynamic
process of the PLL in response to voltage variations (amplitude or
phase angle jump) does not affect the performance of the above-
The CDSC method I (see Fig. 4) based on the original DSC
(ODSC) [25–27] is used for eliminating the low-order harmonics
of interest. For the sake of simplicity, the grid voltage with only the
nth odd harmonic as V a(t) = V ap sin(ωt + θ1) + V n sin(nωt + θn) is
assumed for illustrating the principle of the operator ODSCn. The
output signal ODSCno of the operator ODSCn is given by
Tf
ODSCno(t) = V a(t) + V a(t − td) = V a(t) + V a t −
2n
= V ap sin(ωt + θ1) + V n sin(nωt + θn)
π (4)
+V ap sin ωt + θ1 − + V n sin(nωt + θn − π)
n
π π
= 2V ap cos sin ωt + θ1 −
2n 2n
in which T f is the fundamental period and td is the delay time. It is
clear that the output signal is free from the nth odd harmonic, while
the fundamental component suffers from fixed amplitude and phase
angle shifts. Note that, the nth odd harmonic can be removed by
ODSCn only when td = T f /(2n). Moreover, each ODSC block can
only remove one specific order odd harmonic, so that four ODSC
operators are required in the CDSC method I. The total delay time
of the CDSC method I is 0.255T f , i.e. 5.1 ms for a 50 Hz power
system (the grid frequency is assumed to be always 50 Hz in the
following discussion).

~ ~
~ V a(t) + V a(t − T 1) [V ap sin(ωt) + V x(t)] + [V ap sin(ωt − ωT 1) + V x(t − T 1)]
V 1(t) = =
2 cos(0.5ωT 1) 2 cos(0.5ωT 1)
V x(t) + V x(t − T 1)
= V ap sin(ωt − 0.5ωT 1) +
2 cos(0.5ωT 1)
= V ap sin(ωt − 0.5ωT 1) + V 1n
~ ~ (2)
~ V a(t) − V a(t − T 1) [V ap sin(ωt) + V x(t)] − [V ap sin(ωt − ωT 1) + V x(t − T 1)]
V 2(t) = =
2 sin(0.5ωT 1) 2 sin(0.5ωT 1)
V x(t) − V x(t − T 1)
= V ap cos(ωt − 0.5ωT 1) +
2 sin(0.5ωT 1)
= V ap cos(ωt − 0.5ωT 1) + V 2n

|V x(t) + V x(t − T 1)| |V x(t) | + | V x(t − T 1)| |V x|

|V 1n| = ≤ ≤ = k1 | V x|
|2 cos(0.5ωT 1)| |2 cos(0.5ωT 1)| |cos(0.5ωT 1)|
(3)
|V x(t) − V x(t − T 1)| |V x(t) | + | V x(t − T 1)| |V x|
|V 2n| = ≤ ≤ = k2 | V x|
|2 sin(0.5ωT 1)| |2 sin(0.5ωT 1)| |sin(0.5ωT 1)|
IET Power Electron., 2017, Vol. 10 Iss. 12, pp. 1487-1493 1489
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Fig. 4 Three types of CDSC methods for eliminating the 5th, 7th, 11th, and 13th harmonics

3.2 CDSC method II
In addition to the ODSC operator, the proposed DSC (PDSC)
operator PDSCn for cancelling the nth odd harmonic is first
discussed. Also, the input
V a(t) = V ap sin(ωt + θ1) + V n sin(nωt + θn) is used to illustrate the
principle of the operator PDSCn as (see (5))
It is obvious that the nth odd harmonic can be eliminated for
any given td > 0. A close observation of (4) and (5) reveals that
ODSCn is a special case of PDSCn with td = T f /(2n). Next, how to
design PDSCn for eliminating the nth odd harmonic with less time
delay is given in detail. Considering the high-frequency random
~ eliminate only the nth odd harmonic, so that four cascaded
noise V x in the sampling process as V a(t) = V a(t) + V x(t), (5) can
be rewritten as (see (6))
The ratio of the random noise to the amplitude of the
fundamental component in (6) is defined as
|V x(t) + V x(t − td) − 2 cos(0.5nωtd)V x(t − 0.5td)|
F(td, n) =
|2[cos(0.5ωtd) − cos(0.5nωtd)]V ap|
(7)
|V x | + | V x | + | 2cos(0.5nωtd) | | V x| |V x|
≤ = k3(td, n)
|2[cos(0.5ωtd) − cos(0.5nωtd)]V ap| V ap
where k3(td, n) is termed as the possible maximal noise
amplification factor of PDSCn in the worst case. While in ODSCn
(see (8))
Fig. 5 shows the relationship of the noise amplification factor
versus the delay time. It is clear that the noise amplification factor
k3(td, n) of PDSCn decreases with the increased td in the shown
range. In terms of LVRT operation, a faster detection of the grid
voltage variation ratio is preferred. Therefore, k3 is set to around 3,
so that the total delay time of four cascaded PDSCn (n = 5, 7, 11,
13) operators is 3.43 ms, which is 1.67 ms less than that (5.1 ms) of
the CDSC method I. However, the possible maximal noise
amplification factor of such four PDSC blocks is 81, which may be
not preferred in practise. Alternatively, the 5th and 7th harmonics
are eliminated with PDSC5 and PDSC7, respectively, and the 11
and 13th harmonics are removed with ODSC11 and ODSC13,
respectively, as shown in Fig. 4. This method provides 4 ms time
delay with the total noise amplification factor of 9, and is called the
CDSC method II.
3.3 CDSC method III
In the above discussion, either ODSCn or PDSCn is designed to
operators are required for cancelling the 5th, 7th, 11th, and 13th
harmonics. In this section, a new harmonic elimination operator
PDSCn&m with specifically designed delay factor is introduced to
remove the nth and mth odd harmonics (m > n) simultaneously. As
a result, the number of cascaded blocks can be reduced by half,
thus reducing the computation and delay time. The principle of
PDSCn&m is illustrated as (see (9))
As mentioned above, the nth harmonic can be removed
regardless of td, whereas the mth harmonic can be eliminated only
if
cos(0.5mωtd) − cos(0.5nωtd) = 0 (10)
From (10), to eliminate both the nth and mth harmonics within
the same operator PDSCn&m, the corresponding delay time can be
derived as
jT f jT f
td = or , m > n, j = 1, 2, 3, … (11)
0.5(n + m) 0.5(m − n)

PDSCno(t) = V a(t) + V a(t − td) − 2 cos(0.5nωtd)V a(t − 0.5td)

= V ap sin(ωt + θ1) + V n sin(nωt + θn)
+V ap sin(ωt + θ1 − ωtd) + V n sin(nωt + θn − nωtd)
(5)
−2cos(0.5nωtd)[V ap sin(ωt + θ1 − 0.5ωtd)
+V n sin(nωt + θn − 0.5nωtd)]
= 2[cos(0.5ωtd) − cos(0.5nωtd)]V ap sin(ωt + θ1 − 0.5ωtd)

~ ~ ~ ~
PDSCno(t) = V a(t) + V a(t − td) − 2 cos(0.5nωtd)V a(t − 0.5td)
= 2[cos(0.5ωtd) − cos(0.5nωtd)]V ap sin(ωt + θ1 − 0.5ωtd) (6)
+[V x(t) + V x(t − td) − 2cos(0.5nωtd)V x(t − 0.5td)]

~ ~ ~ Tf π π Tf
ODSCno(t) = V a(t) + V a t − = 2V ap cos sin ωt + θ1 − + Vx + Vx t −
2n 2n 2n 2n
(8)
Tf |V x + V x t − (T f /2n) | |V x| Tf |V x|
F ,n = ≤ = k3 ,n
2n |2 cos(π/2n)V ap| |cos(π/2n) | V ap 2n V ap
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can reduce the computational load compared with the CDSC I and
II methods. In addition, the total delay time of the CDSC method
III is 4.4 ms which is 0.7 ms less than that of the CDSC method I.
From (7), the noise amplification factors of PDSC5&13 and
PDSC7&11 can be derived as

Tf (1 + | cos(0.5nωtd) | )
k3 ,5 =
9 |cos(0.5ωtd) − cos(0.5nωtd)|
(1 + | cos(5π/9) | )
= = 1.054, PDSC5&13
|cos(π/9) − cos(5π/9)|
(13)
Tf (1 + | cos(0.5nωtd) | )
k3 , 7 =
9 |cos(0.5ωtd) − cos(0.5nωtd)|
Fig. 5 Noise amplification factor versus the delay time
(1 + | cos(7π/9) | )
= = 1.035, PDSC7&11
|cos(π/9) − cos(7π/9)|

The noise amplification factors of the designed PDSC5&13 and

Fig. 6 Simulation results of PDSC5&13 and the cascaded block with
PDSC5 and PDSC13
For the purpose of short time delay, the delay time should be
chosen as
2π Tf
td = = (12)
0.5(n + m)ω 0.5(n + m)
Therefore, to eliminate the 5th and 13th harmonics, the delay
time of PDSC5&13 should be T f /9. The simulation results of
PDSC5&13 and the cascaded block with two separate operators
PDSC5 and PDSC13 are given in Fig. 6. The delay times of PDSC5
and PDSC13 are chosen as T f /10 and T f /26, respectively. It can be
observed that these two methods can effectively eliminate the 5th
and 13th harmonics, while holding different voltage gains for the
fundamental components
V α = sin(100πt) + 0.2 sin(500πt) + 0.1 sin(1300πt)
Similarly, PDSC7&11 with td = T f /9 can remove both the 7th
and 11th harmonics. Consequently, only two cascaded blocks,
PDSC5&13 and PDSC7&11, are enough for eliminating the 5th, 7th,
11th, and 13th harmonics, and this method is named as the CDSC
method III. With half number of cascaded blocks, this approach
PDSC7&11 are close to one, which means the CDSC method III has
nearly the same noise rejection capability as the CDSC method I
according to Fig. 5.
Note that the operator PDSCn in the CDSC method II is used
for only eliminating the nth odd harmonic, so that the
corresponding delay time td can be selected flexibly. As mentioned
above, the nth odd harmonic can be eliminated for any given
td > 0. However, the operator PDSCn&m in the CDSC method III is
designed for eliminating both the nth and mth harmonics, so that
the corresponding delay time cannot be selected free like that in the
CDSC II method and must be td = 2T f /(n + m).
It follows from (4), (5), and (9) that the pre-filtering stage
introduces a fixed magnitude shift on the fundamental component,
which can be entirely compensated by using a factor kamp as shown
in Fig. 2b. The compensating factors for different CDSC methods
can be derived from (4), (5), and (9) and are given by (see (14))
3.4 Comparison with previous voltage detection methods
The comparison results between previous voltage detection
methods and the proposed ones with different CDSC methods in
terms of the response time are listed in Table 1 for the condition of
three-phase unbalanced voltage drop with low-order harmonics.
The proposed method can estimate the magnitude of the grid
voltage within 6.6 ms (CDSC I) or 5.5 ms (CDSC II) or 5.9 ms
(CDSC III) when considering the dominant low-order harmonics
5th, 7th, 11th, and 13th. It is worth noting that the response time
mentioned here is obtained considering both the pre-filtering stage
and the voltage detection stage. In terms of the dynamic
performance, the proposed voltage detection methods perform
better than most of the previous ones which can provide accurate
voltage measurement under distorted conditions.

V a(t) = V ap sin(ωt + θ1) + V n sin(nωt + θn) + V m sin(mωt + θm)

PDSCn&mo(t) = V a(t) + V a(t − td) − 2 cos(0.5nωtd)V a(t − 0.5td)
= V ap sin(ωt + θ1) + V n sin(nωt + θn) + V m sin(mωt + θm)
V ap sin(ωt + θ1 − ωtd) + V n sin(nωt + θn − nωtd)
+
+V m sin(mωt + θm − mωtd)
V ap sin(ωt + θ1 − 0.5ωtd) + V n sin(nωt + θn − 0.5nωtd)
−2 cos(0.5nωtd) (9)
+V m sin(mωt + θm − 0.5mωtd)
= 2 cos(0.5ωtd) − cos(0.5nωtd) V ap sin(ωt + θ1 − 0.5ωtd)
+2 cos(0.5nωtd) − cos(0.5nωtd) V n sin(nωt + θm − 0.5nωtd)
+2 cos(0.5mωtd) − cos(0.5nωtd) V m sin(mωt + θm − 0.5mωtd)
= 2 cos(0.5ωtd) − cos(0.5nωtd) V ap sin(ωt + θ1 − 0.5ωtd)
+2 cos(0.5mωtd) − cos(0.5nωtd) V m sin(mωt + θm − 0.5mωtd)
IET Power Electron., 2017, Vol. 10 Iss. 12, pp. 1487-1493 1491
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Table 1 Detection time comparison of different methods considering low-order harmonic distortion
Detection methods FFT-based methods [11–13] RMS method [9] Method [14] Proposed method
CDSC I CDSC II CDSC III
response times 20 ms 20 ms 5–10.1 ms 6.6 ms 5.5 ms 5.9 ms

Fig. 7 Experimental results of the proposed voltage detection method

(a) CDSC method I, (b) CDSC method II, (c) CDSC method III

4 Experimental results
The proposed voltage detection method is verified experimentally
on a digital signal processor chip TMS30F28335-based platform.
The normal voltage amplitude is 310 V and the dropped voltage
amplitude is set to 200 V. Along with the voltage amplitude drop,
the 5th (6%), 7th (4.8%), 11th (4%), and 13th (3.2%) voltage
harmonics are added for testing the harmonic rejection
performance of the developed voltage detection method. All the
operations are conducted with 10 kHz sampling frequency. The
corresponding experimental results are shown in Fig. 7. It can be
observed that the detection method with CDSC I, CDSC II, or
CDSC III can fast detect the voltage amplitude under generally
distorted grid voltages. The response time of the approach with
PDSC (CDSC II or CDSC III) is less compared with the one

1
kamp = = 0.0686, CDSCI
16 cos(π/10)cos(π/14)cos(π/22)cos(π/26)
1
kamp =
4[cos(7π/100) − cos(7π/20)][cos(9π/200) − cos(63π/200)]
(14)
1
× = 0.2021, CDSCII
4 cos(π/22)cos(π/26)
1
kamp = = 0.1316, CDSCIII
4[cos(π/9) − cos(5π/9)][cos(π/9) − cos(7π/9)]
1492 IET Power Electron., 2017, Vol. 10 Iss. 12, pp. 1487-1493
© The Institution of Engineering and Technology 2017

(CDSC I) based on ODSC. The achieved reduction of the delay
time by using PDSC is limited in this paper; however, the freedom
to design the time delay as well as the possibility to reduce the
number of cascaded modules makes PDSC interesting for
applications related to harmonics cancellation. As shown in Fig. 7,
it can be guaranteed that the generated signals V1 and V2 are
mutually orthogonal and clear even if the input grid voltage
contains low-order harmonics. Note that V1 is not in phase with the
fundamental component of the input signal due to the phase delays
caused by the pre-filtering stage and the proposed OSG.
5 Conclusions
This paper presents a fast voltage detection method to assist with
the LVRT operation of grid-tied renewable energy generation
systems. With the proposed approach, the magnitude of each phase
voltage in three-phase power systems can be measured in a fast and
accurate way regardless of unbalanced grid faults and low-order
odd harmonics. Also, the developed voltage detection method can
be applicable to single-phase power systems. First, a new OSG
with relatively fast response speed is analysed in detail. Second,
based on the concept of DSC, a novel harmonic cancellation block
is designed, so that both the delay time and number of the CDSC
blocks required for eliminating the low-order odd harmonics of
interest can be reduced. Finally, the presented voltage detection
method is verified by experimental results.
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[20] Ciobotaru, M., Teodorescu, R., Blaabjerg, F.: ‘A new single-phase PLL
structure based on second order generalized integrator’. Proc. 37th IEEE
PESC, 2006, pp. 1511–1516
[21] Zhang, R., Cardinal, M., Szczesny, P., et al.: ‘A grid simulator with control of
single-phase power converters in D–Q rotating frame’. Proc. IEEE Power
Electronics Specialists Conf., 2002, pp. 1431–1436
[22] Luo, A., Chen, Y.D., Shuai, Z.K., et al.: ‘An improved reactive current
detection and power control method for single-phase photovoltaic grid-
connected DG system’, IEEE Trans. Energy Convers., 2013, 28, (4), pp. 823–
831
[23] Roshan, A., Burgos, R., Baisden, A.C., et al.: ‘A D-Q frame controller for a
full-bridge single phase inverter used in small distributed power generation
systems’. Proc. IEEE Applied Power Electronics Conf., 2007, pp. 641–647
[24] Kulkarni, A., John, V.: ‘A novel design method for SOGI-PLL for minimum
settling time and low unit vector distortion’. Industrial Electronics Society,
IECON 2013-39th Annual Conf. of the IEEE, 2013, pp. 274–279
[25] Neves, F.A.S., Cavalcanti, M. C., de Souza, H. E. P., et al.: ‘A generalized
delayed signal cancellation method for detecting fundamental-frequency
positive-sequence three-phase signals’, IEEE Trans. Power Deliv., 2010, 25,
(3), pp. 1816–1825
[26] Svensson, J., Bongiorno, M., Sannino, A.: ‘Practical implementation of
delayed signal cancellation method for phase-sequence separation’, IEEE
Trans. Power Deliv., 2007, 22, (1), pp. 18–26
[27] Wang, Y.F., Li, Y.W.: ‘Grid synchronization PLL based on cascaded delayed
signal cancellation’, IEEE Trans. Power Electron., 2011, 26, (7), pp. 1987–
1997
[28] Xiong, L., Zhuo, F., Wang, F., et al.: ‘A fast orthogonal signal-generation
algorithm characterized by noise immunity and high accuracy for single-
phase grid’, IEEE Trans. Power Electron., 2016, 31, (3), pp. 1847–1851
[29] Wang, Y.F., Li, Y.W.: ‘Three-phase cascaded delayed signal cancellation PLL
for fast selective harmonic detection’, IEEE Trans. Ind. Electron., 2013, 60,
(4), pp. 1452–1463

6 References
[1] Yang, S., Lei, Q., Peng, F.Z., et al.: ‘A robust control scheme for grid-
connected voltage-source inverters’, IEEE Trans. Ind. Electron., 2011, 58, (1),
pp. 202–212
[2] Kovanen, K.O.: ‘Photovoltaics and power distribution’, Renew. Energy Focus,
2013, 14, (3), pp. 20–21
[3] Bae, Y., Vu, T.K., Kim, R.Y.: ‘Implemental control strategy for grid
stabilization of grid-connected PV system based on German grid code in
symmetrical low-to-medium voltage network’, IEEE Trans. Energy Convers.,
2013, 28, (3), pp. 619–631
[4] E.ON Netz GmbH: ‘Grid code high and extra high voltage Bayreuth’ (E.ON
Netz GmbH, Germany, 2006)
[5] Energinet: ‘Regulation TF 3.2.5 wind turbines connected to grids with
voltages above 100 kV’ (Denmark, 2010)
[6] Marinopoulos, A., Papandrea, F., Reza, M., et al.: ‘Grid integration aspects of
large solar PV installations: LVRT capability and reactive power/voltage
support requirements’. IEEE PowerTech Conf., Trondheim, 2011, pp. 1–8
[7] ‘Technical requirements for connecting photovoltaic power station to power
system’, Technical Report, GB/T 19964-2012, China, December 2012
[8] Kumsuwan, Y., Sillapawicharn, Y.: ‘A fast synchronously rotating reference
frame-based voltage sag detection under practical grid voltages for voltage
sag compensation systems’. Proc. Sixth IET Int. Conf. Power Electronics,
Machines, and Drives, 2012, pp. 1–5
[9] Styvaktakis, E., Bollen Seniorand, M.H.J., Gu, I.Y.J.: ‘Automatic
classification of power system events using rms voltage measurements’. Proc.
Power Engineering Society Summer Meeting, 2002, pp. 824–829
[10] Naidoo, R., Pillay, P.: ‘A new method of voltage sag and swell detection’,
IEEE Trans. Power Deliv., 2007, 22, (2), pp. 1056–1063
[11] Zou, W.H., Su, S.P.: ‘Voltage flicker detection based on wavelet Fourier
transform’. Proc. Int. Conf. Electrical and Control Engineering, 2011, pp.
4218–4220
[12] Jacobsen, E., Lyons, R.: ‘The sliding DFT’, IEEE Signal Process. Mag., 2003,
20, (2), pp. 74–80
[13] Jacobsen, E., Lyons, R.: ‘An update to the sliding DFT’, IEEE Signal Process.
Mag., 2004, 21, (1), pp. 110–111
[14] Ma, C., Gao, F., He, G, et al.: ‘A voltage detection method for the voltage
ride-through operation of renewable energy generation systems under grid
voltage distortion conditions’, IEEE Trans. Sustain. Energy, 2015, 6, (3), pp.
1131–1139
[15] Wang, Y.F., Li, Y.W.: ‘Analysis and digital implementation of cascaded
delayed-signal-cancellation PLL’, IEEE Trans. Power Electron., 2011, 26, (4),
pp. 1067–1080
[16] Lee, K.J., Lee, J.P., Shin, D., et al.: ‘A novel grid synchronization PLL
method based on adaptive low-pass notch filter for grid-connected PCS’,
IEEE Trans. Ind. Electron., 2014, 61, (1), pp. 292–301
[17] Golestan, S., Ramezani, M., Guerrero, J.M., et al.: ‘Moving average filter
based phase-locked loops: performance analysis and design guidelines’, IEEE
Trans. Power Electron., 2014, 29, (6), pp. 2750–2763
[18] Rodriguez, P., Pou, J., Bergas, J.: ‘Decoupled double synchronous reference
frame PLL for power converters control’, IEEE Trans. Power Electron., 2007,
22, (2), pp. 584–592
[19] Yazdani, D., Mojiri, M., Bakhshai, A., et al.: ‘A fast and accurate
synchronization technique for extraction of symmetrical components’, IEEE
Trans. Power Electron., 2009, 24, (3), pp. 674–684

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© The Institution of Engineering and Technology 2017