DEPT MUTHAYAMMAL ENGINEERING

Students Course Project Summary COLLEGE2016-

(An Autonomous Institution)
[SCPS] 2020
(Approved by AICTE, New Delhi, Accredited by NAAC & Affiliated to Anna University)
Rasipuram - 637 408, Namakkal Dist., Tamil Nadu

1. Mallika A
Name of the Students 2. Mamatha C
1
(Max. of 4) 3. Nirmala S

E- Mail ID Contact No
mallikaamirthalingam1999@gmail.co
9080577672
m
2 Students’ Contact Details mamathachandran555@gmail.com 9791743824
nirmalas27061999@gmail.com 6385282083

3 Project Guide Name Dr. R. Praveena Branch ECE

Project is done in the Industry

Department (In House) or
4  In House
Industry. If industry project,
Name of the industry
Project Title:
5
Adaptive clock gating for sequential RAM

6 Project Progress Reviewed by

Description of the Project

Objectives:
Clock gating is an efficient technique for reducing dynamic power in sequential circuits. It saves power
by partitioning the main clock and distributing the clock to the logic blocks only when the is a need for
those blocks to be activated. Synchronous circuits show reduced dynamic power dissipation for
effective clock gating implementations. For reducing dynamic power dissipation data driven clock
gating is a popular technique which is used in many synchronous circuits. In a sequential circuit when a
logic unit is clock, its underlying sequential elements will receive the clock signal regardless of whether
or not they will toggle in the next cycle. The Scaling of CMOS technology has continued due to ever
increasing demand of grater performance with low power consumption. This demand has demand has
grown further by the portable and battery operated device market. These strategies are used to increase
the flexibility of an up-to-date SPI master/slave implementation following by the analysis of power
reduction achieved.
Brief Description about the Project:

Clock gating technology can efficiently reduce the dynamic power waste by using a control signal to
enable and disable the clock. Clock-gating essentially disables the clock to a module whenever the
module is not being used, which avoids power dissipation due to unnecessary charging and discharging
of the unused circuits. Effective clock-gating, however, requires a methodology that determines when
the circuits needed to be gated, and for how long, which usually needs to be controlled manually by
user. But cache idle state is transparent to user, which means it is unknown to users, therefore,
traditional clock gating technology could not be applied to cache power optimization efficiently.
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power
dissipation, by removing the clock signal when the circuit is not in use. Clock gating saves power by
pruning the clock tree, at the cost of adding more logic to a circuit. Pruning the clock disables portions
of the circuitry so that the flip-flops in them do not have to switch states. Switching states consumes
power. When not being switched, the switching power consumption goes to zero, and only leakage
currents are incurred.
Although asynchronous circuits by definition do not have a "clock", the term perfect clock gating is used
to illustrate how various clock gating techniques are simply approximations of the data-dependent
behavior exhibited by asynchronous circuitry. As the granularity on which one gates the clock of a
synchronous circuit approaches zero, the power consumption of that circuit approaches that of an
asynchronous circuit: the circuit only generates logic transitions when it is actively computing.

Clock gating works by taking the enable conditions attached to registers, and uses them to gate the
clocks. A design must contain these enable conditions in order to use and benefit from clock gating. This
clock gating process can also save significant die area as well as power, since it removes large numbers
of muxes and replaces them with clock gating logic. This clock gating logic is generally in the form of
"integrated clock gating" (ICG) cells. However, the clock gating logic will change the clock tree structure,
since the clock gating logic will sit in the clock tree.

In order to generate a clock gating signal automatically, a CACG convenient to users is proposed here
by detecting the module’s current state and external request signal. Every module has three states:
BUSY, IDLE and END, where BUSY represents this module is currently in working state, IDLE indicates
that it is in idle state, and END is an intermediate state of conversion from BUSY to IDLE. The request
signal represents the external module’s reading or writing operation to this module. The history register
will record the last operation. Then the comparator will compare it with current operation to generate
the clock enable signal.

The simplest way to implement a delay buffer is to use shift registers. If the buffer length is and the
word-length is , then a total of DFFs are required, and it can be quite large if a standard cell for DFF is
used. In addition, this approach can consume huge amount of power since on the average binary signals

make transitions in every clock cycle. Though the SRAM-based delay buffers do away with many data
transitions, there still can be considerable power consumption in the SRAM address decoder and the
read/write circuits. Infact, since the memory words are accessed sequentially, we can use counter with
only one rotating active cell to point to the words for write-in and read-out. This method, known as the

pointer-based scheme. Traditional Programmable clock gating (PCG) is coarse controlled that a
module‟s input clock is disabled by controlling the clock-enable register in the program. When the
module is in idle state, the user can write zero to the clock-gating control register, and the clock enable
signal low.

Some latches do not have to be loaded on every clock cycle. For example, some functional block
containing latches may be idle for some period of time. In such cases, we can hold those clock inputs at
the opaque level and save the power associated with loading the latches with new values. An enable
signal is used to control when a latch is loaded. Assuming that the latches are loaded when their clock
inputs are high, the enable signal must not change while the clock is high in order to ensure proper
operation of the latches. The enable signal may be produced by either software or hardware. Once the
gated clock signal has been generated, it may be distributed to the set of latches to be idled. Of course,
some appropriate buffering may be needed if there are a large number of latches in the set.

Materials /Software Used for Implementation:

1. MODELSIM
2. QUARTUS II TOOL
MODEL SIM:

Model Sim is a multi-language HDL simulation environment by mentor graphics, for simulation of
hardware description languages such as VHDL, Verilog and SystemC. Simulation is performed using
the graphical user interface (GUI), or automatically using scripts.

QUARTUS II TOOL:

QUARTUS II Software provides several verification tools that allow you to analyze your design
operating in system and at system speed. It provides a complete, multiplatform design environment
that easily adapts to your specific design needs.

Budget Utilized with Details:

Budget utilized for this project is Rs. 12000 for Software and Simulation.
Outcomes:

In this paper, we presented Accidents are occurring frequently in highly traffic areas .Drivers drive
vigorously without caring the traffic. Intimation of driver about speed and accident prone zone is
necessary. It can be done by using speed controlling technology with the help of embedded system and
controller. This project is focused on “ speed control of vehicles “by detecting the accident prone zone.
The main objective is to design a Smart Display controller meant for Vehicle’s speed control and
monitors the zones, which can run on an embedded system accidents are occurs due to careless driving
and over speed in road. People do not bother about human lives. The accidents rates are increasing year
to year by more vehicles on to ground. The government has taken to many steps to prevent this kind of
things but it not enough.

Feasibility for Product Making:

In This model control the speed of the automobile has been demonstrated. The product system is very
simple which is durable and is of low cost. This project consumes less power. This system is easy to
implement on present system which ensures maximum safety for drivers, passengers, peoples. The
vehicle reduced according to the restricted area speed and Raising and falling of Hump based on the
speed of the vehicle are implemented. This has been developed to avoid road accidents due to over
speeding of the vehicles. This project also used in all type of vehicle field.

Mapping of Program Outcomes (POs) and Program Specific Outcomes (PSOs):

(Mark √ in the box)

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO 12 PSO1 PSO2 PSO3

Guide HoD Principal