1710 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO.

8, AUGUST 2007

A Wideband Digital-RF Modulator for 16

High Data Rate Transmitters
Albert Jerng, Member, IEEE, and Charles G. Sodini, Fellow, IEEE

Abstract—A wideband software-defined digital-RF modulator

16
targeting Gb/s data rates is presented. The modulator consists of
a 2.625-GS/s digital modulator, a 5.25-GHz direct digital-RF
converter, and a fourth-order auto-tuned passive LC RF band-
pass filter. The architecture removes high dynamic range analog
circuits from the baseband signal path, replacing them with
high-speed digital circuits to take advantage of digital CMOS
scaling. The integration of the digital-RF converter with an
RF bandpass reconstruction filter eliminates spurious signals
and noise associated with direct digital-RF conversion. An ef-
ficient passgate adder circuit lowers the power consumption of
the high-speed digital processing and a quadrature digital-IF
approach is employed to reduce LO feedthrough and image
spurs. The digital-RF modulator is software programmable to
support variable bandwidths, adaptive modulation schemes, and
multi-channel operation within a frequency band. A prototype
IC built in 0.13- m CMOS demonstrates a data rate of 1.2 Gb/s
using OFDM modulation in a bandwidth of 200 MHz centered at
5.25 GHz. In-band LO and image spurs are less than 59 dBc
without requiring calibration. The modulator consumes 187 mW
and occupies a die area of 0.72 mm2 .
Index Terms—Delta-sigma, digital-IF, DRFC, OFDM, quadra-
ture modulator, software radio, wideband.
I. INTRODUCTION
EXT-GENERATION wireless systems aim to provide
N high data rates on the order of 1 Gb/s in order to sup-
port demand for high-speed mobile Internet applications. In
addition to increasing channel bandwidths, wireless systems
are employing techniques such as orthogonal frequency-divi-
sion multiplexing (OFDM) and modulation schemes such as
64-QAM to pack more bits per hertz. The system choices lead
to higher signal-to-noise ratio (SNR) requirements and higher
peak-to-average power ratios (PAPR) in the signals. Thus,
higher dynamic range is required in the circuits.
The 802.11n standard for wireless local area networking
(WLAN) targets a maximum data rate of 540 Mb/s. UWB
system proposals under the 802.15.3a task group are targeting
data rates up to 1.32 Gb/s using channel bandwidths of 528 MHz
for short-range, high rate wireless personal area networks [1].
Recent allocation of over 5 GHz of contiguous bandwidth in
the unlicensed 60 GHz band enables transmission of much
higher data rates. The multitude of wireless standards requires
Manuscript received November 20, 2006; revised January 30, 2007. This
work was supported by the MIT Center for Integrated Circuits and Systems.
Chip fabrication was provided by IBM Microelectronics.
A. Jerng was with the Massachusetts Institute of Technology, Cambridge, MA
02139 USA. He is now with Broadcom, San Diego, CA 92127 USA.
C. G. Sodini is with the Massachusetts Institute of Technology, Cambridge,
MA 02139 USA.
Digital Object Identifier 10.1109/JSSC.2007.900255
0018-9200/$25.00 © 2007 IEEE
Fig. 1. Conventional and proposed modulator architectures.
distinct radio designs for each set of specifications. A wide-
band, programmable RF modulator with high dynamic range is
a key building block for a universal transmitter targeting future
high data rate systems.
The conventional I–Q modulator, shown in Fig. 1, consists
of a digital-to-analog converter (DAC), analog filter, and analog
mixer. The DAC and analog filter become more difficult to de-
sign as the bandwidth and dynamic range requirements of the
transmitter increase. At high frequencies, timing errors and non-
linear capacitances limit DAC dynamic range [2], rather than
static DC errors. Power consumption in the analog reconstruc-
tion filter increases proportionally to the signal bandwidth for
a constant dynamic range [3]. The scaling of CMOS transistors
and supply voltages creates further challenges from the stand-
point of dynamic range. Mismatch between I and Q paths and
DC offsets cause modulator image and local oscillator (LO)
leakage signals, respectively.
The proposed wideband digital-RF modulator, shown
in Fig. 1, consists of oversampling I and Q digital mod-
ulators, and a quadrature digital-RF converter with integrated
RF bandpass filter. The digital-RF modulator replaces high
dynamic range analog circuits with high-speed digital circuits,
and active analog lowpass filters with a passive RF bandpass
filter. In this architecture, no analog impairments are present
in the I–Q baseband signal path. Thus, analog design issues
such as noise/linearity tradeoffs, DC offsets, and I–Q matching
are eliminated. Unlike the conventional I–Q modulator, the
digital-RF modulator benefits from digital CMOS scaling since
the power and area of the high-speed modulators will de-
crease as channel lengths and supply voltages are reduced. The
digital-RF converter (DRFC) building block [4], [5] combines
the functionality of a DAC and mixer, and enables greater
integration. Passive RF filtering is attractive because it has high
dynamic range and consumes no power.
The fundamental difficulty with direct digital-RF conversion
[4], [5] is the transmission of spurs outside the signal band that
are difficult to filter at RF frequencies. The frequency spec-
trum of the digital input to the DRFC repeats at multiples of
the sampling frequency. Clock images and quantization noise
JERNG AND SODINI: A WIDEBAND DIGITAL-RF MODULATOR FOR HIGH DATA RATE TRANSMITTERS
Fig. 2. Quadrature digital-RF converter core.
are up-converted without any filtering besides the sinc response
associated with the zero-order hold in the digital-RF interface.
In previous work on direct digital-RF conversion [4]–[6], addi-
tional off-chip filtering is required to avoid transmitting out-of-
band spurs.
In this work, the spurious problem is solved through the in-
tegration of a high- passive LC bandpass filter into the load
of the digital-RF conversion circuit. As signal bandwidths in-
crease, active analog filters consume more power for a given
dynamic range, while on-chip passive LC bandpass filters be-
come feasible due to a reduction in required . Thus, direct dig-
ital-RF conversion is attractive for wideband systems.
The new contributions of this work are the application of the
direct DRFC concept towards wideband systems, and the inte-
gration of an auto-tuned RF bandpass filter and a high-speed
digital modulator in the designed digital-RF modulator.
Due to its wideband capability, the digital-RF modulator can be
software-defined to transmit multiple frequency channels within
a band, with variable bandwidths and modulation schemes while
using a fixed LO. The modulator can be used to transmit in a
band of spectrum on an adaptive basis, depending on wireless
channel conditions and interferers, or upon the specifications of
a given standard. In the following sections, the system and cir-
cuit design details will be discussed, experimental results will
be presented, and conclusions will be made.
II. MODULATOR ARCHITECTURE
A simplified schematic of the multi-bit DRFC core is shown
in Fig. 2. Each unit cell, similar to [5], consists of a current
source, a differential pair driven by an LO signal, and a differen-
tial current-steering switch. The converter cells share a common
cascode device that isolates the output signal from the switches,
preventing data-dependent switching that causes distortion. The
differential LO current in each unit cell is multiplied by 1 or
1, depending on the digital input bit. Summation of the unit
cell LO output currents yields a modulated RF signal that is
obscured by a large amount of quantization noise. RF band-
pass reconstruction filtering removes the out-of-band quantiza-
tion noise.
1711
Fig. 3. Aliasing problem in up-conversion.
The DRFC performs multiplication of the sampled and held
bits with the LO signal. In the frequency domain, this corre-
sponds to a convolution of the frequency spectra of the respec-
tive signals, as depicted in Fig. 3 for DC inputs. In digital-RF
conversion, aliasing of quantization noise and sampling clock
images can occur. Quantization noise and clock images from
the convolution with spill into the positive frequency
spectrum, corrupting the signal spectrum centered at . Like-
wise, noise and images from the convolution with spills into
the negative frequency spectrum. The only filtering that occurs
before the convolution is the sinc response associated with the
zero-order hold in the digital-RF interface.
Aliased clock images will appear as an image signal in the RF
passband, degrading the achievable image rejection of the mod-
ulator. The finite image rejection, however, is correctable. Since
the signal is known and the sinc transfer function is known, the
magnitude and phase of the aliasing clock images are known
as well. For moderate oversampling ratios, the image signal is
small, and pre-distortion of the digital input signal effectively
removes the aliasing images. Aliased quantization noise, on the
other hand, can degrade the in-band SNR of the signal. In order
to prevent degradation of SNR, the following condition must be
met between and :
(1)
By satisfying (1), only quantization noise notches will alias
into the RF passband, having negligible impact on in-band SNR.
In practice, device mismatches in the lower differential pair
cause leakage from the digital input port to the output. The
digital inputs contain large amounts of quantization noise at odd
multiples of . This noise leaks to the output and lies in the
signal passband when is chosen to be an odd multiple of
. Thus, (1) should be modified to
(2)
A. Co-Design of NTF and BPF
The dynamic range of a modulator is a function of its
oversampling ratio (OSR). In a RF modulator, the OSR can
be related to the of the RF bandpass filter (BPF).
1712
The of an LC bandpass filter is limited by and re-
lated to the system center frequency and RF bandwidth
through
Meanwhile, the OSR is related to the oversampling clock fre-
quency and RF bandwidth through
OSR
Expressing in terms of in (4), and using (2) to substitute
into (3), we find a relation between OSR and .
OSR
Equation (5) says that the oversampling ratio of the mod-
ulator is constrained to be less than the of the RF BPF. Intu-
itively, a high OSR corresponds to a narrower bandwidth for
a given clock frequency and LO frequency. A narrower band-
width requires a higher filter. In current technologies,
ranges from 10–25, depending on the top-level metal’s resis-
tance and distance to the substrate.
A second-order, 1-bit modulator is an ideal modulator choice
due to its inherent linearity and stability. However, for low
OSR in the range of 10–16, a second-order, 1-bit modulator is
limited to an SNR of around 40 dB [7]. A higher order 1-bit
modulator can provide higher SNR, but increases the slope
at which out-of-band quantization noise rises, making the
design of an on-chip RF BPF much more difficult. A low-order
multi-bit modulator, on the other hand, provides good SNR
performance for moderate OSR, and also reduces the amount
of out-of-band quantization noise. The multi-bit modulator
requires good matching between unit cells, but is essential for
lowering the required attenuation and order of the RF BPF.
B. Targeted System Parameters
A prototype digital-RF modulator targets Gb/s data rates
using OFDM modulation with 1-MHz sub-carrier spacing and
200-MHz RF bandwidth centered at 5.25 GHz. If 256-QAM
modulation is used on each sub-carrier, a maximum data rate
of 1.6 Gb/s can be transmitted. Assuming a required SNR of
30 dB for 256-QAM and a PAPR of 15 dB for the 200 sub-carrier
OFDM signal, the modulator should provide an SNR 45 dB.
With an LO frequency at 5.25 GHz, is chosen to be 2 in (2)
so that 2.625 GS/s and OSR 13.
Table I lists several topologies and their simulated SNR
with OSR 13. The 1-bit topologies all use optimized zero
locations [8]. Matching requirements to maintain the SNR of
the modulator are based on Monte Carlo simulations in
MATLAB using random mismatches with variance between
unit elements. The results show that the second-order 3-bit mod-
ulator maximizes the in-band SNR and also relaxes the RF fil-
tering requirements.
Fig. 4 plots the output spectrum of a second-order, 3-bit
RF modulator before and after filtering with a fourth-order
Bessel RF BPF with bandwidth of 260 MHz. Out-of-band
quantization noise is low enough to pass the spurious emis-
sion requirements outside the 5.15–5.35 GHz UN-II band.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 8, AUGUST 2007
TABLE I
SIMULATED 16 SNR WITH OSR = 13
(3)
(4)
(5)
Fig. 4. RF output spectrum using second-order, 3-bit 16 modulator.
According to the FCC, spurious emissions must be below
27 dBm/MHz outside the 5.15–5.35 GHz UN-II band [9].
The limits drawn assume a maximum power of 20 dBm and
a PAPR of 16 dB for the final transmit signal out the antenna.
In Fig. 4, the output signal is a pure sine wave with PAPR of
3 dB and its power is normalized to 0 dB. It then follows that
the spurious emissions limits are 60 dBc/MHz.
III. QUADRATURE DIGITAL-IF
The in-band RF output spectrum of the digital-RF mod-
ulator can still be degraded by LO and image spurs due to LO
leakage and quadrature LO phase mismatches. The direct mod-
ulator architecture can be reconfigured into a digital-IF trans-
mitter by adding a digital-IF quadrature up-converter after the
digital modulators. LO and image spurs from the digital-RF
converter will be separated from the RF output by and
, respectively. If the IF frequency is high enough, both sig-
nals will be filtered by the RF BPF. When implemented digi-
tally, the IF quadrature modulator will not introduce any spurs
of its own.
One can implement a multiplier-free quadrature modulation
and eliminate the power consumption of the high-speed digital
mixer by choosing the IF frequency to be , [10], since
quadrature digital sines and cosines at only have values
of 1, 1, or 0. Unfortunately, conventional digital-IF up-con-
version at of a modulated digital baseband signal
causes severe aliasing of quantization noise into the IF signal
passband. This occurs because the baseband spectrum has
noise peaks at while the positive and negative IF fre-
quencies are separated by . A plot of a digital-IF spec-
trum at is shown in Fig. 5.
JERNG AND SODINI: A WIDEBAND DIGITAL-RF MODULATOR FOR HIGH DATA RATE TRANSMITTERS
Fig. 5. Digital-IF output spectrum with f = f =4.
Fig. 6. Quadrature digital-IF 16 RF modulator.
A quadrature digital-IF topology, shown in Fig. 6, greatly
reduces the noise aliasing by cancelling either the positive or
negative IF sideband through the use of two sets of quadra-
ture modulators providing quadrature IF outputs. The cancella-
tion is accomplished in the subsequent RF up-conversion of the
quadrature DRFC and is affected by non-ideal phase matching
of the quadrature LO signals driving the DRFC. MATLAB sim-
ulations of the system in Fig. 6 benchmark the degradation in
SNR due to quadrature LO phase inaccuracies when using a
second-order, 3-bit modulator. The results are plotted in
Fig. 7. The SNR remains above 50 dB for LO phase errors
less than 1.3 . Increasing the number of bits in the quantizer
of the modulator reduces the level of out-of-band quanti-
zation noise and can lower the sensitivity of the SNR to noise
aliasing.
Bandpass modulation at can also be used to pro-
vide a digital-IF output. The quadrature digital-IF topology was
chosen because it easily enables multiplexing between a direct
modulation architecture and a digital-IF architecture, and also
reduces the order of the modulator compared to a bandpass
architecture.
The following equations relate the IF, clock, and LO fre-
quencies given a desired RF output frequency for a digital-IF
architecture.
(6)
(7)
1713
Fig. 7. SNR versus LO phase error for quadrature digital-IF.
For 5.25 GHz and 2.625 GHz, is offset to
4.6 GHz (for upper-sideband mixing).
A drawback of this frequency plan that was experimentally
observed is the presence of spurious energy at 5.25 GHz. The
high-speed digital circuits clocking at 2.625 GHz create a
second harmonic at 5.25 GHz. In order to prevent this spur,
the clock frequency for the modulator can be offset from
. For example, the choice of 2.4 GHz sets
600 MHz and 4.65 GHz.
When is no longer an integer multiple of , violating
(1), aliasing of quantization noise is a concern. The amount of
aliasing depends on the magnitude of the quantization noise
appearing at 5.25 GHz, and the filtering provided by the
frequency response of a zero-order hold. The rectangular pulse
impulse response of a zero-order hold assumes infinitely fast
clock edges. When considering the actual rise and fall times of
the clock signal, the impulse response looks like a trapezoidal
pulse. The frequency response of a trapezoidal pulse with
sampling period and rise/fall time is
(8)
equals the multiplication of two sinc functions.
The first sinc function has nulls at multiples of similar to
the ideal zero-order hold. The second sinc function has nulls
at multiples of and adds additional attenuation at higher
frequencies. Fig. 8 compares the frequency responses of the
rectangular pulse with infinite rise/fall times and the trapezoidal
pulse with rise/fall time of 75 ps.
We are interested in the attenuation provided at around
11 GHz since and are separated by 10.5 GHz.
According to Fig. 8, the trapezoidal impulse response pro-
vides 15 dB additional attenuation in the frequency range of
interest. MATLAB simulations of Fig. 6 with 4.65 GHz
and 2.4 GHz indicate an SNR of 38 dB with an ideal
rectangular pulse and an SNR of 53 dB with the trapezoidal
pulse. Thus, in practice, can be offset slightly from
in the quadrature digital-IF modulator without substan-
tial degradation in SNR. The quadrature digital-IF topology
approaches the performance of an ideal transmitter where the
1714
Fig. 8. Frequency response of zero-order hold.
RF output spectrum contains only the desired signal, with no
LO feedthrough or image spurs.
IV. RF BANDPASS RECONSTRUCTION FILTER
The multi-bit modulator design allows a fourth-order
Bessel bandpass filter with 260-MHz bandwidth at 5.25 GHz
to meet out-of-band noise requirements. However, variations
in capacitance or inductance cause a shift in the filter center
frequency and a large amplitude loss in the fixed RF bandwidth
of the system. A practical realization must include an automatic
control loop to stabilize the filter center frequency over process
and temperature variations.
A. 5.25-GHz Filter Design
A narrowband approximation to a bandpass ladder filter
can be realized with shunt LC resonator sections that are
capacitively coupled [11]. This topology minimizes the number
of inductors required in the filter. Further area reduction is
achieved by converting the topology into its differential form.
The coupled resonator design methodology follows in a manner
analogous to conventional ladder design using filter look-up
tables [11]. Based on the normalized resonator quality factor
defined as
(9)
the normalized coefficients of coupling , and normalized
source and load values are tabulated for coupled ladder
lowpass prototypes. In (9), is the filter bandwidth, is
the filter center frequency, and is the unloaded resonator .
For a particular filter order, there is a minimum required to
realize the filter’s transfer function. The minimum unloaded res-
onator required for a fourth-order Bessel BPF at 5.25 GHz
with bandwidth 260 MHz is [11]
(10)
A schematic of the filter is shown in Fig. 9. A three-turn dif-
ferential inductor was designed and optimized for using the
EM simulator Sonnet. The process featured a 4- m-thick top
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 8, AUGUST 2007
Fig. 9. LC BPF schematic.
metal 7 layer and an M7–substrate spacing greater than 12 m.
A ground shield consisting of strips of M1 was placed under-
neath the inductor and connected to an AC ground to reduce
substrate losses. Simulated differential inductance and were
2.2 nH and 26 at 5.25 GHz.
The resonator load capacitance is implemented using
PN-junction varactors to allow tunability of the filter. MIM
capacitors in series with the varactors linearize the varactor
C–V characteristics. The PN varactor is configured with its
cathode at a virtual ground point of the differential resonator
so that its parasitic substrate diode does not degrade resonator
. The filter is designed to tune from 4.8 GHz to 5.6 GHz, cor-
responding to a tuning range of 8%. Parallel plate capacitors
using the top two metal layers are utilized to implement the
small 26.3-fF coupling capacitors. Minimizing resistance in the
layout connections to the varactors and inductors is critical for
maintaining a high quality factor in the resonator.
B. Automatic Tuning Loop
Automatic frequency tuning can be implemented by config-
uring a replica resonator or the filter itself as a voltage-controlled
oscillator (VCO) and locking it to a separate reference frequency
in a phase-locked loop (PLL) [12]. These PLL tuning systems
are costly in terms of die area and circuit complexity.
This design adapts a tuning technique used in baseband filters
[13] for use at RF frequencies. The tuning scheme takes advan-
tage of the fact that the phase difference between filter input
and filter output is 90 at the center frequency. Fig. 10 shows
a simplified block diagram of the self-tuning loop using single-
ended signals. All circuits are implemented differentially and
all signals are taken differentially except for the operational
amplifier (opamp) output. The filter input and output are coupled
through small capacitors to a high-frequency phase detector.
The differential outputs of the phase detector are applied to a dif-
ferential-input single-ended-output opamp that drives the con-
trol voltage of the varactors in the resonators. The feedback loop
forces zero differential voltage between the phase detector out-
puts, which corresponds to the condition of 90 phase difference
between the phase detector inputs. Since the filter will always be
centered at the system LO frequency, the 5.25-GHz LO signal
driving the digital-RF converter can be used to calibrate the
filter. The filter does not need to be reconfigured as an oscillator.
Self-tuning avoids matching issues and adds minimal additional
JERNG AND SODINI: A WIDEBAND DIGITAL-RF MODULATOR FOR HIGH DATA RATE TRANSMITTERS
Fig. 10. Tuning loop block diagram.
circuitry. Most importantly, the filter can be calibrated in its
actual circuit implementation within the integrated digital-RF
converter, including all parasitic effects of the circuit and layout.
The opamp is a basic two-stage Miller-compensated differ-
ential-to-single-ended amplifier. It has a DC gain of 77 dB,
unity-gain bandwidth of 2 MHz, and phase margin of 88 .
For small excursions from the 90 condition, the effective feed-
back factor in the loop is close to 1, and the settling time is
approximately 0.5 s. The phase detector circuit is based on
the use of a Gilbert-cell multiplier [14]. At high frequencies,
the conventional Gilbert-cell multiplier suffers from phase mis-
matches between its two unsymmetrical input ports. The mis-
match arises from a difference in effective input capacitance
between the bottom port and top port. A finite driving resis-
tance causes a phase delay related to the RC product. If the two
ports have a phase mismatch term , the multiplier will output
a non-zero DC voltage when its inputs are in quadrature. By
using two Gilbert-cell multipliers with cross-coupled inputs as
in Fig. 10, the DC term due to the phase mismatch can be can-
celled by summing the outputs together.
Variations in tuning sensitivity and phase detector gain only
affect the DC gain of the feedback loop. DC offsets at the output
of the phase detector and the input of the opamp cause a finite
phase error (from 90 ) based on the phase detector gain when
the phase detector differential output is near zero. In this design,
a DC offset of 20 mV can be tolerated at the input of the opamp
for a 5-MHz error in the calibrated center frequency.
The coupled resonators ideally have identical resonance fre-
quencies. Small mismatches in loading capacitances between
the input and output nodes of the filter can cause a difference
in resonance frequencies and degrade the filter transfer func-
tion. When a mismatch is present, the filter center frequency
will no longer correspond to the condition of 90 phase differ-
ence between input and output. Routing lines to the filter input
and output must be carefully extracted and equalized during the
layout phase. The loading on filter input and output must also
be equalized. Dummy transistor loads are placed on the output
nodes to match the cascode transistors from the DRFC that load
the filter input nodes.
C. Distortion Versus Tunability
An important consideration in a tunable LC filter is distor-
tion. As shown in Fig. 11, the voltage across the varactor varies
as a function of the input signal driving the filter. This creates a
signal-dependent capacitance that causes distortion. The magni-
tude of the distortion products can be calculated by first writing
1715
Fig. 11. Differential resonator with nonlinear C(V).
an equation for the tank capacitance as a function of the input
signal using a power series expansion.
(11)
The analysis is greatly simplified by assuming that only
contains frequencies of the input current signal. This assumption
is valid because the distortion products are much smaller than
the fundamental frequency and will not influence C(V). One can
then derive an expression for the resonator current as a func-
tion of the resonator voltage to determine the level of distortion
products:
(12)
The relevant distortion products are those that fall into the
passband of the filter. Two-tone inputs at frequencies and
create IM3 products due to nonlinearity at frequencies
and . In the differential implementation shown in
Fig. 11, the tank capacitance C(V) is an even function of the
differential tank voltage. In other words,
due to the symmetry of the circuit. Note that the differential
capacitance C(V) in Fig. 11 is the series combination of C1,
C2, CV1, and CV2. Since C(V) is an even function, only the
even powers of in (11) are required. Equation (11) and
can be substituted into (12), and the
following equation for can be written:
(13)
In (13), it is assumed that , and only the first
three coefficients of C(V) are used. Near resonance,
and will approximately cancel. The relevant terms from
the multiplication in (13) for IM3 calculations are then
(14)
1716 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 8, AUGUST 2007

Given the voltage magnitude of the two tones, the power

ratio between the IM3 tones and the fundamental tones is cal-
culated to be

IM3(dBc) (15)

The IM3 depends on the second-order coefficient, , of the

power series expansion of C(V), and the effective resistance
of the tank at resonance. A higher tank will have higher
and result in worse IM3 performance. This indicates a tradeoff
between filter selectivity and filter distortion in tunable filters.
A higher also causes worse distortion. In general, reducing
the tuning range of the filter will lower .
Using (15) and assuming a maximum expected differential
peak voltage of 0.6 V in the filter, the IM3 products are calcu- Fig. 12. Measured filter response for different vtune.
lated to be 46.5 dBc with 0.3-V differential output for each
of the two fundamental tones. Circuit simulations in SpectreRF
showed the IM3 products to be 51 dBc under the same condi-
tions. The tradeoff between tuning range and distortion can be
alleviated by providing an additional coarse tuning capability
using switchable fixed capacitances [15]. This allows a reduc-
tion in tuning sensitivity of the varactor which minimizes . A
further refinement is to replace the analog varactor with a bank
of digitally switchable capacitances, replace the opamp with a
comparator, and modify the analog tuning loop to an all-digital
tuning loop.

D. Test Filter Measured Results

The performance of the filter and automatic tuning loop
was verified using an on-wafer probe test structure. Broadband
on-chip buffers resistively matched to 50 were used at the
input and output ports to interface to the filter. The test filter
was driven in current mode, in the same way it would be used
in the actual RF modulator. Measured filter responses with
manual tuning are plotted in Fig. 12. The filter tunes from
4.8 to 5.4 GHz. The ideal response, assuming a resonator Q
of 26, is plotted alongside the measured response centered at
5.2 GHz. Resistive losses in the varactor and the metal routing
lower the resonator to 20. As a result, the measured 3-dB
filter bandwidth is 280 MHz, slightly wider than the targeted
260-MHz bandwidth.
In Fig. 13, tuning curves are plotted for both manual and au-
tomatic tuning. In the case of automatic tuning, the input fre-
quency to the filter is varied and the resulting tune voltage is read
out. The results indicate excellent agreement between manual
and automatic tuning curves, confirming proper operation of the
auto tuning loop. The tuning algorithm, as proposed, digitally
stores the calibrated tuning voltage using an ADC and register,
and reapplies the voltage during normal circuit operation using
a DAC. The ADC and DAC do not require high speed or high
resolution, and were not implemented on our test chip.
V. HIGH-SPEED DIGITAL DESIGN
A high clock frequency is used in the digital modulators
to achieve high dynamic range and relax RF filtering require-
ments. The drawback is high dynamic power consumption in
the digital processing. Optimizing the high-speed digital power
Fig. 13. Measured manual tuning and auto tuning curves.
consumption is important to justify replacing the analog circuits
used in conventional I–Q modulators.
A. Modulator Topology
A MASH topology [16], consisting of two cascaded
first-order error feedback stages, implements second-order
noise shaping and was chosen for its simplicity. A block dia-
gram of the implementation is shown in Fig. 14. By placing all
zeros of the noise transfer function at DC, multipliers requiring
precise coefficients are avoided, saving power. The critical path
consists of a single 12-bit adder.
B. Low-Power Passgate Adder
A conventional static mirror adder requires extensive
pipelining to operate at 2.5 GS/s in 0.13- m CMOS. A faster
carry chain can be designed using a passgate style adder whose
carry chain consists of one nMOS passgate per bit. The reduced
logic swing in the carry chain can be amplified back to full
CMOS levels using a differential sense-amplifier flip-flop
scheme [17].
A simplified schematic of the nMOS passgate adder is shown
in Fig. 15. The carry chain is implemented differentially. For
, CMOS transmission gates implement the XOR function. For
, nMOS passgates are used since full logic levels are not re-
quired. In our implementation, the gate count is reduced by not
using logic to produce generate and kill signals from the adder
inputs and . Instead, transmission-gate-based adder logic
JERNG AND SODINI: A WIDEBAND DIGITAL-RF MODULATOR FOR HIGH DATA RATE TRANSMITTERS
Fig. 14. Second-order MASH error feedback topology.
Fig. 15. NMOS passgate adder simplified schematic.
is adopted where the output carry is either equal to the input
carry or , depending on the value of [18]. A pair of nMOS
passgates with drains connected together provide two parallel
paths to implement the logic, minimizing the capacitance on
the critical carry chain nodes. The sense-amplifier flip-flop is
a pMOS version of the modified SAFF design in [19]. It is de-
signed for a delay of less than 170 ps for input
differential voltages as small as 200 mV.
The transistor-level schematic for a passgate adder cell is
shown in Fig. 16. A reset technique is used to pull all carry chain
nodes to ground through a small nMOS transistor during the first
half of the clock cycle [17]. This reduces the available time for
carry propagation to less than half the clock period (200 ps),
but it also insures that all passgates start in their linear region.
Given the typical delay of the sense-amplifier flip-flop driving
an adder input, the propagate signal gating the carry chain will
not be valid until approximately the end of the first half of the
clock cycle anyway. When the carry chain nodes reset to ground,
there is a possibility that the input may be shorted to ground
through the passgate controlled by , which is not valid yet.
In order to prevent current from flowing, a gated-clock version
of is used to open the passgate whenever the clock signal
is high. The additional logic does not affect the resistance or
capacitance of the carry chain RC network. The adder consists
1717
Fig. 16. Passgate adder cell.
TABLE II
ADDER COMPARISON
mainly of static CMOS inverters and passgates. A 6-bit carry
chain has a simulated worst case propagation delay of 72 ps.
A 12-bit adder was built using a two-stage pipeline of 6-bit
nMOS passgate adders. This is an efficient choice since in the
modulator architecture, a delay element is required after
the adder. Most of the pipelining flip-flops are absorbed into the
modulator implementation at no cost. Simulation results com-
paring the passgate adder to a 12-bit static mirror adder at 75 C
and 1.3-V supply using nominal process models are summa-
rized in Table II. The mirror adder required a pipeline of six
2-bit ripple carry adders. A static transmission-gate edge-trig-
gered flip-flop is used to implement all pipeline delays. Power
consumption numbers do not include the power needed to drive
the adder inputs, but do include the power consumed by the
clock driver. Layout parasitics are extracted and included in the
simulations. Compared to the static mirror adder, the passgate
adder dissipates less than half the power for the same simulation
conditions.
C. Top-Level Implementation
A top-level digital block diagram is shown in Fig. 17. The dig-
ital block takes I–Q digital data as input bits and outputs 3-bit, I
and Q, IF bitstreams. The I–Q processing consists of a 4
interpolator, a second-order, 3-bit, digital modulator, and a
digital up-converter with IF frequency of . The digital-IF
function can also be bypassed, allowing the I and Q baseband
bits to directly drive the subsequent digital-RF converter.
Thus, both homodyne and digital-IF transmitters are supported.
The quadrature digital-IF up-converter output bits alternate
between I and Q at the sample rate . The bits are inverted
every two clock samples. The quadrature bitstreams are offset
by one clock sample, corresponding to a 90 phase shift at the
1718
Fig. 17. Digital block diagram.
Fig. 18. Digital-IF up-converter implementation.
IF frequency of . The gate-level digital implementation
is shown in Fig. 18. A transmission gate multiplexer controlled
by a half-rate clock is used to swap between I and Q. It is at the
full sample rate. Another multiplexer, with one inverter in series
with one of its transmission gates, is controlled by a quarter-
rate clock to invert the bits every two clock samples. The entire
block can be bypassed with another multiplexer, which either
directly routes I and Q to the output, or passes I and Q through
the digital-IF up-converter. The up-converter block consumes
much less power than the modulator.
VI. DRFC CIRCUIT DESIGN
A multi-bit DRFC is sensitive to mismatches between
unit elements. Traditional DACs are characterized by metrics
such as differential nonlinearity (DNL) and integral nonlinearity
(INL) at DC, and spurious-free dynamic range (SFDR) at high
frequencies. The output of a DRFC is a digitally modulated RF
signal. Element mismatches cause noise and distortion in the RF
output spectrum. In this case, the signal-to-noise plus distortion
ratio (SNDR) is a more meaningful metric. Knowledge of the
quantitative relation between element mismatch and SNDR is
useful to circuit designers.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 8, AUGUST 2007
Fig. 19. SNDR (mean) versus percent mismatch.
DAC mismatch effects have been analyzed extensively [2],
[20]–[22]. The design of a DRFC introduces a new mismatch
term due to the need to match the high-frequency LO signal
current in amplitude and phase across all unit cell differential
pairs. LO phase mismatches can be treated as an effective am-
plitude mismatch for small phase errors using the small angle
approximation.
(16)
A behavioral model of a multi-bit QDRFC was devel-
oped in MATLAB to quantify the relationship between mis-
match among DRFC unit cells and SNDR. It is assumed that
the multiple sources of amplitude and phase mismatch are sta-
tistically independent, and a single Gaussian random variable
is used to model the mismatch. The 3-bit DRFC is pseudo-seg-
mented using 7 unit cells. The MSB drives 4 unit cells in par-
allel, the ISB drives 2 unit cells in parallel, and the LSB drives
1 unit cell. In the model, a sample rate of 2.5 GS/s is used and
the data bits switch linearly with a rise/fall time of 50 ps.
Single-tone sine-wave inputs are used to characterize the
SNDR performance. Fig. 19 plots the mean of the simulated
SNDR versus percent mismatch for a bandwidth of 200 MHz.
Mismatch less than 1% is required to achieve an SNDR greater
than 50 dB.
Gain mismatch requirements can be translated into phase
matching requirements using (16). For a given LO frequency,
an allowable timing spread for the LO signal can be derived
from the required phase matching. Fig. 20 plots the equivalent
timing spread versus effective gain mismatch for different LO
frequencies. As the LO frequency becomes higher, the allow-
able timing spread of the LO signal becomes very small. For a
5-GHz LO frequency, the timing spread needs to be less than
250 fs to maintain SNDR greater than 50 dB. An advantage of
the approach is that the number of DRFC unit cells is small.
A 3-bit modulator requires only 7 unit cells, leading to
small layout area and minimal timing spread in the LO signal.
Fig. 21 shows a circuit schematic of the DRFC unit cell and
data driver. Each unit cell is biased at 250 A, resulting in a
total current of 3.5 mA for the quadrature DRFC. Standard
JERNG AND SODINI: A WIDEBAND DIGITAL-RF MODULATOR FOR HIGH DATA RATE TRANSMITTERS
Fig. 20. LO timing spread versus effective gain mismatch.
Fig. 21. DRFC unit cell and data driver.
techniques [20] are used to match the current sources to 0.5%
based on values for and provided by the foundry.
The gates of the cascode transistors are connected directly to
the supply voltage of 2.5 V. It is acceptable to use a minimum
length device for the cascode transistor since the maximum
source–drain voltage across the device is 0.8 V during circuit
operation. The biasing voltages are chosen to allow differential
voltage swings of 0.6 Vpk-pk in both the LO signal and data
signals.
The data drivers consist of a latch and buffer, implemented
using source-coupled logic. The load resistance and buffer cur-
rent are chosen to be 1.5 k and 400 A, respectively, providing
a 0.6 Vpk-pk differential swing with approximately 75-ps tran-
sition time. The three buffers drive different load capacitances
and need to be scaled to provide identical timing of their data
signals. The parasitic capacitances of the routing lines to the
DRFC were actually larger than the input capacitance of the
DRFC current-steering switches. Thus, the ISB and LSB buffers
were identical in size, and biased at 400 A each, while the MSB
buffer was biased at 500 A, accounting for its slightly larger
capacitive load.
1719
Fig. 22. Test chip block diagram.
VII. EXPERIMENTAL RESULTS
A prototype IC implemented in 0.13- m CMOS integrates
two high-speed digital modulators, a quadrature digital-RF
converter, an RF bandpass filter with auto-tuning circuitry, and
a quadrature LO path with polyphase filter and LO limiting
buffers. A block diagram is shown in Fig. 22. The quadrature
LO signals are generated with a two-stage RC-polyphase filter.
All I/Os are shown single-ended, but are implemented differ-
entially. Digital data is generated in MATLAB and loaded into
the RAM of a Xilinx Virtex-4 field-programmable gate array
(FPGA). The FPGA provides 11-bit LVDS digital signals at
650 MS/s to the IC, where they are up-sampled by 4, filtered,
and processed by the modulators. A digital control input
is used to select between direct up-conversion and digital-IF
up-conversion. The IC was packaged in an 88-QFN package
with exposed ground paddle.
All measurements are performed after filter calibration.
Fig. 23 plots the output spectrum with a 12-MHz sine-wave
input using direct up-conversion. Measured LO feedthrough is
51 dBc, and measured image rejection is 46 dB. Spurs due
to harmonic distortion are less than 55 dBc. Fig. 24 shows
the output spectrum when using the digital-IF up-converter.
The LO frequency is shifted to 5.85 GHz, while the clock
frequency is 2.4 GHz. The LO and IF image signals are now
out-of-band. In-band image noise is below the noise floor of
the output spectrum. The largest spur is a third harmonic tone
at 52 dBc that is due to random element mismatch in the
multi-bit converter. Measured SNDR is 49 dB. Output power is
8 dBm, after accounting for board and cable losses.
Fig. 25 shows a wideband plot with 2-GHz span, using direct
up-conversion. The bandpass filter is effective in attenuating
out-of-band quantization noise from the second-order, 3-bit
modulator. Fig. 26 shows the output spectrum of a 160-MHz
256-QAM OFDM signal. The FCC spectral limits outside the
5.15–5.35 GHz UN-II band are also shown, indicating that the
spurious requirements are met. Fig. 27 and Fig. 28 show the
output spectrum for a 20-MHz 64-QAM OFDM channel for
the 802.11a standard, and a pair of 20-MHz 256-QAM OFDM
channels.
1720 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 8, AUGUST 2007

Fig. 23. Measured output spectrum: direct up-conversion, 12-MHz sine-wave Fig. 25. Measured output spectrum: wideband plot.
input.

Fig. 26. Measured output spectrum: 160-MHz 256-QAM OFDM signal.

Fig. 24. Measured output spectrum: digital-IF, 12-MHz sine-wave input.

The error vector magnitude (EVM) of a 100-MHz 256-QAM

OFDM signal was measured using a discrete receiver test plat-
form from the MIT WiGLAN project. The receiver was used
to down-convert and digitize the RF output signal from the
digital-RF modulator. The digitized signal was then captured
using an FPGA and processed with MATLAB scripts. Mea-
sured SNR is plotted on a per sub-carrier basis in Fig. 29. The
WiGLAN testing platform SNR was limited to 30 dB by the
resolution of the on-board ADC. The SNR of the digital-RF
modulator alone is estimated to be 30 dB. According to Fig. 29,
almost every sub-carrier can support 64-QAM modulation while
several can support 256-QAM. Assuming 64-QAM modulation
across all 200 MHz, the presented modulator can transmit a data Fig. 27. Measured output spectrum: 20-MHz OFDM channel for 802.11a.
rate of at least 1.2 Gb/s over its intended bandwidth.
The power consumption and die area of the entire modulator
is summarized in Table III. All blocks use a supply voltage in Fig. 30. The modulator consumes 187 mW and occupies
of 1.5 V except for the DRFC core. A die photo is shown a die area of 0.72 mm . A general figure of merit (FOM)
JERNG AND SODINI: A WIDEBAND DIGITAL-RF MODULATOR FOR HIGH DATA RATE TRANSMITTERS 1721

Fig. 28. Measured output spectrum: pair of 20-MHz OFDM channels.

Fig. 30. Die photo.

VIII. CONCLUSION
The digital-RF modulator is a power and area efficient
modulator for wideband systems. Measured results demonstrate
a 1.2-Gb/s data rate over 200-MHz RF bandwidth centered at
5.25 GHz. Spurs associated with direct digital-RF conversion
have been eliminated through the integration of a high- ,
self-tuned RF bandpass filter. The digital-RF modulator is
amenable to digital CMOS scaling and software radio.
Fig. 29. SNR measurement using WiGLAN receiver.

ACKNOWLEDGMENT
TABLE III
DIGITAL-RF MODULATOR POWER CONSUMPTION/DIE AREA The authors are grateful to Prof. A. Chandrakasan and Prof.
M. Perrott for their valuable suggestions and contributions to
this research, and to K. Tan for his help in measuring SNR.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 8, AUGUST 2007
Albert Jerng (M’97) received the B.S.E.E. and
M.S.E.E. degrees from Stanford University, Stan-
ford, CA, in 1994 and 1996, respectively.
He was with Advanced Micro Devices from 1996
to 1999, designing analog and RF integrated circuits.
From 1999 to 2002, he worked at DSP Group, where
he developed CMOS RF transceivers for 900-MHz
and 2.4-GHz cordless phone systems. He received the
Ph.D. degree from MIT in 2006, where his research
interests included low phase noise CMOS VCO de-
sign, and high data rate transmitters. He is currently
a Principal Scientist at Broadcom in San Diego, CA.
Charles G. Sodini (S’80–M’82–SM’90–F’94) re-
ceived the B.S.E.E. degree from Purdue University,
West Lafayette, IN, in 1974, and the M.S.E.E. and
the Ph.D. degrees from the University of California
at Berkeley in 1981 and 1982, respectively.
He was a Member of the Technical Staff at
Hewlett-Packard Laboratories from 1974 to 1982,
where he worked on the design of MOS memory
and later, on the development of MOS devices with
very thin gate dielectrics. He joined the faculty of the
Massachusetts Institute of Technology, Cambridge,
MA, in 1983, where he is currently a Professor in the Department of Electrical
Engineering and Computer Science. He was the Associate Director of MIT’s
Microsystems Technology Laboratories from 1989 to 1996. His research
interests are focused on integrated circuit and system design with emphasis on
analog, RF and memory circuits and systems. Along with Prof. Roger T. Howe,
he is a coauthor of an undergraduate text on integrated circuits and devices
entitled Microelectronics: An Integrated Approach (Prentice Hall, 1997). He
also studied the Hong Kong electronics industry and co-authored a chapter
with Prof. Rafael Reif in a recent book entitled Made in Hong Kong (Oxford
University Press, 1997).
Dr. Sodini held the Analog Devices Career Development Professorship of
Massachusetts Institute of Technology’s Department of Electrical Engineering
and Computer Science, and was awarded the IBM Faculty Development Award
from 1985 to 1987. He has served on a variety of IEEE conference committees,
including the International Electron Device Meeting, where he was the 1989
General Chairman. He was the 1992 Technical Program Co-Chairman and the
1993–1994 Co-Chairman of the Symposium on VLSI Circuits. He served on
the Electron Device Society Administrative Committee from 1988 to 1994. He
is the past president of the IEEE Solid-State Circuits Society and a member of
its Administrative Committee.