PRODUCT BRIEF CHL8318

DIGITAL MULTI-PHASE BUCK CONTROLLER

FEATURES DESCRIPTION
 Intel VR11.x compliant Digital PWM Controller The CHL8318 is a 8-phase digital synchronous buck
®
 Programmable 1-phase to 8-phase operation controller for core regulation of high-performance INTEL
VR11.1 and VR11.0 platforms. The CHL8318 is fully
 Configurable switching frequency from 200 kHz to compliant with VR11.1 including Power Status Indicator
1MHz per phase with accuracy better than 2% (PSI) and for improved light load efficiency and accurate
 Customized Digital Over-Clocking Features current output (IMON).
o Easy-to-use SMBus Gamer command
The CHiL CHL8318 includes a customized set of digital
o Gamer VID control up to 2.3V, Gamer Vmax, over-clocking features which require no external
VID Override or Track, Digital Load-Line Adjust, components. Gaming applications can use the SMBus
Gamer OC/OVP, Gamer OFF pin, Gamer OTP interface to place the VRD into “Gamer Mode”. Gamer Mode
 CHiL Efficiency Shaping Features features include Extended Gamer VID up to 2.3V with 6.25
o Variable Gate Drive mV resolution, Gamer Vmax, CPU VID Override or Track,
Digital Load-Line adjust, Gamer OC/OVP and Gamer OFF
o Dynamic Phase Control pin.
 1-phase to 4-phase PSI for Light Loads
 Adaptive Transient Algorithm minimizes output bulk The CHL8318 deploys a number of efficiency shaping
capacitors features. The CHL8318 can be configured to optimize
MOSFET gate drive versus load current, PSI can be
 Designed for use with coupled inductors programmed to be up to four phases for optimum light-load
 Enables Thermal Phase Balancing efficiency, and the controller can autonomously add/drop
 SMBus Fault Indicators: OVP, UVP, OCP, OTP phases in low-current and mid-current regions to deliver
90+% efficiency across the entire load range.
 SMBus interface for configuring and monitoring; SMBus
commands include monitoring input current and power CHiL’s unique Adaptive Transient Algorithm, based on non-
 Compatible with CHiL ATL Drivers and tri-state Drivers linear digital PWM algorithms, minimizes output bulk
 Nine bytes of NVM storage available for customer use capacitors. Coupled inductor mode of operation allows two
phase PSI and add/drop of phases which are 180°out of
 +3.3V supply voltage; 0ºC to 85ºC Ambient operation phase for further improvement in transient response and
 RoHS Compliant, MSL level 1 package form factor.

CHL8318 supports three NTC temperature sensors to report

temperature and trigger VR HOT and OTP faults. Digital
ISEN3
IRTN1
ISEN1
IRTN2
ISEN2
IRTN3

ISEN4

ISEN5
IRTN6
ISEN6
IRTN7
ISEN7
IRTN4

IRTN5

thermal balancing allows proportional current imbalance

between phases.
56 55 54 53 52 51 50 49 48 47 46 45 44 43
RCSP 1 42 IRTN8 The CHL8318 provides extensive OVP, UVP, OCP and OTP
RCSM 2 41 ISEN8
fault protection. Device and fault configuration parameters
VCC 3 40 VCC
are easily defined using the CHiL Intuitive Power Designer
VCPU 4 39 PWM8
VRTN 5 CHiL (IPD) GUI and stored in on-chip non-volatile memory (NVM).
38 PWM7
SADDR/ CHL8318
6 37 PWM6
56 Pin
GAMER_OFF
7 8mmx8mm 36
The 3-pin SMBus interface can be used to monitor a variety
IMON PWM5
RRES 8 QFN 35 PWM4
of operating parameters on up to seven CHL8318 based
VINSEN 9
TOP VIEW
34 PWM3
VRs. The controller includes a unique sensorless and
TSEN1 10 33 PWM2 lossless input current monitoring capability.
GND
TSEN2 11 32 PWM1
TSEN3 12 31 NC The CHL8318 truly simplifies VRD design and enables
EN 13 30 VCC fastest time-to-market with its “set-and-forget” methodology.
V18A 14 29 VAR_GATE
15 16 17 18 19 20 21 22 23 24 25 26 27 28
APPLICATIONS
SALERT#
SDA
SCL
PSI#
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_READY
VR_HOT

 Intel® VR11.x CPU VRD and VRM; DDR Memory

 High Performance Desktops and Servers
 Over-clocking and High-Efficiency Applications

Figure 1. CHL8318 56 Pin QFN Package

Trademarks and registered trademarks are the property of the respective One Highwood Drive, Tewksbury, MA 01876
owners. Page 1 of 4 Tel: +1(978)-640-0011
PB0006 Rev. 1.00, October 26, 2009 www.chilsemi.com
© 2009 CHiL Semiconductor Corp. All rights reserved
 PRODUCT BRIEF CHL8318
DIGITAL MULTI-PHASE BUCK CONTROLLER

FUNCTIONAL BLOCK DIAGRAM

RRES V18A 3.3V

VID0
VID1 1.8V LDO

VID2 Reference
VID3 VID decode
VID4 and DAC

VID5 Digital Processor

Vref
VID6
VID7
PID +
OVP Controller

PWM1
VCPU Voltage
VRTN Σ Error PWM2
ADC
PWM3

ISEN1 Transient PWM PWM4

IRTN1 Controller Generator
PWM5
ISEN2
IRTN2 PWM6
ISEN3 PWM7
IRTN3
ISEN4 PWM8
IRTN4 Channel Current Sense
ISEN5
IRTN5 Current
ISEN6 Balance
IRTN6
ISEN7
IRTN7
ISEN8
IRTN8

RCSP
RCSM

Monitor
TSEN1 ADC
TSEN2 VAR_GATE
OVP
TSEN3
VINSEN Oscillator, NVM
EN State Control, and Current
SADDR/ Monitoring Monitor IMON
GAMER_OFF

PSI
SDA SMBus
SCL Interface

SALERT VRHOT VR_Ready GND

Figure 2. Functional Block Diagram

Page 2 of 4 PB0006
Rev. 1.00, October 26, 2009
 PRODUCT BRIEF CHL8318
DIGITAL MULTI-PHASE BUCK CONTROLLER

TYPICAL APPLICATIONS
12V

V
1 BOOT
Vcc HI_GATE V_CPU
Rseries RCSP V_VGD HVCC SWITCH

V
CCS LVCC L
RTh RCS PWM LO_GATE O
32 MODE GND A
Rseries PWM1
2 55 CHL8510 D
RCSM ISEN1
56
+3.3V IRTN1
3
12V

V
30
40 BOOT
VCC Vcc HI_GATE
V_VGD HVCC SWITCH

V
4 LVCC
VCPU PWM LO_GATE
5 VRTN
PWM 2 33 MODE GND
6 SADDR/ 53 CHL8510
ISEN2
GAMER_OFF 54
IRTN2
12V

V
To 7
IMON
CPU R_IMON C_IMON
BOOT
HI_GATE
Vcc
V_VGD
CHL8318 HVCC SWITCH

V
LVCC
VRTN PWM LO_GATE
34 MODE GND
PWM3
51 CHL8510
ISEN3
8 RRES 52
+12V IRTN3
12V

V
RVIN_1
9 VINSEN
BOOT
RVIN_2 10 Vcc HI_GATE
TSEN1 V_VGD HVCC SWITCH
V LVCC
RTh PWM LO_GATE
35 MODE GND
PWM4
11 49 CHL8510
TSEN2 ISEN4
RTh 50
IRTN4
12V
V

12
TSEN3
RTh BOOT
Vcc HI_GATE
V_VGD HVCC SWITCH
V

LVCC
PWM LO_GATE
36 MODE GND
From 13 PWM5
EN CHL8510
V

System 47
ISEN5
14 V18A 48
IRTN5
12V
V

BOOT
Vcc HI_GATE
+3.3V V_VGD HVCC SWITCH
V

LVCC
PWM LO_GATE
15 37 MODE GND
SMBus

SALERT# PWM6
V

16 45 CHL8510
SDA ISEN6
V

17 46
SCL
V

IRTN6
12V
V

18
PSI#
V

BOOT
19 Vcc HI_GATE
VID7
V

V_VGD HVCC SWITCH

V

LVCC
20 PWM LO_GATE
VID6
V

38 MODE GND
21 PWM7
VID5 43 CHL8510
V

ISEN7
From CPU

22 44
VID4 IRTN7
V

12V
V

23
VID3
V

BOOT
24 VID2 Vcc HI_GATE
V

V_VGD HVCC SWITCH

V

LVCC
25
VID1 PWM LO_GATE
V

39 MODE GND
26 PWM8
VID0 41 CHL8510
V

ISEN8
27 42
To VR_READY IRTN8
28 12V
CPU
V

VR_HOT
BOOT
Vcc HI_GATE
NC 31 HVCC SWITCH
LVCC
PWM LO_GATE V_VGD
MODE GND
VAR_GATE 29 CHL8510
Optional Variable
Gate Drive Circuit
GND

Figure 3. 8-phase VRD using CHL8318 Controller and CHL8510 MOSFET drivers

Page 3 of 4 PB0006
Rev. 1.00, October 26, 2009
 PRODUCT BRIEF CHL8318
DIGITAL MULTI-PHASE BUCK CONTROLLER

ORDERING INFORMATION
Package Tape & Reel Qty Part Number
CHL8318   
QFN 3000 CHL8318CRT

T: Tape & Reel

Package type
R : QFN

Operating Temperature Range

C: Commercial Standard

PACKAGE INFORMATION

Page 4 of 4 PB0006
Rev. 1.00, October 26, 2009