library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity Prexamenu2 is

port

A, B: in std_logic_Vector(3 downto 0);

Segs: out std_logic_vector(6 downto 0);

Kcu: out std_logic

);

end entity;

architecture rtl of Prexamenu2 is

signal S:std_logic_vector(3 downto 0);

signal sel: std_logic;

begin

S <= A WHEN A > B ELSE

B;
 SEGS <= "1111110" WHEN (S = x"0") ELSE

"0110000" WHEN (S = x"1") ELSE

"1101101" WHEN (S = x"2") ELSE

"1111001" WHEN (S = x"3") ELSE

"0110011" WHEN (S = x"4") ELSE

"1011011" WHEN (S = x"5") ELSE

"1011111" WHEN (S = x"6") ELSE

"1110000" WHEN (S = x"7") ELSE

"1111111" WHEN (S = x"8") ELSE

"1111011" WHEN (S = x"9") ELSE

"1110111" WHEN (S = x"A") ELSE

"0011111" WHEN (S = x"B") ELSE

"1001110" WHEN (S = x"C") ELSE

"0111101" WHEN (S = x"D") ELSE

"1001111" WHEN (S = x"E") ELSE

"1000111";

kcu <= '0';

end rtl;