April 2011

SYNOPSYS, UPF Fundamentals Workshop

INC LAB WORKBOOK

UPF_Fundamentals - Lab WorkbookLab Workbook

v2.docx | Synopsys 1
Table of Contents
Lab Data Setup .......................................................................................................................... 3

Lab1 Leon3s UPF Lab ................................................................................................... 4

General Lab Flow .................................................................................................................. 5
Leon3s Core Overview .......................................................................................................... 6
Leon3s Core Power Intent ..................................................................................................... 7
Task 1. Understanding the Power Intent Specification ......................................................... 8
Task 2. Creating the UPF for Leon3s ................................................................................... 9
Task 3. Verifying the correctness of the UPF using DC and MVRC ................................. 12

Lab2 Leon3mp UPF Lab .............................................................................................. 15

General Lab Flow ................................................................................................................ 16
Leon3mp Overview ............................................................................................................. 17
Leon3mp Power Intent ........................................................................................................ 17
Task 1. Understanding the Power Management Cells ........................................................ 19
Task 2. Understanding the Leon3mp UPF .......................................................................... 20
Task 3. Debugging the Leon3mp UPF in DC ..................................................................... 21
Task 4. Debugging the Leon3mp UPF in MVRC ............................................................... 23

UPF_Fundamentals - Lab Workbook v2.docx 2

Lab Data Setup
Lab Data Installation
In the directory where the labs will be installed, extract the tarball and edit the
lab_setup.csh such that the PROJECT_ROOT variable points to your installation directory:

% gtar -zxvf <tarfile_name>.tgz

% vi lab_setup.csh

Relevant Files and Directories

All files for this lab, including libraries, are pre-installed in the lab installation directory at
$PROJECT_ROOT, which contains the following subdirectories:

GOLDEN/ RTL/ - RTL files for original LEON3 design

LEON_SANDBOX/rtl/ - RTL files modified for this lab design
techlib/ - SAED 90nm technology libraries
lab1/ - starting directory for Lab 1
lab2/ - starting directory for Lab 2
Inside each lab directory are the following subdirectories:
DATA_SAED – design constraints for respective lab data
scripts_block – tcl scripts from the tools’ Recommended Methodology (RM)
rm_dc – working directory for DC, based on the RM
rm_mvrc – working directory for MVRC, based on the RM
mvrc是低功耗的相关工具

Setting up the Environment

To set up the environment for these labs, source the setup script, then “cd” into the
appropriate directory for each lab.

% source lab_setup.csh
% cd ./lab<X>

3
 1
Lab1 Leon3s UPF Lab

Learning Objectives

After completing this lab, you should be able to:

 Understand the different components of the power intent
of a design
 Create a UPF file based on the power intent description
 Use DC and MVRC to verify the correctness and
completeness of the UPF with respect to the design and
power state table

Lab Duration:
45 minutes

Lab 1 4
General Lab Flow

Study the Leon3s design and

the desired power intent
设计和所需的功率意图

Complete the necessary UPF

file for Leon3s

Verify the UPF for Leon3s

using DC and MVRC

Lab 1 5
Leon3s Core Overview

P0
Integer Pipeline and
Control

pd_switchable

RF0
3 port Register File

TBMEM0 CMEM0
Trace Buffer Cache Memory

For our lab, we consider two levels of power domain hierarchy: top level (leon3s
core), and pd_switchable. The logical hierarchy block pd_switchable can be
shutdown and has a lower operating voltage than the top level.

Lab 1 6
 Power
Leon3sIntent Diagram
Core Power Intent for Leon3s Core

TOP VDD VDD_LOW

(1.08V)

PD_SW VDD_LOW
(0.7V / OFF)
NSleep
pwrcon_pd_n

P0
VDD_LOW_SW

HL ELS

VSS pd_switchable
Actual intent is
ISO and LS, but
pwrcon_iso_n want ELS
cells inferred
VSS

© Synopsys 2011
• Top level
5
logic and P0 block are always on, operating at 1.08 V

• Logic block pd_switchable (containing tbmem0, cmem0, and rf0) has a

switchable supply, operating at 0.7V

• All domains share a common ground VSS, operating at 0.0v

• No state retention used

• Power sequencing is controlled via external interface:

– pwrcon_pd_n - domain is shutdown when signal is low
– pwrcon_iso_n - outputs isolated when signal is low
– When domain is isolated, outputs are clamped to 1

Operational States
• The valid operating states for the Leon3s design are:
– Run – everything powered up and running
– Idle – pd_switchable shut down

• Leon3s supply nets (with corresponding voltages and port state names):
– VDD is always on at 1.08V (HV)
– VDD_LOW is always on at 0.7V (LV)
– VDD_LOW_SW is the output of the power switch;
it is either operating at 0.7V (LV) or “off” (OFF)
– VSS is always on at 0.0V (GND)

Lab 1 7
 Task 1. Understanding the Power Intent Specification

Looking at the description of the power intent for Leon3s above, please answer the
following questions.

Question 1. What type of protection devices are needed on the outputs of

pd_switchable? Why?

____________________________________________________________

____________________________________________________________

Question 2. What type of protection devices are needed on the inputs of

pd_switchable? Why?

____________________________________________________________

____________________________________________________________

Question 3. From the description of the power states, please fill in the table
below to correctly describe the two legal power states for the
Leon3s design. List both the port state name and the operational
voltage for each supply, in each power state.

VDD VDD_LOW VDD_LOW_SW VSS

Run

Idle

Lab 1 8
 Task 2. Creating the UPF for Leon3s

In the lab directory, open the file leon3s.upf. You will use this file to review and
complete the UPF specification for Leon3s.

Please refer to the lecture materials to help complete this task.

1. Create the top level power domain (TOP), using the

create_power_domain commmand.

2. Domain TOP has three supply ports (VDD, VDD_LOW, and VSS) that drive
the supplies in Leon3s. These need to be declared in the UPF. Please
complete the create_supply_port commands for all three supply
ports.

3. Domain TOP has three supply nets (VDD, VDD_LOW, and VSS) that have to
be declared in the UPF. Please complete the create_supply_net
commands for all three supply nets.

4. The supply nets VDD, VDD_LOW, and VSS need to be connected to their
corresponding supply ports. Please complete the connect_supply_net
commands for all three supply nets.

5. VDD is the primary power supply and VSS is the primary ground supply for
domain TOP. This needs to be specified in the UPF. Please complete the
set_domain_supply_net command.

6. Before continuing with this task, invoke DC and check to see if your UPF file
reads in cleanly. Remember to source the lab_setup.csh in the installation
directory if you have not already done so.

Change to the following working directory:

UPF_fundamentals/lab1/rm_dc/tmp
% run_dc_leon3s

This will take approximately 5 minutes to run.

Lab 1 9
 7. Log files are written to the “../logs” subdirectory; reports are written to the
“../rpts” directory; data is written to the “../work” directory. Check the log file
to for any errors or warnings from the load_upf command. If you have errors
in your UPF, you can remove the data (make corrections in a separate editor
window) and reload it. Iterate until your UPF loads without issue, then start
the Design Vision GUI.

dc_shell-topo> remove_upf
dc_shell-topo> load_upf ../../leon3s.upf
** Continue when your UPF loads cleanly… **
dc_shell-topo> start_gui

8. Open the Visual UPF GUI via the “Power” pulldown on the main menu of the
DV GUI:

9. The second power domain PD_SW has already been created for the
pd_switchable block. The following questions relate to UPF objects created
in association with that power domain. You can review the leon3s.upf file
directly, or review the UPF using the Visual UPF GUI.

Lab 1 10
 In domain PD_SW, supplies VDD_LOW and VSS are extensions from the
supplies VDD_LOW and VSS created in domain TOP.

Question 4. What is the option used in the create_supply_net command

that allows the re-declaration of VDD_LOW and VSS? (In other
words, how to we reuse these supply nets?)

________________________________________________________________

We create a new supply VDD_LOW_SW in domain PD_SW.

Question 5. Why is this additional supply net required?

________________________________________________________________

Since domain PD_SW can be shut down, a power switch strategy is required.
Look at the create_power_switch command PD_SW_sw
Question 6. What logic signal in Leon3s controls the power switch? What
should be the value of this signal for the power switch to be on?

_________________________________________________________________

Domain PD_SW can “turn off” and domain TOP is “always on”. The boundary
between PD_SW and TOP has to be isolated. Look at the isolation strategy
PD_SW_iso_out.
Question 7. The isolation strategy is only applied to the outputs of PD_SW. Is
this sufficient or do the input ports need to be isolated?

_________________________________________________________________

Since there is a voltage difference between TOP and PD_SW, level shifters are
needed at the interface.
Question 8. Why are two level shifter strategies defined?

_________________________________________________________________

_________________________________________________________________

When you are finished with the Visual UPF GUI, just click
“Cancel” to exit that window, but do not yet exit out of DC.

Lab 1 11
 Task 3. Verifying the correctness of the UPF using DC
and MVRC

1. While still in the DC GUI, execute check_mv_design

Question 9. Did you get any errors or warnings from this command? Can they
be ignored at this point? Why or why not?

_________________________________________________________________

_________________________________________________________________

_________________________________________________________________

2. Exit out of DC:

dc_shell-topo> exit

------------------------------------------------------- ----

3. Change to the MVRC working directory and review the

mvcmp_compile_leon3s.csh script:

% cd ../../rm_mvrc
vi mvcmp_compile_leon3s_compile.csh

This is the compile script required to compile the leon3s design for analysis in
MVRC.

NOTE: To make this script run more efficiently, the files in the individual “mvcmp”
commands having the same “-work” argument could actually be combined into a “file
list”, then sourced with a single “mvcmp -f <file_list>” command.

Lab 1 12
 4. To verify the UPF file leon3s.upf for correctness, you will have to compile
this file into the MVRC database and elaborate the RTL + UPF to run the
static checking rules. This is done using a Makefile. Review the Makefile
and look at the following targets:

compile_leon3s_upf:
mvcmp -upf ../leon3s.upf -error_info | tee leon3s_upf.log;
elaborate:
mvdbgen -top work.leon3s -rc | tee elaborate_leon3s.log;
mvrc:
mvrc -f ${SCRIPTS}/leon3s_rtl.cmd | tee mvrc_leon3s.log
all_leon3s:
clean compile_design compile_leon3s_upf elaborate mvrc

5. Review the mvrc command file leon3s_rtl.cmd. It includes the following:

read_db
report_power_intent -file intent.txt
check_protection -critique -no_design_checks
-severity INFO -file protection.txt
create_root -type clock -signal leon3s:clk
create_root -type reset -signal leon3s:rstn
check_architecture -signal_corruption
-file signal_corruption.txt
exit

6. Compile the files for leon3s:

% make all_leon3s

This should take approximately 3 minutes to execute.

Question 10. Did you get any errors or warnings in the mvrc log summary?
(Look where it says “MVRC completed”) Can these be ignored?

_________________________________________________________________

_________________________________________________________________

Lab 1 13
 Question 11. Scroll back up and look at the “Status” lines for the two checks
that were run. Did they both pass?

_________________________________________________________________

7. Run MVRC in the GUI mode

make gui

8. In the GUI, click on ISO_REQD message in the Summary window.

9. Click on the first of of ISO_REQD messages (1 of 10) in the message window

and the details for this INFO message will pop up in the window on the right.
Review the details for this message.

Question 12. Why are Source and Boundary Source described in this message
different? Hint: To what “boundary” do you think it’s
referring?

_________________________________________________________________

_________________________________________________________________

Lab 1 14
2
Lab2 Leon3mp UPF Lab

Learning Objectives

After completing this lab, you should be able to:

 Determine the flavors of power management cells
available in your target libraries
 Understand the different components of the power intent
for a more complex design
 Debug a UPF file based on the power intent description
and checking / debugging capabilities in DC and MVRC

Lab Duration:
45 minutes
General Lab Flow

Study the power management

library cells to understand
what flavors are available

Study the Leon3mp design

and the desired power intent

Debug and correct issues with

power intent

Verify the corrected UPF for

Leon3mp
using DC and MVRC

Lab 2 16
 Leon3mp Overview

Timer
Leon3s Leon3s Leon3s Leon3s Power GPIO
Processor Processor Processor Processor Controller

IRQ
AHB/APB
Pads Bridge
RST
PWR

Memory AHB RAM PCI Processor

Controller 4K bytes Target Debug UART

For this lab, we instantiate 4 Leon3s cores.

顶层设计/projects/work/randomize/upf_work/new_upf_fundamentals_2018/synthesis_lab/RTL/TOP
leon3mp.vhd 为顶层，控制信号都来自power_controller_top. leon3_p0,p1,p2,p3都是使用power_controller.v复用

Leon3mp
Power Power Diagram
Intent Intent for Leon3mp Core
VDD TOP (1.08V) VDD_LOW
VDD_LOW VDD
VDD p2_sd
p0_sd
LS
ISO VDD_LOWS_p2
VDDS_p0
LS
ISO
u0_0/pd_switchable VDD u0_2/pd_switchable
all_sd LEON3_p2
LEON3_p0
VSS (1.08V / OFF) VSS (0.7V / OFF)
VDD VDDS_misc
p0_isolation p2_isolation
RR
all_isolation ISO
VDD_LOW VDD
VDD
p3_sd
p1_sd
LEON3_misc VDD_LOWS_p3
VDDS_p1 VSS (1.08V / OFF) LS
LS
ISO ISO
p1_isolation
p3_isolation
u0_1/pd_switchable u0_3/pd_switchable
LEON3_p1 LEON3_p3
VSS (1.08V / OFF) VSS (0.7V / OFF)
VSS

© Synopsys 2011 15

Lab 2 17
 • Top level (TOP) power domain consists of the P0 block from each of the four leon3s
cores, and the power controller
– Always on, operating at 1.08v
• Leon3s core power domains
– LEON3_p0 (u0_0/pd_switchable) operating at 1.08v
– LEON3_p1 (u0_1/pd_switchable) operating at 1.08v
– LEON3_p2 (u0_2/pd_switchable) operating at 0.7v
– LEON3_p3 (u0_3/pd_switchable) operating at 0.7v
– Each LEON3_p* domain can be independently shut down with control signals
• Outputs should be isolated, clamped high
• Five separate logical hierarchical cells (sdc, timer0, uart1, uart2, dsu0) form the
power domain LEON3_misc
– Operating at 1.08v
– Can also be shut down
• Outputs should be isolated, clamped high

• Retention is required in domain LEON3_misc

– Retention save signal is all_save (active high) from power controller
– Retention restore signal all_restore (active high) from power controller
– Valid retention cells
• RSDFCD1, RSDFCD2, RSDFCD4
• RSDFCD1HVT, RSDFCD2HVT, RSDFCD4HVT
• RSDFCSD1, RSDFCSD2, RSDFCSD4
• RSDFCSRD1

• All of the power management control signals are driven from the power controller.

Power State Table

Port Voltage Port State
VDD 1.08 VDD_HV
VDD_LOW 0.7 VDD_LV
VSS 0.0 GND
u0_0/pd_switchable/leon3_p0_sw/out 1.08 VDD_HV
off OFF
u0_1/pd_switchable/leon3_p1_sw/out 1.08 VDD_HV
off OFF
u0_2/pd_switchable/leon3_p2_sw/out 0.7 VDD_LV
off OFF
u0_3/pd_switchable/leon3_p3_sw/out 0.7 VDD_LV
off OFF
leon3_misc_sw/out 1.08 VDD_HV
off OFF

Lab 2 18
 Task 1. Understanding the Power Management Cells

This lab will be conducted in the lab2 directory, using the Leon3mp design. If you
have not already done so, be sure to source the lab_setup.csh from the installation
directory.
1. For this part of the lab, you will be running Design Compiler Topographical
(DCT). From installation directory (UPF_fundamentals/), execute the
following:

% cd lab2/rm_dc/tmp
% run_dc_no_upf

This executes the dc_init_no_upf.tcl script, which reads in the design and links in the
libraries, but doesn’t load any UPF power intent, and remains in dc_shell-topo
when the script completes. It should take about 5 minutes to execute.

2. Inside the DC shell, execute the command that generates a report of all the
special mv library cells.

dc_shell-topo> report_...

3. This generates quite a long report, so generate a report on just the level shifter
cells to answer the following questions. Hint: use the -help option or tab
completion to determine what the syntax is for the options for this command.

Question 13. What is the prefix for a high-to-low (HL) level shifter? _______

Question 14. What is the standard cell main rail (scmr) for the HL LS cells?

____________________________________________________________

Question 15. What placement limitations will this create on the cell?

____________________________________________________________
Question 16. What is the prefix for a low-to-high enable level shifter? _______

Question 17. What is the standard cell main rail for the low-to-high ELS cells?

____________________________________________________________
Question 18. What placement limitations will this create on the cell?

____________________________________________________________
Question 19. Are any of the level shifters marked “dont_use”? How can you
determine this?
____________________________________________________________

Lab 2 19
 Question 20. From what’s shown in the report, how does a LS cell differ from an
ELS cell?

____________________________________________________________

4. If you have time, explore the library information for some of the other MV
cell types. When you are finished, do not exit the DC shell.

Task 2. Understanding the Leon3mp UPF

In order to debug the UPF in the next task, you must first understand the desired
power intent for the Leon3mp design. Use the diagrams and details at the beginning
of Lab 2 to answer the following questions

Question 21. Which of the domains will use “-location parent” for the isolation
strategy?

____________________________________________________________

Question 22. In which domain(s) will the power switches need to be created, for
each of the shutdown designs?

____________________________________________________________

____________________________________________________________

Question 23. Where are the input and output level shifters related to the domain
LEON3_p2 shown? Why do you suppose those locations were
chosen?

____________________________________________________________

____________________________________________________________

Question 24. What is the isolation power used to supply the ISO cells in
LEON3_p1? What about LEON3_p2?

____________________________________________________________

____________________________________________________________

Lab 2 20
 Task 3. Debugging the Leon3mp UPF in DC

This task assumes you have already run Task 1, and are still in the same session. If
you are not still in the DC shell, re-run Task 1.

1. Type the following at the DC shell command prompt to start the GUI, then
load the UPF:

dc_shell-topo> start_gui
dc_shell-topo> load_upf ../../leon3mp.upf

Question 25. Did your UPF load cleanly? _______

2. You will find more than one issue. Use the messages in the log file from the
load_upf command execution, along with the Visual UPF GUI, to debug
the issues. Look at the leon3mp.upf file for hints on the missing/incorrect
commands. List them here:

___________________________________________________________________

___________________________________________________________________

___________________________________________________________________

___________________________________________________________________

3. Make corrections to the leon3mp.upf file, remove the UPF loaded into the
design, and reload the corrected UPF. Continue iterating until you have no
errors or warnings from the load_upf command.

dc_shell-topo> remove_upf
dc_shell-topo> load_upf ../../leon3mp.upf

4. Once you have a syntactically correct UPF (i.e., cleanly executed

load_upf), you’ll want to run check_mv_design to ensure you don’t
have strategy or logical power net connectivity violations. Prior to running
check_mv_design, you need to ensure your logical power nets have
voltage values assigned, using the set_voltage command.

dc_shell-topo> source -echo -verbose \

../../DATA_SAED/set_voltage.tcl
dc_shell-topo> check_mv_design

[NOTE: this command will take a few minutes to execute.]

Lab 2 21
 Question 26. Did you get any warnings or errors from check_mv_design?

_______

5. Take another look at the leon3mp.upf file for hints on what’s missing or
incorrect. List what you find here:

___________________________________________________________________

___________________________________________________________________

___________________________________________________________________

6. Make corrections to the leon3mp.upf file, remove the UPF loaded into the
design, reload the corrected UPF, and re-source the set_voltage.tcl script.

dc_shell-topo> remove_upf
dc_shell-topo> load_upf ../../leon3mp.upf
dc_shell-topo> source -echo -verbose \
../../DATA_SAED/set_voltage.tcl

7. Re-run check_mv_design. Note that this command is still analyzing a

pre-synthesized design, so some problems may not show up at this point, and
some problems may be reported that aren’t actually problems.

Question 27. Take another look at the log file for the check_mv_design
command. What errors/warnings are still being reported? Are they
expected? Why or why not?

___________________________________________________________________

___________________________________________________________________

At this point, if you have time, feel free to take a look at the power intent using the
Visual UPF GUI. When you are finished, exit out of the DC shell by typing “quit”.

dc_shell-topo> quit

Lab 2 22
 Task 4. Debugging the Leon3mp UPF in MVRC

This task will utilize MVRC (Synopsys’ multi-voltage static rule checker).

1. Type the following at the unix command prompt to change to the MVRC
working directory and execute the RTL multi-voltage analysis on Leon3mp:

% cd ../../rm_mvrc
(i.e., change directories to the
UPF_Fundamentals/lab2/rm_mvrc directory)

% make all_leon3mp

Question 28. Based on the MVRC command file (leon3mp_rtl.cmd), what

checking commands were executed? What are the names of the
report files generated?

______________________________________________________

______________________________________________________

Question 29. Looking at intent_leon3mp.txt, how many domain crossovers were

reported for the LEON3_misc power domain?

______________________________________________________

2. Invoke the MVRC GUI to look further at your results

% make gui_leon3mp

3. Scroll back in the log window to view the “Status” returned for the check
commands that were executed.
Question 30. Did the MVRC checks pass or fail?

______________________________________________________

4. On the right side of the GUI, in the “Summary” window, double click on
ISOLATION_POLICY_REDUNDANT, then on the left side, under
“Messages” -> “Warning”, click on the “1 of 1” to get the details on the
warning.

Question 31. What is the cause of these warnings?

______________________________________________________

______________________________________________________
Lab 2 23
This completes the workshop labs. Please close all of the tools and editor
windows you may have opened.

We welcome any and all feedback on your experience.

Thank you for your time.

The following slides from the lecture material are included here to assist you
with the labs.