CHAPTER 2

OPERATIONAL AMPLIFIERS

Chapter Outline

2.1 The Ideal Op Amp

2.2 The Inverting Configuration
2.3 The Noninverting Configuration
2.4 Difference Amplifiers
2.5 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance
2.6 Large-Signal Operation of Op Amps
2.7 Integrators and Differentiators
2.8 DC Imperfections
2.9 Op-Amp Applications

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 2.1 THE IDEAL OP AMP
Introduction
Their applications were initially in the area of analog computation and
Instrumentation.
Op amp is very popular because of its versatility.
Op amp circuits work at levels that are quite close to their predicted theoretical
performance.
We will first treat the op amp as a building block and study its terminal
characteristics and its applications.
Op-Amp Symbol and Terminals
Two input terminals: inverting input terminal (−) and non-inverting input terminal (+).
One output terminal.
Two dc power supplies V + and V −.
Other terminals for frequency compensation and offset nulling.

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Ideal Characteristics of Op Amp

Differential-input, single-ended-output amplifier.

Infinite input impedance
i1 = i2 = 0 (regardless of the input voltage)
Zero output impedance
vOUT = A(v2 – v1) (regardless of the load)
Infinite open-loop differential gain
Infinite common-mode rejection
Infinite bandwidth

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741 Op-Amp Schematic

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Typical Op Amp Parameters

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Range where
we operate
the op amp as
an amplifier.

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Differential and Common-Mode Signals

Two independent input signals: v1 and v2

Differential-mode input signal (vId): vId = (v2 – v1)

Common-mode input signal (vIcm): vIcm = (v1 + v2)/2

Alternative expression of v1 and v2:

v1 = vIcm – vId /2
v1 vId /2
v2 = vIcm + vId /2

vIcm vId /2

v2

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 2.2 THE INVERTING CONFIGURATION

The Inverting Close-Loop Configuration

♦ External components R1 and R2 form a close loop.

♦ Output is fed back to the inverting input terminal.
♦ Input signal is applied from the inverting terminal.

Circuit model

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 vk
ik =
Rk
n
 Rf Rf Rf 
vo = 0 − R f  ik = − v1 + v2 + .. vn 
k =1  R1 R2 Rn 
 Rf Rf Rf 
vo = − v1 + v2 + .. vn 
 R1 R2 Rn 

Ra Rc

 R  R   R  R  R  R  R1
vo = v1  a  c  + v2  a  c  − v3  c  − v4  c  v1 Rb
 R1  Rb   R2  Rb   R3   R4  vo
v2
R2 v3

v4

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 2.3 THE NONINVERTING CONFIGURATION

The Noninverting Close-Loop Configuration

♦ External components R1 and R2 form a close loop.

♦ Output is fed back to the inverting input terminal.

♦ Input signal is applied from the noninverting terminal.

Circuit model

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The Voltage Follower
♦ Unity-gain buffer
♦ It is operated in noninverting configuration with G = 1.
♦ Ri = ∞ and Ro = 0
♦ Can be used as a buffer amplifier to connect a source
with a high impedance to a low-impedance load.
Circuit model

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 2.4 DIFFERENCE AMPLIFIER
Difference Amplifier
▪ Ideal difference amplifier
• Amplify only the differential input signal vId
• Reject completely the common-mode input signal vIcm. vId = v2 – v1
vIcm = (v1 + v2)/2
v1 = vIcm – vId/2
v2 = vIcm + vId/2

Single Op-Amp difference amplifier

Analysis Technique (I)
v2
+
v = v2
RF v1 − v + v + − v0
=
RF + R1 R1 RF
v1
R
v0 = F ( v2 − v1 )
R1
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 R1 R2
In general
R2
1+ R3
R R1 v1
v0 = − 2 v1 + v
R1 R3 2
1+
R4
v2
R4
R
1+ 2
R2 v R1 v
v0 = − (vIcm − Id ) + (vIcm + Id )
R1 2 R 2
1+ 3
R4

 R2   R2 
1+  1+ 
v0 = 
R1 R2  1 R1 R2 
− vIcm + + vId
 R3 R1  2 1+ R3 R1 
1+   
 R4   R4 
 R2 
 R2  1+ 
1+   R1 R2 
Ad =
1 R1
+
R2  : differential-mode gain, − : common-mode gain
 R3 R1 
2 1+ R3 R1  1+ 
   R4 
 R4 

If R1/R2 = R3/R4 common-mode gain is zero

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Common Mode Rejection Ratio (CMRR)

Input and Output Impedance

• Output Impedance Ro = 0
• Input Impedance Ri = 2R1
• Large R1 can be used to
increase Ri, but R2 will become
impractically large to maintain
required gain.
• Gain can be adjusted by
changing R1 and R2
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simultaneously
 Instrumentation Amplifier

I = (v1 – v2)/Rgain (v1 – v2)

B
- Differential-mode gain
can be adjusted by
 R1  tuning Rgain.
v AB = 2 IR1 + (v1 − v2 ) = (v1 − v2 ) 2 + 1 - Common-mode gain
 R  is zero
 gain  - Input impedance is
infinite
R3  R  R3
= (v2 − v1 ) 2 + 1
- Output impedance is
v0 = vBA 1
R2  R R zero
 gain  2

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 2.5 EFFECT OF OPEN-LOOP GAIN AND BANDWIDTH

Practical Op Amp Characteristics

• Op amp with finite open-loop gain: Av(jω) = Av0
• Op amp with finite open-loop gain and bandwidth: Av(jω) = Av0 / (1 + jω /ωb)
Frequency response of op amp:

Av0

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Open-Loop Op Amp

The frequency response of an open-loop op amp is approximated by STC

form:

Av(jω) = Avo /(1 + jω / ωb).

At low frequencies (ω << ωb), the open-loop op amp is approximated by

|Av(jω)| ≈ Av0

At high frequencies (ω >> ωb), the open-loop op amp is approximated by

|Av(jω)| ≈ ωb Av0 / ω

Unity-gain bandwidth (ft = ωt /2π) is defined as the frequency at which

|Av(j ωt)| ≈ 1

→ ωt = Av0 ωb
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Inverting configuration using Op Amp with Finite Open Loop Gain

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Input impedance

Output impedance

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Inverting configuration using Op Amp with Finite Gain and Bandwidth

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→ 𝐺𝑜 𝜔3𝑑𝐵 ≈ 𝐴𝑉𝑜 𝜔𝑏

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 2.6 Large Signal Operation Of Op-Amp
Output voltage saturation

Output current limits

iL < iomax

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 2.7 INTEGRATORS AND DIFFERENTIATORS
Inverting configuration with general impedance

The Inverting Integrator

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The Miller Integrator With Parallel Feedback Resistance
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The Op-Amp Differentiator

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 F

1/RFC

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The Differentiator With Series Resistance

RF

1/RFC 1/RC

Vo(jω)/Vi(jω) = - RF/(R + 1/jωC)

= - jωRFC/(1 + j ωRC)
= -RF/R

(ω << 1/RC) is - jωRFC

= 1/RC

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 2.8. DC Imperfections
Offset Voltage
An imaginary voltage source
in series with the user-
supplied input, which effects
an op amp output

What causes VOS?

– Unavoidable mismatches in the
differential stage of the op amp.
It is impossible to perfectly
match all transistors.
Range of magnitude?
– 1mV to 5mV
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How can this offset be reduced?
– offset nulling terminals – A variable resistor (if properly set) may be
used to reduce the asymmetry present and, in turn, reduce offset.
– capacitive coupling – A series capacitor placed between the source
and op amp may be used to reduce offset, although it will also filter
out dc signals.

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 Input Bias and Offset Currents

• input bias current - is the

dc current which must be
supplied to the op-amp
inputs for proper operation
• input offset current - the
difference between bias
current at both terminals

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 36
The non-inverting terminal connects to ground
How can this bias be reduced?
– Placement of R3 as additional resistor between non-inverting
input and ground.
How is R3 defined?
– Parallel connection of R2 and R1

I = IB1R1/(R1 + R2)
I
Vo = -IB2R3 +
IB1 IB1(R1/(R1+R2))R2
IB2
If IB1 = IB2 and vo = 0
then R3 = R1//R2

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 2.9 OP-AMP APPLICATIONS

• Electrocardiogram (EKG) Amplification

– Need to measure difference in voltage from lead 1 and
lead 2
– 50/60 Hz interference from electrical equipment

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• Simple EKG circuit
– Uses differential
amplifier to cancel
common mode signal
and amplify
differential mode
signal

• Realistic EKG circuit

– Uses two non-
inverting amplifiers to
first amplify voltage
from each lead,
followed by
differential amplifier
– Forms an
“instrumentation
amplifier”
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 Use a Wheatstone bridge to
Strain Gauge determine the strain of an
element by measuring the
change in resistance of a
strain gauge

(No strain) Balanced Bridge

R #1 = R #2

(Strain) Unbalanced Bridge

R #1 ≠ R #2

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 Applications
PID Controller – PID Controller Circuit Diagram

VERR PID

Adjust Change
Kp RP1, RP2
Ki RI, CI
Kd RD, CD
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