1.

Any signed negative binary number is recognised by its ________

a) MSB
b) LSB
c) Byte
d) Nibble

2. The parameter through which 16 distinct values can be represented is known as

________
a) Bit
b) Byte
c) Word
d) Nibble

3. If the decimal number is a fraction then its binary equivalent is obtained by

________ the number continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting

4. The representation of octal number (532.2)8 in decimal is ________

a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10

5. The decimal equivalent of the binary number (1011.011)2 is ________

a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10

6. An important drawback of binary system is ________

a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number

7. The decimal equivalent of the octal number (645)8 is ______

a) (450)10
b) (451)10
c) (421)10
d) (501)10
8. The largest two digit hexadecimal number is ________
a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16

9. Representation of hexadecimal number (6DE)H in decimal:

a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160

10. The quantity of double word is ________

a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits

11. The given hexadecimal number (1E.53)16 is equivalent to ____________

a) (35.684)8
b) (36.246)8
c) (34.340)8
d) (35.599)8

12. The octal number (651.124)8 is equivalent to ______

a) (1A9.2A)16
b) (1B0.10)16
c) (1A8.A3)16
d) (1B0.B0)16

13. The octal equivalent of the decimal number (417)10 is _____

a) (641)8
b) (619)8
c) (640)8
d) (598)8

14. Convert the hexadecimal number (1E2)16 to decimal.

a) 480
b) 483
c) 482
d) 484

15. (170)10 is equivalent to ____________

a) (FD)16
b) (DF)16
c) (AA)16
d) (AF)16

16. Convert (214)8 into decimal.

a) (140)10
b) (141)10
c) (142)10
d) (130)10

17. Convert (0.345)10 into an octal number.

a) (0.16050)8
b) (0.26050)8
c) (0.19450)8
d) (0.24040)8

18. Convert the binary number (01011.1011)2 into decimal.

a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.7893)10

19. Octal to binary conversion: (24)8 =?

a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2

20. Convert binary to octal: (110110001010)2 =?

a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8

21. What is the addition of the binary numbers 11011011010 and 010100101?
a) 0111001000
b) 1100110110
c) 11101111111
d) 10011010011

22. Perform binary addition: 101101 + 011011 = ?

a) 011010
b) 1010100
c) 101110
d) 1001000
23. Perform binary subtraction: 101111 – 010101 = ?
a) 100100
b) 010101
c) 011010
d) 011001

24. Binary subtraction of 100101 – 011110 is?

a) 000111
b) 111000
c) 010101
d) 101010

25. Perform multiplication of the binary numbers: 01001 × 01011 = ?

a) 001100011
b) 110011100
c) 010100110
d) 101010111

25. 1’s complement of 1011101 is ____________

a) 0101110
b) 1001101
c) 0100010
d) 1100101

26. 2’s complement of 11001011 is ____________

a) 01010111
b) 11010100
c) 00110101
d) 11100010

27. On subtracting (01010)2 from (11110)2 using 1’s complement, we get

____________
a) 01001
b) 11010
c) 10101
d) 10100

28. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get

____________
a) 0111001
b) 1100101
c) 0110110
d) 1000011
30. On subtracting (001100)2 from (101001)2 using 2’s complement, we get
____________
a) 1101100
b) 011101
c) 11010101
d) 11010111

31. On addition of 28 and 18 using 2’s complement, we get ____________

a) 00101110
b) 0101110
c) 00101111
d) 1001111

32. On addition of +38 and -20 using 2’s complement, we get ____________
a) 11110001
b) 100001110
c) 010010
d) 110101011

33. On addition of -46 and +28 using 2’s complement, we get ____________
a) -10010
b) -00101
c) 01011
d) 0100101

34. On addition of -33 and -40 using 2’s complement, we get ____________
a) 1001110
b) -110101
c) 0110001
d) -1001001

35. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1

36. Binary coded decimal is a combination of __________

a) Two binary digits
b) Three binary digits
c) Four binary digits
d) Five binary digits

37. The decimal number 10 is represented in its BCD form as __________

a) 10100000
b) 01010111
c) 00010000
d) 00101011

38. Add the two BCD numbers: 1001 + 0100 = ?

a) 10101111
b) 01010000
c) 00010011
d) 00101011

39. Carry out BCD subtraction for (68) – (61) using 10’s complement method.
a) 00000111
b) 01110000
c) 100000111
d) 011111000

40. How many bits would be required to encode decimal numbers 0 to 9999 in
straight binary codes?
a) 12
b) 14
c) 16
d) 18

41. The excess-3 code for 597 is given by __________

a) 100011001010
b) 100010100111
c) 010110010111
d) 010110101101

42. The decimal equivalent of the excess-3 number 110010100011.01110101 is

_____________
a) 970.42
b) 1253.75
c) 861.75
d) 1132.87

43. In boolean algebra, the OR operation is performed by which properties?

a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned

44. The expression for Absorption law is given by _________

a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A

45. According to boolean law: A + 1 = ?

a) 1
b) A
c) 0
d) A’

46. The involution of A is equal to _________

a) A
b) A’
c) 1
d) 0

47. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A

48. DeMorgan’s theorem states that _________

a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B

49. (A + B)(A’ * B’) = ?

a) 1
b) 0
c) AB
d) AB’

50. Complement of the expression A’B + CD’ is _________

a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)

51. Simplify Y = AB’ + (A’ + B)C.

a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A

52. The boolean function A + BC is a reduced form of ____________

a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B

53. The expression Y=AB+BC+AC shows the _________ operation.

a) EX-OR
b) SOP
c) POS
d) NOR

54. The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.

a) AND
b) POS
c) SOP
d) NAND

55. A product term containing all K variables of the function in either complemented
or uncomplemented form is called a __________
a) Minterm
b) Maxterm
c) Midterm
d) ∑ term

56. According to the property of minterm, how many combination will have value
equal to 1 for K input variables?
a) 0
b) 1
c) 2
d) 3

57. The canonical sum of product form of the function y(A,B) = A + B is __________
a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’

58. A variable on its own or in its complemented form is known as a __________

a) Product Term
b) Literal
c) Sum Term
d) Word

59. Maxterm is the sum of __________ of the corresponding Minterm with its literal
complemented.
a) Terms
b) Words
c) Numbers
d) Nibble

60. Canonical form is a unique way of representing ____________

a) SOP
b) Minterm
c) Boolean Expressions
d) POS

61. There are _____________ Minterms for 3 variables (a, b, c).

a) 0
b) 2
c) 8
d) 1

62. _____________ expressions can be implemented using either (1) 2-level AND-OR
logic circuits or (2) 2-level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS

63. There are ______ cells in a 4-variable K-map.

a) 12
b) 16
c) 18
d) 8

64. The K-map based Boolean reduction is based on the following Unifying
Theorem: A + A’ = 1.
a) Impact
b) Non Impact
c) Force
d) Complementarity

65. Each product term of a group, w’.x.y’ and w.y, represents the ____________ in that
group.
a) Input
b) POS
c) Sum-of-Minterms
d) Sum of Maxterms

66. The prime implicant which has at least one element that is not present in any
other implicant is known as ___________
a) Essential Prime Implicant
b) Implicant
c) Complement
d) Prime Complement

67. Product-of-Sums expressions can be implemented using ___________

a) 2-level OR-AND logic circuits
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits
d) Both 2-level OR-AND and NOR logic circuits

68. Each group of adjacent Minterms (group size in powers of twos) corresponds to
a possible product term of the given ___________
a) Function
b) Value
c) Set
d) Word

69. Don’t care conditions can be used for simplifying Boolean expressions in
___________
a) Registers
b) Terms
c) K-maps
d) Latches

70. It should be kept in mind that don’t care terms should be used along with the
terms that are present in ___________
a) Minterms
b) Expressions
c) K-Map
d) Latches

71. Using the transformation method you can realize any POS realization of OR-AND
with only.
a) XOR
b) NAND
c) AND
d) NOR
72. There are many situations in logic design in which simplification of logic
expression is possible in terms of XOR and _________________ operations.
a) X-NOR
b) XOR
c) NOR
d) NAND

73. These logic gates are widely used in _______________ design and therefore are
available in IC form.
a) Sampling
b) Digital
c) Analog
d) Systems

74. In case of XOR/XNOR simplification we have to look for the following

_______________
a) Diagonal Adjacencies
b) Offset Adjacencies
c) Straight Adjacencies
d) Both diagonal and offset adjencies

75. Entries known as _______________ mapping.

a) Diagonal
b) Straight
c) K
d) Boolean

76. The output of an EX-NOR gate is 1. Which input combination is correct?

a) A = 1, B = 0
b) A = 0, B = 1
c) A = 0, B = 0
d) A = 0, B’ = 1

77. In which of the following gates the output is 1 if and only if at least one input is
1?
a) AND
b) NOR
c) NAND
d) OR

78. The time required for a gate or inverter to change its state is called __________
a) Rise time
b) Decay time
c) Propagation time
d) Charging time

79. What is the minimum number of two input NAND gates used to perform the
function of two input OR gates?
a) One
b) Two
c) Three
d) Four

80. Odd parity of word can be conveniently tested by ___________

a) OR gate
b) AND gate
c) NAND gate
d) XOR gate

81. The number of full and half adders are required to add 16-bit number is
__________
a) 8 half adders, 8 full adders
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders

82. Which of the following will give the sum of full adders as output?
a) Three point major circuit
b) Three bit parity checker
c) Three bit comparator
d) Three bit counter

83. Which of the following gate is known as coincidence detector?

a) AND gate
b) OR gate
c) NOR gate
d) NAND gate

84. An OR gate can be imagined as ____________

a) Switches connected in series
b) Switches connected in parallel
c) MOS transistor connected in series
d) BJT transistor connected in series

85. How many full adders are required to construct an m-bit parallel adder?
a) m/2
b) m
c) m-1
d) m+1
86. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11

87. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2

88. A universal logic gate is one which can be used to generate any logic function.
Which of the following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND

89. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates

90. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16

91. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH
b) At least one input is LOW
c) All inputs are HIGH
d) All inputs are LOW

92. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates

93. The basic logic gate whose output is the complement of the input is the
___________
a) OR gate
b) AND gate
c) INVERTER gate
d) XOR gate

94. The AND function can be used to ___________ and the OR function can be used to
_____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert

95. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR

96. If we use an AND gate to inhibit a signal from passing one of the inputs must be
___________
a) LOW
b) HIGH
c) Inverted
d) Floating

97. Logic gate circuits contain predictable gate functions that open theirs
____________
a) Outputs
b) Inputs
c) Pre-state
d) Impedance state
View Answer
98. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8

99. Propagation delay is defined as __________

a) the time taken for the output of a gate to change after the inputs have changed
b) the time taken for the input of a gate to change after the outputs have changed
c) the time taken for the input of a gate to change after the intermediates have
changed
d) the time taken for the output of a gate to change after the intermediates have
changed

100. Propagation delay times can be divided as __________

a) t(PLH) and t(LPH)
b) t(LPH) and t(PHL)
c) t(PLH) and t(PHL)
d) t(HPL) and t(LPH)

101. The delay times are measured between the __________ % voltage levels of the
input and output waveforms.
a) 50
b) 75
c) 25
d) 100

102. Power Dissipation in DIC is expressed in __________

a) Watts or kilowatts
b) Milliwatts or nanowatts
c) DB
d) Mdb

103. Fan-in is defined as __________

a) the number of outputs connected to gate without any degradation in the voltage
levels
b) the number of inputs connected to gate without any degradation in the voltage
levels
c) the number of outputs connected to gate with degradation in the voltage levels
d) the number of inputs connected to gate with degradation in the voltage levels

104. The maximum noise voltage that may appear at the input of a logic gate
without changing the logical state of its output is termed as __________
a) Noise Margin
b) Noise Immunity
c) White Noise
d) Signal to Noise Ratio

105. Depending upon the flow of current from the output of one logic circuit to the
input of another the logic families can be divides into _________ categories.
a) 2
b) 3
c) 4
d) 5

106. Fan-in and Fan-out are the characteristics of ___________

a) Registers
b) Logic families
c) Sequential Circuits
d) Combinational Circuits

107. Which of the following options comes under the non – saturated logic family in
Digital Electronics?
a) Emitter – coupled Logic
b) High-Threshold Logic
c) Integrated – injection Logic
d) Diode – Transistor Logic

108. What is a switching function that has more than one output called in Digital
Electronics?
a) Multi-gate function
b) Multi-output function
c) Multiple-gate function
d) Multiple-output function

109. Which characteristic of IC in Digital Circuits represents a function of the

switching time of a particular transistor?
a) Fan – out
b) Fan – in
c) Power dissipation
d) Propagation delay

110. When can one logic gate drive many other logic gates in Digital Electronics?
a) When its output impedance is low and the input impedance is low
b) When its output impedance is high and the input impedance is high
c) When its output impedance is high and the input impedance is low
d) When its output impedance is low and the input impedance is high

111. Which of the following digital logic circuits can be used to add more than 1 – bit
simultaneously?
a) Full – adder
b) Ripple – carry adder
c) Half – adder
d) Serial adder

112. Which gates in Digital Circuits are required to convert a NOR-based SR latch to
an SR flip-flop?
a) Two 2 input AND gates
b) Two 3 input AND gates
c) Two 2 input OR gates
d) Two 3 input OR gates
113. When does a negative level triggered flip-flop in Digital Electronics changes its
state?
a) When the clock is negative
b) When the clock is positive
c) When the inputs are all zero
d) When the inputs are all one

114. Which of the following options represent the synchronous control inputs in an
S – R flip flop?
a) S
b) R
c) Clock
d) Both S and R

115. What must be used along with synchronous control inputs to trigger a change
in the flip flop?
a) 0
b) 1
c) Clock
d) Previous output

116. Which of the following majorly determines the number of emitters in a TTL
digital circuit?
a) Fan – in
b) Fan – out
c) Propagation delay
d) Noise immunity

117. What will be the output from a D flip – flop if the clock is low and D = 0?
a) 0
b) 1
c) No change
d) Toggle between 0 and 1

118. What are the basic gates in MOS logic family?

a) NAND and NOR
b) AND and OR
c) NAND and OR
d) AND and NOR

119. How must the output of a gate in a TTL digital circuit act when it is HIGH?
a) Acts as a voltage source
b) Acts as a current sink
c) Acts as a current source
d) Acts as a voltage sink

120. What is the minimum distance required for single error detection according to
Hamming’s analysis in Digital Electronics?
a) 1
b) 2
c) 3
d) 4

121. Which of these error-detecting codes enables to find double errors in Digital
Electronic devices?
a) Parity method
b) Check sum method
c) Bit generation method
d) Odd-Even method

122. What will be the output from a D flip-flop if D = 1 and the clock is low?
a) No change
b) Toggle between 0 and 1
c) 0
d) 1

123. What characteristic will a TTL digital circuit possess due to its multi-emitter
transistor?
a) Low capacitance
b) High capacitance
c) Low inductance
d) High inductance

124. What input should be given to “S” when SR flip – flop is converted to JK flip –
flop?
a) K.Q
b) K.Q
c) J.Q
d) J.Q

125. What value is to be considered for a “don’t care condition”?

a) 0
b) 1
c) Either 0 or 1
d) Any number except 0 and 1

126. What is the group of 1s in 4 cells of a K – map called?

a) Pair
b) Quad
c) Octet
d) Octave

127. What will be the frequency of the output from a JK flip – flop, when J = 1, K = 1,
and a clock with pulse waveform is given?
a) Half the frequency of clock input
b) Equal to the frequency of clock input
c) Twice the frequency of clock input
d) Independent of the frequency of clock input

128. What gate is placed between clock input and the input of AND gate to convert a
positive level triggered flip – flop to a negative level triggered flip – flop?
a) NOR gate
b) NOT gate
c) Buffer
d) NAND gate

129. In Digital Circuits, which of the following options represent the synchronous
control inputs in a T flip flop?
a) T
b) 0
c) Clock
d) 1

130. What will a TTL digital circuit possess due to the presence of a multi – emitter
transistor?
a) Smaller resistance
b) Larger area
c) Smaller area
d) Larger resistance

131. How must the output of a gate act when it is LOW in a TTL circuit?
a) Acts as a voltage source
b) Acts as a current sink
c) Acts as a current source
d) Acts as a voltage sink

132. Which of the following gives the correct number of multiplexers required to
build a 32 x 1 multiplexer?
a) Two 16 x 1 mux
b) Three 8 x 1 mux
c) Two 8 x 1 mux
d) Three 16 x 1 mux
133. What must be the input given to “R” when SR flip – flop is converted to JK flip –
flop?
a) K.Q
b) K.Q
c) J.Q
d) J.Q

134. What minimum distance is required for a single error correction according to
Hamming’s analysis in Digital Electronics?
a) 1
b) 2
c) 3
d) 4

135. How many errors can the Digital Electronics parity method can find in a single
word?
a) Single error
b) Double error
c) Triple error
d) Multiple errors

136. What is the group of 1s present in 8 cells of a K – map called?

a) Pair
b) Quad
c) Octet
d) Octave

137. Which of these flip – flops cannot be used to construct a serial shift register?
a) D – flip flop
b) SR flip – flop
c) T flip – flop
d) JK flip – flop

138. Which of these options represent the other name of Inter – Integrated logic?
a) Merged Transistor Logic
b) Emitter – Coupled Logic
c) High threshold logic
d) Resistor – Transistor logic

139. Which of the following options is a Current – Mode logic used in Digital Circuits?
a) TTL
b) RTL
c) ECL
d) IIC
139. How many AND gates are required to construct a 4 – bit parallel multiplier if
four 4 – bit parallel binary adders are given?
a) Four 2 – input AND gates
b) Eight 2 – input AND gates
c) Sixteen 2 – input AND gates
d) Two 2 – input AND gates

140. How many cycles of addition and shifting in a 4 – bit multiplier are required to
perform multiplication using the shift method?
a) 1
b) 2
c) 4
d) 8

141. How many 4 – bit parallel binary adders will be required to construct a 4 – bit
parallel multiplier?
a) 1
b) 2
c) 4
d) 8

142. What kind of operation occurs in a J – K flip flop when both inputs J and K are
equal to 1?
a) Preset operation
b) Reset operation
c) Clear operation
d) Toggle operation

143. Which of the following codes is a sequential code?

a) 8421 code
b) 2421 code
c) 5421 code
d) 2441 code

144. Which of these code pairs correctly represent Digital Electronics reflective
codes?
a) 2421 and 5211
b) 2421 and 8421
c) 5211 and 8421
d) 5421 and 2421

145. Which of the following options correctly represent the characteristic of Excess –
3 code?
a) It is a reflexive as well as a sequential code
b) It is a reflexive code but not a sequential code
c) It is a sequential code but not a reflexive code
d) It is neither a reflexive code nor a sequential code

146. The result “X + XY = X” follows which of these laws?

a) Consensus law
b) Distributive law
c) Duality law
d) Absorption law

147. Which of the following options correctly represents the consensus law of Digital
Circuits?
a) AB + AC + BC = AB + AC
b) AB + AC + BC = AB + AC
c) AB + AC + BC = AB + AC
d) AB + AC + BC = AB + AC

148. Which of the following points is not correct regarding an Ex – NOR gate in
Digital Electronics?
a) It is a one – bit comparator
b) It is a buffer
c) It is a one – bit inverter
d) It is a universal gate

149. Which gate is called the anti – coincidence and coincidence gate respectively?
a) XNOR and XOR
b) AND and OR
c) OR and AND
d) XOR and XNOR

150. What frequency division of the pulsed clock signal can be obtained by
connecting 4 flip – flops in cascade?
a) 2
b) 4
c) 8
d) 16

151. Which of the following options represent the correct reduction of XYZ + XYZ ?
a) 0
b) YZ
c) X + X
b) 2YZ

152. A priority encoder has four inputs I0, I1, I2, and I3 where I3 has the highest priority
and I0 has the least priority. If I2 = 1, what will be the output?
a) 00
b) 01
c) 10
d) 11

153. Which of the following options are correct for a 4×1 multiplexer?
a) It has four 3 – input AND gates
b) It has four 2 – input AND gates
c) It has one 3 – input AND gate
d) It has one 3 – input AND gate

154. What determines the output from the combinational logic circuit in Digital
Electronics?
a) Input signals from the past condition
b) Input signals at the present moment
c) Input signals from both past and present
d) Input signals expected in future

155. Which of these pins will allow to activate and deactivate a multiplexer?
a) Enable pin
b) Selection pin
c) Logic pin
d) Preset pin

156. The full form of SIPO is ___________

a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out

157. A shift register that will accept a parallel input or a bidirectional serial load and
internal shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion

158. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF

159. What is meant by the parallel load of a shift register?

a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data

160. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit
parallel output shift register with an initial state 01110. After three clock pulses, the
register contains ________
a) 01110
b) 00001
c) 00101
d) 00110

161. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to
store the nibble 1100. What will be the 4-bit pattern after the second clock pulse?
(Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111

162. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data
nibble 0111 is waiting to enter. After four clock pulses, the register contains ________
a) 0000
b) 1111
c) 0111
d) 1000

163. With a 200 kHz clock frequency, eight bits can be serially entered into a shift
register in ________
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms

164. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz
to achieve a time delay (td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us

165. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW.
The nibble 0111 is waiting to be entered on the serial data-input line. After two clock
pulses, the shift register is storing ________
a) 1110
b) 0111
c) 1000
d) 1001

166. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0.

After three clock pulses, the data outputs are ________
a) 1110
b) 0001
c) 1100
d) 1000

167. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit
parallel output shift register with an initial state 11110000. After two clock pulses,
the register contains ______________
a) 10111000
b) 10110111
c) 11110000
d) 11111100

168. By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it

becomes a ________ ________ and ________ out register.
a) Parallel-in, serial, parallel
b) Serial-in, parallel, serial
c) Series-parallel-in, series, parallel
d) Bidirectional in, parallel, series

169. What type of register would have a complete binary number shifted in one bit
at a time and have all the stored bits shifted out one at a time?
a) Parallel-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-in Parallel-out

170. In a 4-bit Johnson counter sequence, there are a total of how many states or bit
patterns?
a) 1
b) 3
c) 4
d) 8

171. If a 10-bit ring counter has an initial state 1101000000, what is the state after
the second clock pulse?
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000

172. How much storage capacity does each stage in a shift register represent?
a) One bit
b) Two bits
c) Four bits
d) Eight bits

173. Which of the following has the lowest access time?

a) RAM
b) ROM
c) Registers
d) Flag

174. A sequential access memory is one in which __________

a) A particular memory location is accessed rapidly
b) A particular memory location is accessed sequentially
c) A particular memory location is accessed serially
d) A particular memory location is accessed parallely
175. An example of sequential access memory is __________
a) Floppy disk
b) Hard disk
c) Magnetic tape memory
d) RAM

176. A Random Access Memory is one in which __________

a) Any location can be accessed sequentially
b) Any location can be accessed randomly
c) Any location can be accessed serially
d) Any location can be accessed parallely

177. An example of RAM is __________

a) Floppy disk
b) Hard disk
c) Magnetic tape memory
d) Semiconductor RAM

178. A static memory is one in which __________

a) Content changes with time
b) Content doesn’t changes with time
c) Memory is static always
d) Memory is dynamic always
179. A dynamic memory is one in which __________
a) Content changes with time
b) Content doesn’t changes with time
c) Memory is static always
d) Memory is dynamic always

180. Volatile memory refers to __________

a) The memory whose loosed data is achieved again when power to the memory
circuit is removed
b) The memory which looses data when power to the memory circuit is removed
c) The memory which looses data when power to the memory circuit is applied
d) The memory whose loosed data is achieved again when power to the memory
circuit is applied

181. Non-volatile memory refers to __________

a) The memory whose loosed data is retained again when power to the memory
circuit is removed/applied
b) The memory which looses data when power to the memory circuit is removed
c) The memory which looses data when power to the memory circuit is applied
d) The memory whose loosed data is achieved again when power to the memory
circuit is applied
182. The example of non-volatile memory device is __________
a) Magnetic Core Memory
b) Read Only Memory
c) Random Access Memory
d) Both Magnetic Core Memory and Read Only Memory