UMBB - IGEE Digital systems II with VHDL

Spring 2024 EE222 – L04

Lab work # 1
Combinational circuit analysis and design (2)
Objectives
The objective of this lab assignment is to explore fundamental concepts related to arithmetic circuits and
their applications using fixed-function ICs, schematic design, and VHDL modeling.

Note: The pre-lab of each problem must be prepared before coming to the lab!
You may use the provided Quartus II lab manual for project and file creations and tools’ utilization.

Problem 1 – Using the 74181 ALU IC

The 74181 (Fig.1) is a 4-bit high-speed parallel
Arithmetic Logic Unit (ALU) that can perform a
variety of logic and arithmetic operations on two 4-bit
variables. The functionality is determined by 4-bit
selection inputs (S) and the operation mode input (M),
as illustrated in Fig.2.
Fig.1: The 74181 IC pinout

Fig.2: The 74181 IC function table for active-high inputs and outputs.
Notes:
• The arithmetic operations of the 74181 ALU are expressed in 2’s complement notation.
• In the ALU function table: (+) is the logic OR function, (PLUS) is the arithmetic addition, H stands
for high-level (logic 1), and L stands for Low-level (logic 0).
Pre-lab: Draw the function table with all possible operations for: A=0110, B=0111, Cn=0 (no carry).
S3 S2 S1 S0 M=1 M=0, Cn=0
(Op Selection) (Logic operations) (Arithmetic operations)
0 0 0 0 ….. ….
0 0 0 1 ….. …..
….. ….. …..

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UMBB - IGEE Digital systems II with VHDL
Spring 2024 EE222 – L04

In-Lab: Insert the 74181 IC into the Digi-designer, connect four switches to the selection inputs, and four
LEDs to the outputs, then test the IC functionality.
Hints: Set the operand (A and B) and the mode input (M) to +Vcc (1s) for high logic and GND (0s) for
low logic. Additionally, note that unconnected input pins are by default set to logic 1.

Problem 2 – Adder/Subtractor circuit design

Pre-lab: Design a 3-bit Adder/Subtractor circuit (one circuit) using full-adder blocks and gates. The
design should include 3-bit operands (B2, B1, B0, A2, A1, A0), a 1-bit mode input (M, where M=0 for
addition and M=1 for subtraction), a 3-bit output result (R2, R1, R0), status flags (overflow occurrence V,
negative number N, and zero flag Z), and a 1-bit carry-out (Cout), then write the structural VHDL code that
implements the adder/subtractor circuit design.

In-lab: In a new directory (D:\lab1\pbm2\):

1. Create a new Quartus project, then new VHDL file. Save it as: add_sub.
2. Create another VHDL file, then save it as: full_add, and write the VHDL code of the full-adder block.
3. Write the structural VHDL code of the add_sub circuit. Save, then start analysis and synthesis.
4. Perform functional simulation for a set of input combinations and verify the result (consider signed and
unsigned inputs and output)
5. Assign pins, compile, then download the overall design onto the DE2 board to test its functionality.

Problem 3 – 4-bit ALU with VHDL

Pre-lab: Using if-then statements and the table of Fig.3, write a VHDL code of a 4-bit, 16-operation
ALU provided with the CF, NF and ZF flags.
Sel Y Description Sel Y Description
0000 a AND b Bitwise AND 1000 a+b a plus b
0001 a OR b Bitwise OR 1001 a-b a minus b
0010 Not a 1’s complement a 1010 INC a Increment a
0011 a NAND b Bitwise NAND 1011 DEC a Decrement a
0100 a NOR b Bitwise NOR 1100 INC b Increment b
0101 Not b 1’s complement b 1101 DEC b Decrement b
0110 a XOR b Bitwise XOR 1110 NOT a +1 2’s complement of a
0111 a XNOR b Bitwise XNOR 1111 NOT b +1 2’s complement of b

Fig.3: 4-bit ALU function table

In-lab: In a new directory (D:\lab9\pbm3\):

1. Create a new Quartus project then new VHDL file. Save the file then start typing the VHDL code.
2. Start analysis and synthesis and check and correct any errors appear in the “Messages” window.
3. Conduct functional simulation with some input combinations, then verify your output waveforms.
4. Assign pins, then compile the overall design.
5. After successful compilation, download the design onto the DE2 board to test its functionality.

Extra work: Use the 7-segment display to display the ALU output result.