Sixth Semester B.

Tech (EC)
EC-302 VLSI Design
Assignment 1
Due Date: 20/03/2024
Max. Marks 20
Note: Answer any five questions. Assume suitable missing data if any.
5. Design a resistive load inverter with R = 1 KΩ, such that VOL = 0.6 V. The enhancement type
nMOS driver transistor has the following parameters:
VDD = 5.0 V
VT0 = 1.0 V
γ = 0.2 V1/2
λ=0
µnCOX = 22.0 µA/V2
(a) Determine the required aspect ratio, W/L.
(b) Determine VIL and VIH.
(c) Determine noise margin NML and NMH. [CO2-An]

6. Consider a CMOS inverter circuit with following parameters:

VDD = 3.3 V
VT0,n = 0.6 V
VT0,p = -0.7 V
kn = 200 µA/V2
kp = 80 µA/V2
Calculate the noise margins of the circuit, Notice that the CMOS inverter being considered here
has kR = 2.5 and VT0,n ≠ |VT0,p|; hence it is not a symmetric inverter. [CO2-An]

7. Consider a CMOS inverter with the following parameters:

nMOS: 𝑽𝑻𝑶,𝒏 = 𝟏. 𝟎 𝑽 𝝁𝒏𝑪𝒐𝒙 = 𝟒𝟓 𝝁𝑨⁄𝑽2 (𝑾⁄𝑳)𝒏 = 𝟏𝟎
pMOS: 𝑽𝑻𝑶,𝒑 = -𝟏. 𝟐 𝑽 𝝁𝒑𝑪𝒐𝒙 = 𝟐𝟓 𝝁𝑨⁄𝑽2 (𝑾⁄𝑳)p = 𝟐𝟎
The power supply voltage is 5 V, and the output load capacitance is 1.5 pF.
(a) Calculate the rise time and the fall time of the output signal using
(i) Exact method (differential equations)
(ii) Average Current Method
(b) Determine the maximum frequency of periodic square-wave input signal so that the
output voltage can still exhibit a full logic swing from 0 V to 5 V in each cycle. [CO2-An]
(c) Calculate the dynamic power dissipation at this frequency.
8. Sketch the capacitances of M1 in Fig. as VX varies from zero to 3 V. Assume VTH = 0.6 V and λ = γ
= 0. [CO1-An]