BG96 Reference Design

LTE Module Series

Rev. BG96_Reference_Design_Rev.A

Date: 2017-08-14

www.quectel.com
 LTE Module Series
BG96 Reference Design

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GENERAL NOTES

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PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT

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Copyright © Quectel Wireless Solutions Co., Ltd. 2017. All rights reserved.

BG96_Reference_Design Confidential / Released 1/4

 LTE Module Series
BG96 Reference Design

About the Document

History

Revision Date

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Author Description

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A 2017-08-14 Lyndon LIU Initial

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BG96_Reference_Design Confidential / Released 2/4

 LTE Module Series
BG96 Reference Design

Contents

About the Document ................................................................................................................................... 2

Contents ....................................................................................................................................................... 3

1 Reference Design ................................................................................................................................. 4

1.1. Introduction ................................................................................................................................ 4
1.2. Schematics ................................................................................................................................ 4

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BG96_Reference_Design Confidential / Released 3/4

 LTE Module Series
BG96 Reference Design

1 Reference Design

1.1. Introduction

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This document provides the reference design for Quectel BG96 module.

1.2. Schematics

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The schematics illustrated in the following pages are provided for your reference only.

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BG96_Reference_Design Confidential / Released 4/4

 6 5 4 3 2 1

Module Interface

VBAT_RF [2,3]
ANT_MAIN [6]
l
D D
U101-B
63 RESERVED GND 102
[7] GPIO64 64 GPIO64 GND 101

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65 RESERVED GND 100
66 RESERVED RESERVED 99

62
61
60
59
58
57
56
55
54
53
52
51
50
67 98

t
GND RESERVED

GND
GND
ANT_MAIN
GND
GND
RESERVED
RESERVED
GND
GND
VBAT_RF
VBAT_RF
RESERVED
GND
68 GND RESERVED 97
69 GND RESERVED 96
1 49

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[5] PSM_IND PSM_IND ANT_GNSS ANT_GNSS [6] 70 95
Note 4 [1] ADC1 2 ADC1 GND 48
71
GND RESERVED
94

c
3 47 GND RESERVED
Note 2 4
GND USIM_GND
46
USIM_GND [4] 72 GND RESERVED 93
[8] CODEC_PCM_CLK PCM_CLK USIM_CLK USIM_CLK [4] 73 92
5 45 GND RESERVED
[8] CODEC_PCM_SYNC PCM_SYNC USIM_DATA USIM_DATA [4] 74 91

a
6 44 GND GND
Note 5 [8] CODEC_PCM_IN PCM_IN USIM_RST USIM_RST [4]
[1] USB_BOOT 75 USB_BOOT GND 90

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7 43

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[8] CODEC_PCM_OUT PCM_OUT USIM_VDD USIM_VDD [4] 76 89
8 42 RESERVED GND
[5,7] USB_VBUS USB_VBUS USIM_PRESENCE USIM_PRESENCE [4] 77 88
R106 0R 9 41 RESERVED RESERVED
[5] USB_DP USB_DP U101-A I2C_SDA I2C_SDA [8]

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78 RESERVED RESERVED 87
[7] USB_DP_TEST R107 NM_0R 10 BG96 40
USB_DM I2C_SCL I2C_SCL [8] Note 5 79 GND RESERVED 86
R108 0R C

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[5] USB_DM 80 85
R109 NM_0R 11 39 GND RESERVED
C [7] USB_DM_TEST
12
RESERVED RI
38
RI_MODULE [4] 81 GND RESERVED 84
RESERVED DCD DCD_MODULE [4] 82 83

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13 37 GND RESERVED
RESERVED RTS RTS_MODULE [4]
14 RESERVED CTS 36
CTS_MODULE [4] BG96
Note 3 [5,7] PWRKEY 15 PWRKEY TXD 35 TXD_MODULE [4]
16 RESERVED RXD 34 RXD_MODULE [4]

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[5] RESET_N 17 RESET_N VBAT_BB 33

UART3_RXD
UART3_TXD
RESERVED

18 32
AP_READY

[5] W_DISABLE# W_DISABLE# VBAT_BB VBAT_BB [2,3]

DBG_RXD
NETLIGHT

DBG_TXD

VDD_EXT
STATUS

GPIO26

USB_BOOT Design
ADC0

GND
DTR
19
20
21
22
23
24
25
26
27
28
29
30
31
J101
T-PIN-1X2

1
2
f
R105 10K
DTR_MODULE [4] [1] USB_BOOT VDD_EXT [1,2,3,4,5]
R117 0R
VDD_EXT [1,2,3,4,5]
D101
[5] AP_READY

[7] DBG_RXD
[7] DBG_TXD
[5,7] STATUS
[7] NETLIGHT

[1] ADC0

R110 0R ESD9X3.3ST5G
RXD3_MODULE [5]

n
R112 0R
TXD3_MODULE [5]
B GPIO26 [7]
B
Note 4 Note:
When USB_BOOT is at high level, the module will be forced into download mode.

o
Note 2
Notes:
1. Keep all RESERVED and unused pins unconnected, and all GND pins should be connected to ground.
ADC Design
2. ADC pin can not be directly connected to the power supply and must not exceed the voltage range. 490K 1% R101
ADC1_INPUT ADC1 [1]

C
Power saving can be realized through using ADCx_M signal to control ADC sampling.
3. It is recommended to reserve the test points for upgrading the firmware over USB interface and 490K 1% R102
ADC0_INPUT ADC0 [1]
minimize the stub length of USB test signals.
4. The funcitons of PSM_IND and AP_READY pins are under development. R104 R103
490K 1% 490K 1%
5. PCM and I2C funtions are used together for Audio Codec design.
Audio function is under development.

Q101
Q102
D

D
G G
[5] ADC0_M ADC1_M A
Quectel Wireless Solutions

RUM001L02T2CL
[5]

RUM001L02T2CL
S

S
A
DRAWN BY PROJECT TITLE
Lyndon LIU BG96 Reference Design
Note 2 SIZE VER
CHECKED BY A2 A
Woody WU SHEET 1 OF 9 DATE 2017/8/14

6 5 4 3 2 1
 6 5 4 3 2 1

Power Supply Design (Standard)

DC-DC Application Power Supply for Audio Codec

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D It is used when the input voltage is above 7V. First use a DC-DC converter to convert the D
high input voltage into a 5V output, and then the LDO will generate a 3.8V typical voltage
for the module.

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e.g. DC12V in DC 5V out DC 3.8V out for module
DC-DC LDO BG96
U202

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SGM2019-ADJYN5G/TR
VDD_3.3V = (R0305/R0308+1)*1.207 = 3.3V
DC 3.3V out for Codec 1 IN
LDO [2] DC_5V OUT 5 VDD_3.3V [3,8]

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Codec C214 C215 3 EN R210
BP 4

2 GND
DC 1.8V out for Codec 73.2K 1%
LDO C216 C217 C218
1uF 100nF
Note: 4.7uF 100nF 33pF
R209

a
Customers should choose only one of them from standard and battery power supply modes. 51K R211
42.2K 1%

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Q207

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[3,5] CODEC_POWER_ENA
DTC043ZE
LDO Design

[2,3,8] VDD_1V8
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C

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C It is used when the input voltage is below 7V.
VBAT

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U201 MIC29302WU
+5V
[2] DC_5V 2 IN OUT 4
C201 C202 R201 R202 C203 C204 C205 R204
+

+
D201

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GND

100K
5 ADJ

51K 470R
1 EN

TVS 470uF 100nF 1% 470uF 33pF 10pF

3

R203 U203
47K SGM2019-ADJYN5G/TR VDD_1V8 = (R0310/R0312+1)*1.207 = 1.8V
1% 1 IN
[2] DC_5V OUT 5 VDD_1V8 [2,3,8]
[5] MCU_POWER_ON/OFF Q201 3 EN R214 C221 C222 C223
C219 BP 4

2 GND
C220 39K 1%
DTC043ZE R220
4.7uF 100nF 33pF
1uF 100nF NM_51K

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R221 R215
VBAT = (R202/R203+1)*1.24 = 3.88V R212 100K 75K 1%
[1,3,4,5] VDD_EXT
0R

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B B

VBAT Design

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VBAT

R222 0R
VBAT_BB [1,3]

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R223 0R
VBAT_RF [1,3] Notes:
C206 C207 C208 C209 C210 C211 C212 C213 1. CODEC_POWER_ENA must be at low level in order to ensure the normal output voltage of VDD_3.3V.
+

D204
100uF 100nF 33pF 10pF 100uF 100nF 33pF 10pF If VDD_3.3V power supply needs to be switched off, please keep CODEC_POWER_ENA at high level.
PZ3D4V2H
2. To ensure that the audio codec works normally, please follow the power-on and power-off sequences of its power supply.
Power ON Sequence: power on VDD_1V8 first, and then VDD_3V3.
Close to the module VBAT pins Power OFF Sequence: power off VDD_3V3 first, and then VDD_1V8.

A
A Quectel Wireless Solutions
Note:
DRAWN BY PROJECT TITLE
VBAT should be routed in star structure to VBAT_BB and VBAT_RF pins. Lyndon LIU BG96 Reference Design
SIZE VER
CHECKED BY A2 A
Woody WU SHEET 2 OF 9 DATE 2017/8/14

6 5 4 3 2 1
 6 5 4 3 2 1

Power Supply Design (Battery)

Battery Application Power Supply for Audio Codec

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D The following is the battery application scheme block diagram. D
The output voltage of batteries must stay between 3.3V and 4.3V.

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DC 3.3~4.2V out for module
Batteries BG96
U302

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SGM2019-ADJYN5G/TR
VDD_3.3V = (R0305/R0308+1)*1.207 = 3.3V
DC 3.3V out for Codec 1 IN
LDO [2,3,5,7] VBAT OUT 5 VDD_3.3V [2,8]

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Codec C310 C311 3 EN R305
BP 4

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DC 1.8V out for Codec

2 GND
73.2K 1%
LDO C312 C313 C314
1uF 100nF
4.7uF 100nF 33pF
R304

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Note: 51K R306
42.2K 1%

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Customers should choose only one of them from standard and battery power supply modes. Q301

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[2,5] CODEC_POWER_ENA
DTC043ZE

[2,3,8] VDD_1V8
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Battery Polarity Protection for BG96 C

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C

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VBATT VBAT
U301
4 1

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D S
7 2
D S
5
S
6
S
BATT1 3 8 U303
G S
C301 SGM2019-ADJYN5G/TR VDD_1V8 = (R0310/R0312+1)*1.207 = 1.8V
CSD25310Q2 1 IN
100uF [2,3,5,7] VBAT OUT 5 VDD_1V8 [2,3,8]
X5R
BATT2 3216 3 EN R310 C317 C318 C319
C315 BP 4

2 GND
C316 39K 1%
R307
4.7uF 100nF 33pF

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1uF 100nF NM_51K

R309 R311
R308 100K 75K 1%
[1,2,4,5] VDD_EXT

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0R
B B

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VBAT Design
VBAT
Notes:

C
R302 0R 1. CODEC_POWER_ENA must be at low level in order to ensure the normal output voltage of VDD_3.3V.
VBAT_BB [1,2]
If VDD_3.3V power supply needs to be switched off, please keep CODEC_POWER_ENA at high level.
R303 0R 2. To ensure that the audio codec works normally, please follow the power-on and power-off sequences of its power supply.
VBAT_RF [1,2]
Power ON Sequence: power on VDD_1V8 first, and then VDD_3V3.
C302 C303 C304 C305 C306 C307 C308 C309
+

D301 Power OFF Sequence: power off VDD_3V3 first, and then VDD_1V8.
100uF 100nF 33pF 10pF 100uF 100nF 33pF 10pF
PZ3D4V2H

Close to the module VBAT pins A

A Quectel Wireless Solutions
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Note: Lyndon LIU BG96 Reference Design
VBAT should be routed in star structure to VBAT_BB and VBAT_RF pins. SIZE VER
CHECKED BY A2 A
Woody WU SHEET 3 OF 9 DATE 2017/8/14

6 5 4 3 2 1
 6 5 4 3 2 1

UART and (U)SIM Designs

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D D

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UART Level Translator (U)SIM Design

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[1,4] USIM_VDD VDD_EXT[1,2,3,4,5]
U401
R401 51K 1 A1 R402 51K [1,4] USIM_VDD
B1 20

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2 VCCA VCCB 19

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[1,2,3,4,5] VDD_EXT VDD_MCU [5] R408 R409
3 A2 15K 51K
[1] RI_MODULE B2 18 RI [5] C406 100nF

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[1] DCD_MODULE 4 A3 B3 17 DCD [5] J401
C

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[1] RTS_MODULE 5 A4 B4 16 USIM_GND [1]
RTS [5] VCC GND
C 6 A5 R405 0R
[1] RXD_MODULE B5 15 RXD [5] [1] USIM_RST RST VPP

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7 A6 R406 0R
[1] DTR_MODULE B6 14 DTR [5] [1] USIM_CLK CLK I/O
[1] CTS_MODULE 8 A7 B7 13 [1] USIM_PRESENCE
CTS [5] PRESENCE

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[1] TXD_MODULE 9 A8 B8 12 Molex 91228
TXD [5]
R404 10K
[1,2,3,4,5] VDD_EXT 10 OE GND 11
R407 0R
[1] USIM_DATA
TXS0108EPWR C402
C401 R403 100nF
120K C403 C404 C405
100nF
33pF 33pF 33pF Note 5

4
5
6
3
f
2
U402 ESDA6V8AV6

Notes: Notes:

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B 1. TXS0108EPWR is used to realize the voltage level translation between BG96 and MCU. 1. R405~R407 are applied to facilitate debugging. It is recommended to reserve the series resistors for B
2. VCCA should not exceed VCCB. For more information about TXS0108EPWR, please (U)SIM signals of the module.
refer to the datasheet from TI website. 2. R408 can improve anti-jamming capability of the (U)SIM circuit.

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3. BG96 supports (U)SIM card hot-plugging, which can be implemented through USIM_PRESENCE pin.
4. The value of C406 should be less than 1uF.
5. Parasitic capacitance of the ESD array should not exceed 15pF.
6. If the system ground plane is complete, USIM_GND can be connected to the system ground directly.

6 5
C 4 3 2
Woody WU
Quectel Wireless Solutions
DRAWN BY
Lyndon LIU

CHECKED BY
SHEET
PROJECT
BG96
SIZE
A2
4 OF 9 DATE

1
TITLE
Reference Design
VER
A
2017/8/14
A
 6 5 4 3 2 1

MCU Interface
U501

1 [1,2,3,4,5] VDD_EXT VDD_EXT [1,2,3,4,5]

VDD VDD_MCU [4,5] RESET_N [1]
2

l
D GND
3
D
TXD RXD [4]
4
RXD TXD [4] [5] MCU_RESET
5 R501 R502 C502
RTS RTS [4] 1nF Q504
6 4.7K 4.7K DTC043ZE
CTS CTS [4]

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7
DTR DTR [4]
8
DCD DCD [4]

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RI 9 [4]
RI Q501 2SC4617TLQ
10 R503 0R [1] AP_READY
VBUS USB_VBUS [1,5,7] AP_READY_M [5]
11

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VBUS_CONTROL VBUS_CTRL [5]
12
USB_DP USB_DP [1]

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USB_DM 13
USB_DM [1]
USB_ID 14
15
GPIO_01 MCU_PWRKEY [5]

a
16 PWRKEY [1,7]
GPIO_02 PSM_IND_M [5] W_DISABLE# [1]

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17
MCU_RESET [5]

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GPIO_03
18
GPIO_04 AP_READY_M [5]
19 C504
GPIO_05 MCU_POWER_ON/OFF [2] [5] MCU_PWRKEY

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20 Q503 10nF
GPIO_06 W_DISABLE_M [5] [5] W_DISABLE_M C505 DTC043ZE
Q502
21 10nF C

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GPIO_07 CODEC_POWER_ENA [2,3] DTC043ZE
22
C GPIO_08
23
ADC0_M [1]
GPIO_09 ADC1_M [1]

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GPIO_10 26 STATUS_N [5]
GPIO_11 27
S_TXD 24 RXD3 [5]
S_RXD 25 TXD3 [5] [4,5] VDD_MCU

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[4,5] VDD_MCU R530
Notes: 10K
1. U501 represents customer's MCU. R506
10K STATUS_N [5]
2. Pay attention to the UART connection of RTS/CTS.
3. BG96 can only work as a USB device and supports FS/HS mode. PSM_IND_M [5]
[1,7] STATUS
Q510
To communicate with USB interface, MCU needs to support USB host or OTG function. DTC043ZE

f
The USB interface is primarily used for AT command communication, data transmission, software [1] PSM_IND
Q509
debugging and firmware upgrade. DTC043ZE

The USB_VBUS pin of BG96 is used for USB detection, and VBUS_CTRL

n
B powers on and off VBUS. B
PSM Mode PSM_IND PSM_IND_M State STATUS STATUS_N
Y 0 1 POWER OFF 0 1
N 1 0 POWER ON 1 0

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[1,2,3,4,5] VDD_EXT VDD_MCU [4,5]

C
R508 Q506 SI2333CDS-T1 C524
[2,3,7] VBAT USB_VBUS R516 R517
0R S D [1,5,7] [1,2,3,4,5] VDD_EXT VDD_EXT [1,2,3,4,5] 4.7K 1nF 4.7K
G

R504 C525
10K R518 R519 Q505
4.7K 4.7K 1nF [1] TXD3_MODULE TXD3 [5]
2SC4617TLQ
[5] VBUS_CTRL Q508
Q507
DTC043ZE [1] RXD3_MODULE RXD3 [5] A
A 2SC4617TLQ
Quectel Wireless Solutions
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Lyndon LIU BG96 Reference Design
SIZE VER
CHECKED BY A2 A
Woody WU SHEET 5 OF 9 DATE 2017/8/14

6 5 4 3 2 1
 6 5 4 3 2 1

RF and GNSS Design

l
D D

c t e l
Main Antenna Interface GNSS Antenna Interface

e t i a
VDD
C

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C J601
C603 R602
10R
0.1uF

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J602 L601
R601 0R Active Antenna /
ANT_MAIN [1] 47nH
Passive Antenna

Q ide
C601 C602 C604 100pF
NM NM ANT_GNSS [1]

D601 C605 C606

NM NM
LXES15AAA1-133

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B B

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Notes:

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1. It is recommended to use a PI type matching circuit for the main antenna circuit, so as to ensure convenient subsequent debugging.
2. An external LDO can be selected to supply power according to the active antenna requirement. If the module is designed with a passive antenna, then R602 and L601 are not needed.
3. ESD protection devices should be added to the GNSS antenna interface, and the parasitic capacitance should be less than 0.05pF.

A
A Quectel Wireless Solutions
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Lyndon LIU BG96 Reference Design
SIZE VER
CHECKED BY A2 A
Woody WU SHEET 6 OF 9 DATE 2017/8/14

6 5 4 3 2 1
 6 5 4 3 2 1

Test Points and Indicators

Reserved Test Points Indicators

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D D

J701

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1
VBAT [2,3,5,7]
2

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3 PWRKEY [1,5]

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4
USB_VBUS [1,5]

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5
USB_DM_TEST [1]
6
USB_DP_TEST [1]

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7
DBG_RXD [1]

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8 DBG_TXD [1]
9
Note 4 VBAT VBAT
GPIO26 [1]

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10 GPIO64 [1] C

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11 D710 D711
C
12

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13
R701 R702
D701

D702

D703

D704

ESD9X3.3ST5G D705

ESD9X3.3ST5G D706

ESD9X3.3ST5G D708

ESD9X3.3ST5G D709
ESD9X3.3ST5G D707

2.2K 2.2K

Q ide
ESD9L5.0ST5G

SESD3Z5V
ESD9L5.0ST5G

SD12C.TCT

D
Q701

D
G
[1] NETLIGHT Q702
RUM001L02T2CL

S
G
[1,5] STATUS
RUM001L02T2CL

S
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B Notes: B
1. Both USB and UART2 interfaces are reserved for software debugging.

o
2. USB interface also can be used to upgrade firmware.
3. Keep USB test points as close as possible to USB pins.
Junction capacitance of ESD protection components on USB data lines might influence the signal.
Please pay attention to it. Typically, the capacitance should be less than 1pF.

C
4. The voltage level of UART2 and GPIO interfaces is 1.8V. Do not connect them directly to a 3.3V level.

A
A Quectel Wireless Solutions
DRAWN BY PROJECT TITLE
Lyndon LIU BG96 Reference Design
SIZE VER
CHECKED BY A2 A
Woody WU SHEET 7 OF 9 DATE 2017/8/14

6 5 4 3 2 1
 6 5 4 3 2 1

Audio Codec Design

l
D D

VDD_3.3V
VDD_1V8

VDD_1V8
t e
R822 R823 MICBIAS
0R 0R

c l
R802 0R
VDD_1V8 R813
R801 0R 1K

C808
C809
100nF C810
a
C805 C804 C803 C848 C801 C802
C806 C807 C849

e i
4.7uF 4.7uF 100nF 4.7uF 100nF

2.2uF
2.2uF
NM_33pF
4.7uF 100nF NM_33pF

15
30
29
31
R814

5
6
1.5K

t AVDD

CPVDD

DBVDD
DCVDD
DACREF

MICVDD
C

u
C C824 2.2uF
C811 4.7uF R803 32 MICBIAS1 C815 2.2uF [9] MIC_P MIC+ [8]
CPP1 14

n
0R 2 IN1P/DMC_DAT CPN1 13 C825 2.2uF
[9] MIC_N MIC- [8]
MICBIAS
C816 2.2uF
CPP2 12
[8] MIC+ 3 IN2P CPN2 11 R815 C826

Q ide
[8] MIC- 4 IN2N/JD2 1.5K 10uF
R824 0R C817 1uF
HPO_R 17 SPK_R [9]
0R C818 1uF
U801 HPO_L 20 R825 SPK_L [9]
25 MCLK
0R ALC5616 R816
R804 22 R811 0R C819 1uF
[1] CODEC_PCM_OUT DACDAT1 LOUTL/P 9 SPK_P [9] 1K
R805 0R 21 0R C820 1uF
[1] CODEC_PCM_IN ADCDAT1 LOUTR/N 10 R812 SPK_N [9]
R806 0R 24
[1] CODEC_PCM_CLK BCLK1
R807 0R 23 16 C721 2.2uF
[1] CODEC_PCM_SYNC LRCK1 CPVPP
19 C822 2.2uF
CPVEE

f
C813 C812 C814 18
CPVREF
NM NM NM 8 C823 4.7uF
VREF2
28 GPIO1/IRQ1
SDA 27 I2C_SDA [1]

n
1 JD1 SCL 26 I2C_SCL [1]
VDD_3.3V
R808 NM_10K
B B
33 DGND
7 AGND

R810 R809
4.7K 4.7K

o
VDD_1V8

C
Notes:
1. To ensure that ALC5616 works normally, please follow the power-on and power-off sequences of its power supply.
Power-on Sequence: power on DBVDD/AVDD/DACREF/CPVDD first, and then MICVDD.
Power-off Sequence: power off MICVDD first, and then DBVDD/AVDD/DACREF/CPVDD.
For more details, please refer to ALC5616 datasheet.
2. BG96 module will automatically initialize the codec via I2C interface after it is turned on successfully, so all power supplies for the codec need to be powered on before that.
A
A Quectel Wireless Solutions
DRAWN BY PROJECT TITLE
Lyndon LIU BG96 Reference Design
SIZE VER
CHECKED BY A2 A
Woody WU SHEET 8 OF 9 DATE 2017/8/14

6 5 4 3 2 1
 6 5 4 3 2 1

Audio Interface
Handset Application

l
D D

ESD9X5.0ST5G

e
C901 C902 C903 C904 C905 C906 D901 D902
10pF 33pF 10pF 33pF 10pF 33pF J901

t
F901 0R 4
[8,9] MIC_P
F902 0R 1
[8,9] MIC_N

l
F903 0R 3
[8] SPK_P
0R

c
[8] SPK_N F904 2

C907 C908 C909 C910 C911 C912 D903 D904

a
10pF 33pF 10pF 33pF 10pF 33pF

e i
PESD5V0S1BL

t
C

u
C
Earphone Application

n
[8,9] MIC_N

Q ide
C913 C914 C915
10pF 33pF 4.7uF
Close to earphone interface.

CTIA OMTP
R901 0R M
R902/R905 NM
R902 NM_0R 2 J902
[8,9] MIC_P
4 R901/R904 M NM
[8] SPK_L

f
5
[8] SPK_R 3
1
R903 0R
C916 C917 D905 C918 C919 D906 C920 C921 D907

n
R904 0R R-0805
MIC_P [8,9]
10pF 33pF 10pF 33pF 10pF 33pF
B R905 NM_0R B
ESD9X5.0ST5G PESD5V0S1BL PESD5V0S1BL

o
Notes:
1. The analog output only drives earphone and handset. For larger power loads such as speakers, the design needs to incease the audio power amplifier.
2. The maximum capacitive loading for speaker is 330 pF and the maximum capacitive loading for microphone is 250 pF.

C
3. In handset application, the microphone and speaker signal traces both need to be routed as differential pairs.
4. In earphone application, the microphone signal traces need to be routed as differential pairs.
5. All microphone and speaker signal traces should be routed with total grounding and far away from noise such as clock and DC-DC signals, etc.

A
A Quectel Wireless Solutions
DRAWN BY PROJECT TITLE
Lyndon LIU BG96 Reference Design
SIZE VER
CHECKED BY A2 A
Woody WU SHEET 9 OF 9 DATE 2017/8/14

6 5 4 3 2 1