LAB MANUAL

DIGITAL LOGIC DESIGN

DEPARTMENT OF ELECTRICAL ENGINEERING

NATIONAL UNIVERSITY OF MODERN LANGUAGES | ISLAMABAD
DIGITAL LOGIC DESIGN
OBJECTIVES
• To become familiar with the practical implementation of different logic gates and digital
circuit design concepts.
• To provide necessary skills to the students for developing professional applications using state-
of-the-art tools and technologies.

INTRODUCTION
The Experiments in the Lab have been divided into two major portions: • Hardware Labs • Hardware
Description Language (Verilog) Labs Hardware Labs have been designed to familiarize students with the
Combinational Digital Logic Design and Sequential Digital Logic Design through the implementation of
Digital Logic Circuits using ICs of basic logic gates and some simple digital logic circuits. HDL (Verilog) Labs
have been designed to familiarize students with the HDL based Digital Design Flow. These labs introduce
students with different levels of coding available in Verilog i.e. Gate level, Dataflow level.
Modelsim/synaptiCad tools have been used in these labs. Finally, the skills learned in the HDL labs are
employed to implement some digital logic circuits.

DESIGN SKILLS / TECHNIQUES PRACTICED

The students will practice and implement the following techniques and skills:

1. Converting logic problem to the digital circuit.

2. Use of integrated circuits and IC pin diagram reading.
3. Developing a logic circuit using basic gates.
4. Developing HDL-based digital design flow.
5. Designing professional applications by integrating modern paradigms and approaches.

SOFTWARE TOOLS / TECHNOLOGY INVOLVED/HARDWARE

Following tools and technologies will be used for implementing software programs in lab:

HARDWARE RESOURCES
1. Hardware trainers for logic circuit design and analysis
2. Electronic Chips of all digital gates
3. Power Supplies
SOFTWARE RESOURCES

The lab also consists of the software resources required by the students namely:

1. Pentium-IV PCs (with MS WinXp OS)

2. ModelSim
3. SynaptiCad

EFFECTIVENESS
After completion of the lab, the students will acquire the required skills and knowledge to develop digital
logic design applications. They will be able to analyze a given problem and select suitable controls and
operations for its implementation on hardware as well as computer software. The students will be able
to develop applications that integrate real-time problems and applications.

With the help of the two threads of the lab mentioned above, students will have a clear understanding of
all the three paradigms of implementation of digital logic circuits: • Implementation using ICs for basic
logic gates and simple circuits • Implementation through hardware design language using
ModelSim/synapticad. This makes students adept in basic concepts involved in digital logic design. The
lab contributes a lot to the basic learning of digital systems. This shows the indispensability of the DLD
Lab.
DIGITAL LOGIC DESIGN
DEPARTMENT OF ELECTRICAL ENGINEERING
NATIONAL UNIVERSITY OF MODERN LANGUAGES ISLAMABAD

LAB OUTLINE
Week No. Title of the Lab
Introduction to Lab Equipment and verification of basic logic gates
1 • Introduction to digital trainer i.e. power supply, input-output ports, and
different modules.
• Study logic gates and verify their truth tables.
Introduction to Verilog and synapticad.
2 • Introduction to Verilog design methodologies and conventions.
• Identifiers, number specification, and keywords used in Verilog.
• Module structure and stimulus block in Verilog.
Implementation of Demorgans Law, Distributive Law using gates and
Verilog.
3
• Applications of Demorgans law and Distributive law using basic gates.
• The HDL-based design language of de-morgans law and distributive law
using Verilog.
Simplified Boolean expression to a minimum number of literals using
Logic gates and Verilog.
4
• Simplify Boolean expression using properties.
• The HDL-based design language for simplified expressions using
Verilog.
Design and implementation of adders and subtractors using Logic gates
and Verilog.
5 • Design and construct half adder, full adder, half subtractor and
full subtractor circuits and verify the truth table using logic gates.
• The HDL-based design language for adders and subtractors using
Verilog.
Design and implementation of code converter using logic gates and
6
Verilog.
 • Design and implement 4-bit Binary to gray code converter and Gray to
binary code converter.
• HDL based design language for gray code converters using verilog.
Design and implementation of BCD to Excess-3 and Excess-3 to BCD
converter using logic gates and verilog.
7
• Design and implement 4-bit BCD to Excess-3 and Excess-3 to BCD
converter.
• HDL based design language for Excess-3 converters using verilog.
Open Ended Lab
8
• Design and implement the designated task using gates.
• HDL based design language for designated task using Verilog.
Design and implementation of magnitude comparator using logic gates
and using Verilog.
9 • Design and implement 2 – Bit magnitude comparator using basic
gates.
• HDL based design language for 2-bit magnitude comparator using
Verilog.
Design and implementation of multiplexer and de-multiplexer using logic
gates and Verilog.

10 • Design and implement multiplexer and demultiplexer using logic gates

and study of IC 74150 and IC 74154.
• HDL based design language for multiplexer and demultiplexer using
Verilog.

Design and implementation of encoder and decoder using logic gates and
verilog.
11
• Design and implement encoder and decoder using logic gates
and study of IC 7445 and IC 74147.
• HDL based design language for encoder and decoder using Verilog.
Study of different types of flip flops using gates.
12
• Verify basic flip flops i.e. D-flip flop and JK flip flop using IC.

Design and Implementation of shift register.

13
• Verify serial to parallel shift register using IC.
Implementation of decade counter.
14
• Verify mod 10/decade counter using IC.
Table of Contents
LAB 1: INTRODUCTION TO LAB EQUIPMENT AND VERIFICATION OF BASIC LOGIC GATES .................................... 10
OBJECTIVE:- ................................................................................................................................................................10
PARTS REQUIRED:- .......................................................................................................................................................10
EQUIPMENT REQUIRED:- ................................................................................................................................................10
THEORY ......................................................................................................................................................................10
PROCEDURE:- ..........................................................................................................................................................18
ANALYSIS ....................................................................................................................................................................19
LAB ASSIGNMENT .........................................................................................................................................................19
CONCLUSION ...............................................................................................................................................................19
LAB 2: INTRODUCTION TO VERILOG AND SYNAPTICAD. ......................................................................................... 1
OBJECTIVE ....................................................................................................................................................................1
RESOURCES REQUIRED ....................................................................................................................................................1
THEORY ........................................................................................................................................................................1
PROCEDURE ..................................................................................................................................................................5
ANALYSIS ......................................................................................................................................................................6
LAB ASSIGNMENT ...........................................................................................................................................................6
CONCLUSION .................................................................................................................................................................6
LAB 3: IMPLEMENTATION OF DEMORGANS LAW, DISTRIBUTIVE LAW USING GATES AND VERILOG. ..................... 7
OBJECTIVE ....................................................................................................................................................................7
PARTS REQUIRED:- .........................................................................................................................................................7
EQUIPMENT REQUIRED:- ..................................................................................................................................................7
THEORY:- .....................................................................................................................................................................7
PROCEDURE:- ................................................................................................................................................................8
ANALYSIS ......................................................................................................................................................................9
LAB ASSIGNMENT ...........................................................................................................................................................9
CONCLUSION .................................................................................................................................................................9
LAB 4: SIMPLIFIED BOOLEAN EXPRESSION TO THE MINIMUM NUMBER OF LITERALS. ......................................... 10
OBJECTIVE: ..............................................................................................................................................................10
PARTS REQUIRED:- .......................................................................................................................................................10
EQUIPMENT REQUIRED:- ................................................................................................................................................10
THEORY ......................................................................................................................................................................10
PROCEEDURE:- ........................................................................................................................................................13
ANALYSIS ....................................................................................................................................................................13
LAB ASSIGNMENT .........................................................................................................................................................13
CONCLUSION ...........................................................................................................................................................13
LAB 5: DESIGN AND IMPLEMENTATION OF ADDERS AND SUBTRACTORS USING LOGIC GATES USING VERILOG. . 14
OBJECTIVE:- ................................................................................................................................................................14
PARTS REQUIRED:- .......................................................................................................................................................14
EQUIPMENT REQUIRED:- ................................................................................................................................................14
THEORY:- .................................................................................................................................................................14
PROCEEDURE:- ........................................................................................................................................................20
ANALYSIS ....................................................................................................................................................................20
 LAB ASSIGNMENT .........................................................................................................................................................20
CONCLUSION ...............................................................................................................................................................20
LAB 6: DESIGN AND IMPLEMENTATION OF GRAY TO BINARY AND BINARY TO GRAY CODE CONVERTER USING
LOGIC GATES AND VERILOG. ................................................................................................................................ 21
OBJECTIVE:- ................................................................................................................................................................21
PARTS REQUIRED:- .......................................................................................................................................................21
EQUIPMENT REQUIRED:- ................................................................................................................................................21
THEORY: ..................................................................................................................................................................21
PROCEEDURE:- ........................................................................................................................................................26
ANALYSIS ....................................................................................................................................................................26
LAB ASSIGNMENT .........................................................................................................................................................26
CONCLUSION ...............................................................................................................................................................26
LAB 7: DESIGN AND IMPLEMENTATION OF BCD TO EXCESS-3 AND EXCESS-3 TO BCD CONVERTER USING LOGIC
GATES AND VERILOG. .......................................................................................................................................... 27
OBJECTIVE:- ................................................................................................................................................................27
PARTS REQUIRED:- .......................................................................................................................................................27
EQUIPMENT REQUIRED:- ................................................................................................................................................27
THEORY: ..................................................................................................................................................................27
PROCEDURE:............................................................................................................................................................33
ANALYSIS ....................................................................................................................................................................33
LAB ASSIGNMENT .........................................................................................................................................................33
CONCLUSION ...............................................................................................................................................................33
LAB 8: OPEN ENDED LAB ...................................................................................................................................... 34
STATEMENT: ...............................................................................................................................................................34
OBJECTIVES OF OPEN-ENDED LAB.....................................................................................................................................34
LAB 9: DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR USING LOGIC GATES AND USING
VERILOG .............................................................................................................................................................. 35
OBJECTIVE:- ................................................................................................................................................................35
PARTS REQUIRED:- .......................................................................................................................................................35
APPARATUS:- ..............................................................................................................................................................35
THEORY: ..................................................................................................................................................................35
PROCEDURE:............................................................................................................................................................39
ANALYSIS ....................................................................................................................................................................39
LAB ASSIGNMENT .........................................................................................................................................................39
CONCLUSION ...............................................................................................................................................................39
LAB 10: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DE-MULTIPLEXER USING LOGIC GATES AND
VERILOG. ............................................................................................................................................................. 40
OBJECTIVE:- ................................................................................................................................................................40
PARTS REQUIRED:- .......................................................................................................................................................40
EQUIPMENT:- ..............................................................................................................................................................40
THEORY:- .................................................................................................................................................................40
PROCEDURE:............................................................................................................................................................45
ANALYSIS ....................................................................................................................................................................45
LAB ASSIGNMENT .........................................................................................................................................................45
 CONCLUSION ...............................................................................................................................................................45
LAB 11: DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER USING LOGIC GATES AND VERILOG. ........ 46
OBJECTIVE:- ................................................................................................................................................................46
PARTS REQUIRED-: .......................................................................................................................................................46
APPARATUS:- ..............................................................................................................................................................46
THEORY: ..................................................................................................................................................................46
............................................................................................................................................................................ 47
PROCEDURE:............................................................................................................................................................49
ANALYSIS ....................................................................................................................................................................49
LAB ASSIGNMENT .........................................................................................................................................................49
CONCLUSION ...............................................................................................................................................................49
LAB 12: STUDY OF DIFFERENT TYPES OF FLIP FLOPS USING GATES. ...................................................................... 50
OBJECTIVE:- ................................................................................................................................................................50
PARTS REQUIRED:- .......................................................................................................................................................50
THEORY ......................................................................................................................................................................50
PROCEDURE:............................................................................................................................................................54
ANALYSIS ....................................................................................................................................................................54
LAB ASSIGNMENT .........................................................................................................................................................54
CONCLUSION ...............................................................................................................................................................54
LAB 13: DESIGN AND IMPLEMENTATION OF SHIFT REGISTER............................................................................... 55
OBJECTIVE:- ................................................................................................................................................................55
PARTS REQUIRED:- .......................................................................................................................................................55
THEORY ......................................................................................................................................................................55
PROCEDURE:............................................................................................................................................................59
ANALYSIS ....................................................................................................................................................................59
LAB ASSIGNMENT .........................................................................................................................................................59
CONCLUSION ...............................................................................................................................................................59
LAB 14: IMPLEMENTATION OF DECADE COUNTER. .............................................................................................. 60
OBJECTIVE:- ................................................................................................................................................................60
PARTS REQUIRED:- .......................................................................................................................................................60
THEORY: ..................................................................................................................................................................60
PROCEDURE:............................................................................................................................................................64
ANALYSIS ....................................................................................................................................................................64
LAB ASSIGNMENT .........................................................................................................................................................64
CONCLUSION ...............................................................................................................................................................64
LAB 1: Introduction to Lab Equipment and verification of
basic logic gates
Objective:-

• Introduction to trainer, breadboard, IC and power supply.

• To study about logic gates and verify their truth tables.
Parts required:-

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

4. NAND GATE 2 I/P IC 7400 1

5. NOR GATE IC 7402 1

6. X-OR GATE IC 7486 1

7. NAND GATE 3 I/P IC 7410 1

Equipment required:-
o Trainer/ proto board o Wire
cutter
o Voltmeter
o Patch Cord

Theory
The Breadboard
The breadboard consists of two terminal strips and two bus strips (often broken in the
centre). Each bus strip has two rows of contacts. Each of the two rows of contacts is a
node. That is, each contact along a row on a bus strip is connected together (inside the
breadboard). Bus strips are used primarily for power supply connections, but are also
used for any node requiring a large number of connections. Each terminal strip has 60
rows and 5 columns of contacts on each side of the centre gap. Each row of 5 contacts
is a node.
You will build your circuits on the terminal strips by inserting the leads of circuit
components into the contact receptacles and making connections with 22 -26 gauge
wire. There are wire cutter/strippers and a spool of wire in the lab. It is a good practice
to wire +5V and 0V power supply connections to separate bus strips.

Fig 1. The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs (Integrated
circuits) used during the experiments. Incorrect connection of power to the ICs could
result in them exploding or becoming very hot - with the possible serious injury occurring
to the people working on the experiment! Ensure that the power supply polarity and all
components and connections are correct before switching on power.

Building the Circuit

Throughout these experiments we will use TTL chips to build circuits. The steps for wiring
a circuit should be completed in the order described below:

1. Turn the power (Trainer Kit) off before you build anything!

2. Make sure the power is off before you build anything!

 3. Connect the +5V and ground (GND) leads of the power supply to the power and
ground bus strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the chips in the
same direction with pin 1 at the upper-left corner. (Pin 1 is often identified by a
dot or a notch next to it on the chip package)

5. Connect +5V and GND pins of each chip to the power and ground bus strips on
the breadboard.
6. Select a connection on your schematic and place a piece of hook-up wire
between corresponding pins of the chips on your breadboard. It is better to make
the short connections before the longer ones. Mark each connection on your
schematic as you go, so as not to try to make the same connection again at a later
stage
7. Get one of your group members to check the connections, before you turn the
power on.
8. If an error is made and is not spotted before you turn the power on. Turn the
power off immediately before you begin to rewire the circuit.
9. At the end of the laboratory session, collect you hook-up wires, chips and all
equipment and return them to the demonstrator.
10. Tidy the area that you were working in and leave it in the same condition as it
was before you started

Common Causes of Problems

1. Not connecting the ground and/or power pins for all chips
2. Not turning on the power supply before checking the operation of the circuit.
3. Leaving out wires
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, components at
the start of the experiment and return them to their proper place after you have finished
the experiment. Please inform the demonstrator or technician if you locate faulty
equipment. If you damage a chip, inform a demonstrator, don't put it back in the box of
chips for somebody else to use.

Example Implementation of a Logic Circuit

Build a circuit to implement the Boolean function F = (A.B), please note that the notation
A refers to A. You should use that notation during the write-up of your laboratory
experiments.
 Quad 2 Input 7400 Hex 7404 Inverter

Fig 2. The complete designed and connected circuit

Sometimes the chip manufacturer may denote the first pin by a small indented circle
above the first pin of the chip. Place your chips in the same direction, to save confusion
at a later stage. Remember that you must connect power to the chips to get them to
work.

THEORY:
Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.

OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates. Basic gates form these gates.
 AND GATE:

The AND gate performs a logical multiplication commonly known as AND

function. The output is high when both the inputs are high. The output is low level when
any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when both
the inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low.

The output is low when the input is high.

NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs
are low and any one of the input is low .The output is low level when both inputs are
high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.

X-OR GATE:
The output is high when any one of the inputs is high. The output is low when

both the inputs are low and both the inputs are high.
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE :

SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE:
SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

NOR GATE:

PROCEDURE:-
(a) Place the IC of required on the bread board. Be sure that it is seated firmly,
straddling the notch in the socket, and that none of the pins are bent.

(b) connect Vcc=5V to pin 14 and Ground to pin 7

(c) Pin lay out of the IC is given in Annex connect one of gates. connect
inputs(pin1&2)to SW1 and SW2 and output to the LED

(d) Switch ON the circuit and complete following truth table

(e)Complete the following table measuring input and output voltages with

voltmeter
 Repeat these steps for difference positions of switches and note the output

Questions

(a) The ICs you worked on are from which logic family? How do you get
the answer?
(b) Is there any variation in voltage level for high and low output?
(c) What logic function is performed by the gate in step 6 and 7, if “negative logic”
is used?

(d) The circuit is performing _____ function.

(e) Switch off the circuit carefully disconnect the circuit.

7. Repeat steps for following gates

a. NOT

b. NAND

C. X-OR

Analysis
Build an exclusive OR gate using AND, OR and NOT gate.

Lab Assignment
Read different gates and IC of 74 series.

Conclusion
Gates has been verified
LAB 2: Introduction to Verilog and synapticad.
Objective
Introduction to HDL Based Designing

Resources Required
• A Computer
• ModelSim

Theory
Introduction
HDL (Hardware Description Language) is any language from a class of computer languages, specification
languages, or modeling languages for formal description and design of electronic circuits, and most-
commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to
verify its operation by means of simulation. The two most popular HDLs are Verilog and VHDL. Verilog due
to its similarity to C language is easier to understand so has become most widely used HDL in educational
institutions.

Design Methodologies
There are two basic types of digital design methodologies:
• a top-down designmethodology
• bottom-up design methodology.
In a top-down design methodology, we define the top-level block and identify the sub-blocks
necessary to build the toplevel block. We further subdivide the sub-blocks until we come to leaf cells,
which are the cells that cannot further be divided.
In a bottom-up design methodology, we first identify the building blocks that are available to us.
We build bigger cells, using these building blocks. These cells are then used for higher-level blocks until
we build the top-level block in the design.

Module
Verilog provides the concept of a module. A module is the basic building block in Verilog. A module can
be an element or a collection of lower-level design blocks. In Verilog, a module is declared by the
keyword module. A corresponding keyword endmodule must appear at the end of the module
definition. Each module must have a module_name, which is the identifier for the module, and a
module_terminal_list, which describes the input and output terminals of the module.

module <module_name> (<module_terminal_list>);

//outputs first then inputs
...
<module internals> // Also called module body
...
endmodule
Lexical Conventions
The basic lexical conventions used by Verilog HDL are similar to those in the C programming language.
Verilog contains a stream of tokens. Tokens can be comments, delimiters, numbers, strings, identifiers,
and keywords. Verilog HDL is a case-sensitive language. All keywords are in lowercase.

Whitespace Blank spaces (\b) , tabs (\t) and newlines (\n) comprise the whitespace. Whitespace is
ignored by Verilog except when it separates tokens. Whitespace is not ignored in strings.

Comments
Comments can be inserted in the code for readability and documentation. There are two ways to write
comments. A one-line comment starts with "//". Verilog skips from that point to the end of line. A
multiple-line comment starts with "/*" and ends with "*/". Multipleline comments cannot be nested.
However, one-line comments can be embedded in multiple-line comments.

a = b && c; // This is a one-line comment

/* This is a multiple line
comment */

Operators
Operators are of three types: unary, binary, and ternary. Unary operators precede the operand. Binary
operators appear between two operands. Ternary operators have two separate operators that separate
three operands.
a = ~ b; // ~ is a unary operator. b is the operand
a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands number.

Number Specification
There are two types of number specification in Verilog: sized and unsized.
a) Sized numbers Sized numbers are represented as <size> '<base format> <number>.
<size> is written only in decimal and specifies the number of bits in the number. Legal base formats are
decimal ('d or 'D), hexadecimal ('h or 'H), binary ('b or 'B) and octal ('o or 'O). The number is specified as
consecutive digits from 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f. Only a subset of these digits is legal for a
particular base. Uppercase letters are legal for number specification.
4'b1111 // This is a 4-bit binary number
12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal

b) Unsized numbers
Numbers that are specified without a <base format> specification are decimal numbers by default.
Numbers that are written without a <size> specification have a default number of bits that is simulator
and machine-specific (must be at least 32).

23456 // This is a 32-bit decimal number by default

'hc3 // This is a 32-bit hexadecimal number
'o21 // This is a 32-bit octal number
Strings
A string is a sequence of characters that are enclosed by double quotes. The restriction on a string is
that it must be contained on a single line, that is, without a carriage return. It cannot be on multiple
lines. Strings are treated as a sequence of one-byte ASCII values.
"Hello Verilog World" // is a string
"a / b" // is a string

Identifiers and Keywords

Keywords are special identifiers reserved to define the language constructs. Keywords are in lowercase.
Identifiers are names given to objects so that they can be referenced in the design. Identifiers are made
up of alphanumeric characters, the underscore ( _ ), or the dollar sign ( $ ). Identifiers are case sensitive.
Identifiers start with an alphabetic character or an underscore. They cannot start with a digit or a $ sign
(The $ sign as the first character is reserved for system tasks).
reg value; // reg is a keyword; value is an identifier
input clk; // input is a keyword, clk is an identifier
Simulation
Once a design block is completed, it must be tested. The functionality of the design block can be tested
by applying stimulus and checking results. We call such a block the stimulus block. It is good practice to
keep the stimulus and design blocks separate. The stimulus block can be written in Verilog. A separate
language is not required to describe stimulus. The stimulus block is also commonly called a test bench.
Different test benches can be used to thoroughly test the design block. Stimulus block is usually of the
form:

module Stimulus;
reg <inputs> //all inputs become reg
wire <outputs> //all outputs becomes wire
<main_module instance> //Instantiation will be discussed
in more detail in future labs
<Simulation conditions with timings> //which give specific
outputs related to design
endmodule

HDL Coding.
Verilog is both a behavioral and a structural language. Internals of each module can be defined at four
levels of abstraction, depending on the needs of the design. The module behaves identically with the
external environment irrespective of the level of abstraction at which the module is described. The
internals of the module are hidden from the environment. Thus, the level of abstraction to describe
a module can be changed without any change in the environment. The levels are defined below.

Behavioral or algorithmic level

This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms
of the desired design algorithm without concern for the hardware implementation details. Designing at
this level is very similar to C programming.
Dataflow level
At this level, the module is designed by specifying the data flow. The designer is aware of how data
flows between hardware registers and how the data is processed in the design.

Gate level
The module is implemented in terms of logic gates and interconnections between these gates. Design at
this level is similar to describing a design in terms of a gate-level logic diagram.
Switch level
This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of
switches, storage nodes, and the interconnections between them. Design at this level requires
knowledge of switch-level implementation details. Verilog allows the designer to mix and match all four
levels of abstractions in a design. Due to increasing complexity of circuits, Switch Level Modeling is
becoming rare so we will not discuss it in these labs.

Gate Types
In this lab, we discuss a design at a low level of abstraction-gate level. Most digital design is now done
at gate level or higher levels of abstraction. At gate level, the circuit is described in terms of gates (e.g.
and nand). Hardware design at this level is intuitive for a user with a basic knowledge of digital logic
design because it is possible to see a one to one correspondence between the logic circuit diagram and
the verilog description.

Basic Gates
Procedure
Analysis
Build a Verilog code exclusive OR gate in combination with AND, OR and NOT gate.

Lab Assignment
Use different gates combination to make your own design circuit .

Conclusion
Verilog code for basic gates has been generated with timing diagram
LAB 3: Implementation of Demorgans Law, Distributive Law using
gates and Verilog.
Objective
Distributive law
o A (B + C) = AB + AC

o (A + B)(C + D) = AC + AD + BC + BD

• DeMorgan’s law

o (A+B)=A. B o (A.B)= A + B

Parts required:-

IC Type 7408 Quadruple 2-input AND gates

IC Type 7432 Quadruple 2-input OR gates

Equipment required:-
• Trainer/ proto board

• Wire cutter
• Patch Cord

• Voltmeter

Theory:-

Distributive law

DeMorgan’s law
Procedure:-
(a) Place the IC of required on the bread board. Be sure that it is seated firmly, straddling the
notch in the socket, and that none of the pins are bent
(b) connect Vcc=5V to pin 14 and Ground to pin 7
(c) Pin lay out of the IC is given in Annex connect one of gates. Connect inputs(pin1&2)to SW1
and SW2 and output to the
LED
(d) Switch ON the circuit and complete following truth tables for both cases for distributive
law
Truth Table
A (B+C) =AB+BC

A B C B+C A(B+C) AB AC AB+AC

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Analysis
Prove commutative law using gates and verilog.

Lab Assignment
Prove commutative law using verilog code and generate a timing diagram.

Conclusion
Demorgan Law and distributive law has been verified.
LAB 4: Simplified Boolean expression to the minimum number of
literals.
OBJECTIVE:
Simplify the Boolean Expression to the minimum number of literals and then demonstrate it on the
breadboard.

Parts required:-

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

Equipment required:-
o Trainer/ proto board o Wire cutter
o Voltmeter
o Patch Cord

Theory

In this lab, we are going to use three gates. One will be AND 2nd will be OR Gate. What we are going to
do is that we will do complex output procedures to demonstrate and prove the given Boolean
expression.
1. AB+A(B+C)+B(B+C)
Simplification:
AB+AB+AC+BB+BC
AB+AC+B+BC
AB+AC+B(1+C)
AB+AC+B
B(A+1)+AC
B(1)+AC
AC+B
LOGIC DIAGRAM:

K-MAP
AC(B+B’) + B(A+A’)(C+C’)
ACB+ACB’ +BA (C+C’) +BA’(C+C’)
ABC+AB’C ABC+AB’C+AB’C+ABC +ABC’ A’BC +A’BC’
(7,5,7,5,5,7,6,3,2)
(2,3,5,6,7)
 1. AB+AC(D+D’)
Simplification:
AB + AC
A(B+C)
Truth Table

A B C B+C A(B+C)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
LOGIC DIAGRAM:

K-MAP
AB+AC
AB(C+C’) + AC(B+B’)
ABC+ABC’ + ABC+ AB’C
(7,6,7,5)
(5,6,7)
C’ C
A’.B’ 0 0
A’.B 0 0
A.B 1 1
 A.B’ 0 1
PROCEEDURE:-

(i) Verify the gates

(ii) Connect the proper power supply
(iii) Connections are given as per circuit diagram.
(iv) Logical inputs are given as per circuit diagram.
(v) Observe the output and verify the truth table.
Analysis
Simplify to minimum number of literals using properties

F=A.B.C+A’+A.B’.C

Lab Assignment
Simplify to minimum number of literals using properties and write a verilog code for simplified and
original expression and generate a timing diagram.

F=A.B.C+A’+A.B’.C

CONCLUSION
Since the output of A(B+C) is correctly displayed on breadboard the experiment has successfully
concluded.
LAB 5: Design and implementation of adders and subtractors using
Logic gates using Verilog.
Objective:-
To design and construct half adder, full adder, half subtractor and full subtractor circuits and verify the
truth table using logic gates.

Parts required:-
Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1

2. X-OR GATE IC 7486 1

3. NOT GATE IC 7404 1

4. OR GATE IC 7432 1

Equipment required:-
• Trainer/ proto board
• Wire cutter
• Patch Cords
• Voltmeter
THEORY:-
HALF ADDER:-
A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’ and other
from the carry ‘ c’ into the higher adder position. Above circuit is called as a carry signal from the addition
of the less significant bits sum from the X-OR Gate the carry out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three
inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In
full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input
and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR Gate,
borrow output can be implemented using an AND Gate and an inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic
circuit should have three inputs and two outputs. The two half subtractor put together gives a full
subtractor.

.The first half subtractor will be C and A B. The output will be difference output of full subtractor. The
expression AB assembles the borrow output of the half subtractor and the second term is the inverted
difference output of first X-OR.

LOGIC DIAGRAM:
HALF ADDER

TRUTH TABLE:
K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:
FULL ADDER
FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:
K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC
LOGIC DIAGRAM:
HALF SUBTRACTOR

TRUTH TABLE:
K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B
LOGIC DIAGRAM:

FULL SUBTRACTOR
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:

K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

Borrow = A’B + BC + A’C

PROCEEDURE:-

(vi) Verify the gates

(vii) Connect the proper power supply
(viii) Connections are given as per circuit diagram.
(ix) Logical inputs are given as per circuit diagram.
(x) Observe the output and verify the truth table.
Analysis
Write a verilog code and generate a timing diagram.

Lab Assignment
Read adders and subtractors from text book.
Conclusion
Adders and subtractors has been verified using gates and verilog
LAB 6: Design and implementation of Gray to Binary and Binary to
Gray code converter using logic gates and verilog.
Objective:-

To design and implement 4-bit

(i) Binary to gray code converter
(ii) Gray to binary code converter

Parts required:-
Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1

Equipment required:-

• Trainer/ proto board

• Wire cutter
• Patch Cords
• Voltmeter
THEORY:

The availability of large variety of codes for the same discrete elements of information results in the use
of different codes by different systems. A conversion circuit must be inserted between the two systems if
each uses different codes for same information. Thus, code converter is a circuit that makes the two
systems compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses four bits to
represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code.

The input variable are designated as B3, B2, B1, B0 and the output variables are designated as C3,
C2, C1, Co. from the truth table, combinational circuit is designed. The Boolean functions are obtained
from K-Map for each output variable.

LOGIC DIAGRAM:

BINARY TO GRAY CODE CONVERTOR

K-Map for G3:

G3 = B3
K-Map for G2:
K-Map for G1:

K-Map for G0:

 LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

B3 = G3
K-Map for B2:

K-Map for B1:

K-Map for B0:

TRUTH TABLE:
PROCEEDURE:-

(i) Verify the gates

(ii) Connect the proper power supply
(iii) Connections are given as per circuit diagram.
(iv) Logical inputs are given as per circuit diagram.
(v) Observe the output and verify the truth table.
Analysis
Write a verilog code and generate a timing diagram.

Lab Assignment
Read applications of gray code.

Conclusion
Gray code has been verified.
LAB 7: Design and implementation of BCD to Excess-3 and Excess-3 to
BCD converter using logic gates and verilog.
Objective:-

To design and implement 4-bit

(i) BCD to excess-3 code converter

(ii) Excess-3 to BCD code converter

Parts required:-

Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1

2. AND GATE IC 7408 1

3. OR GATE IC 7432 1

4. NOT GATE IC 7404 1

Equipment required:-
• Trainer/ proto board
• Wire cutter
• Patch Cords
• Voltmeter

THEORY:

The availability of large variety of codes for the same discrete elements of information results in
the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes
the two systems compatible even though each uses different binary code.

A code converter is a circuit that makes the two systems compatible even though each uses a
different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit
combination of elements as specified by code and the output lines generate the corresponding bit
combination of code. Each one of the four maps represents one of the four outputs of the circuit as a
function of the four input variables.
 A two-level logic diagram may be obtained directly from the Boolean expressions derived by the
maps. These are various other possibilities for a logic diagram that implements this circuit. Now the OR
gate whose output is C+D has been used to implement partially each of three outputs.

LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

K-Map for E3:

K-Map for E2:

K-Map for E1:

K-Map for E0:

TRUTH TABLE:

LOGIC DIAGRAM:
 EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X
K-Map for B:
K-Map for C:

K-Map for D:
PROCEDURE:

(i) verify the gates

(ii) Connect the proper power supply
(iii) Connections were given as per circuit diagram.
(iv) Logical inputs were given as per truth table
(v) Observe the logical output and verify with the truth tables.
Analysis
Design BCD to excess-2 code convertor.

Lab Assignment
Write a verilog code and generate a timing diagram..

Conclusion
BCD to excess-3 and excess-3 to BCD has been verified
LAB 8: Open Ended Lab
Statement:
Design a combinational circuit that generates the 9’s complement of a BCD digit.

Objectives of open-ended lab

1. Design and implement.

(Truth table, K-map (if required), Expression, Logic diagram, etc.)
2. Implementation of logic diagram using Logisim.
3. Verilog implementation using Modelsim.
(Verilog Code, Timing Diagram)
LAB 9: Design and implementation of magnitude comparator using
logic gates and using verilog
Objective:-

To design and implement

(i) 2 – Bit magnitude comparator using basic gates.

Parts required:-
Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2

2. X-OR GATE IC 7486 1

3. OR GATE IC 7432 1

4. NOT GATE IC 7404 1

5. 4-BIT MAGNITUDE IC 7485 2

COMPARATOR

Apparatus:-
• Trainer/ proto board
• Wire cutter
• Patch Cords
• Voltmeter
THEORY:
The comparison of two numbers is an operator that determines one number is greater than, less than (or)
equal to the other number. A magnitude comparator is combinational circuits that compares two

numbers A and B and determine their relative magnitude. The outcome of the comparator
is specified by three binary variables that indicate whether A>B, A=B or A<B.

A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational circuit designated by the symbol
(A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits

starting from most significant position. A is 0 and that of B is 0.

 We have A<B, the sequential comparison can be expanded as
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
The same circuit can be used to compare the relative magnitude of two BCD digits.

Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

¾ ¾ ¾ ¾

x3 x2 x1 x0
LOGIC DIAGRAM:
2 BIT MAGNITUDE COMPARATOR

K MAP
TRUTH TABLE

PIN DIAGRAM FOR IC 7485:

 LOGIC DIAGRAM:

8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

PROCEDURE:
(i) Verify the gates
(ii) Connections are given as per circuit diagram.
(iii) Logical inputs are given as per circuit diagram.
(iv) Observe the output and verify the truth table.
Analysis
Make a truth table for 4-bit magnitude comparator.

Lab Assignment
Write a verilog code and generate a timing diagram..

Conclusion
Magnitude comparator has been verified
LAB 10: Design and implementation of multiplexer and de-multiplexer
using logic gates and Verilog.
Objective:-

To design and implement multiplexer and demultiplexer using logic gates and study of IC

74150 and IC 74154.

Parts required:-

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

Equipment:-
• Trainer/ proto board
• Wire cutter
• Patch Cords
• Voltmeter
THEORY:-
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number of channels
or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is controlled by a
set of selection lines. Normally there are 2n input line and n selection lines whose bit combination
determine which input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information from one
line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known
as a data distributor. Decoder can also be used as demultiplexer.
 In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select
lines enable only one gate at a time and the data on the data input line will pass through the selected gate
to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:
TRUTH TABLE:

PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
Analysis
Draw a block diagram for 8x1 line multiplexer.

Lab Assignment
Write a verilog code and generate a timing diagram..

Conclusion
Multiplexer and demultiplexer has been verified
LAB 11: Design and implementation of encoder and decoder using
logic gates and verilog.
Objective:-
To design and implement encoder and decoder using logic gates and study of IC 7445 and IC 74147.

Parts required-:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1

Apparatus:-
• Trainer/ proto board
• Wire cutter
• Patch Cords
• Voltmeter

THEORY:
ENCODER:

An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2n input lines
and n output lines. In encoder the output lines generates the binary code corresponding to the input
value. In octal to binary encoder it has eight inputs, one for each octal digit and three output that generate
the corresponding binary code. In encoder it is assumed that only one input has a value of one at any
given time otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the
outputs are zero. The zero outputs can also be generated when D0 = 1.

DECODER:
A decoder is a multiple input multiple output logic circuits which converts coded input into coded
output where input and output codes are different. The input code generally has fewer bits than the
output code. Each input code word produces a different output code word i.e. there is one to one mapping
can be expressed in truth table. In the block diagram of decoder circuit the encoded information is present
as n input producing 2n possible outputs. 2n output values are from 0 through out 2n – 1.
PIN DIAGRAM FOR IC 7445:
BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
Analysis
Design and implement 2 to 4 line encoder

Lab Assignment
Write a verilog code and generate a timing diagram.

Conclusion
Encoder and decoder has been verified.
LAB 12: Study of different types of flip flops using gates.
Objective:-
To design and verify D-flipflop and JK-flip flop.

Parts required:-
Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 1

2. D Flip Flop IC 7474 1

Theory
D-Flip Flop

One of the main disadvantages of the basic SR NAND Gate Bistable circuit is that the indeterminate
input condition of SET = “0” and RESET = “0” is forbidden.
This state will force both outputs to be at logic “1”, over-riding the feedback latching action and
whichever input goes to logic level “1” first will lose control, while the other input still at logic “0”
controls the resulting state of the latch.
But in order to prevent this from happening an inverter can be connected between the “SET” and the
“RESET” inputs to produce another type of flip flop circuit known as a Data Latch, Delay flip flop, D-type
Bistable, D-type Flip Flop or just simply a D Flip Flop as it is more generally called.
The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that ensures that
inputs S and R are never equal to one at the same time. The D-type flip flop are constructed from a
gated SR flip-flop with an inverter added between the S and the R inputs to allow for a single D (Data)
input.
Then this single data input, labelled “D” and is used in place of the “Set” signal, and the inverter is used
to generate the complementary “Reset” input thereby making a level-sensitive D-type flip-flop from a
level-sensitive SR-latch as now S = D and R = not D as shown.
D-type Flip-Flop Circuit

We remember that a simple SR flip-flop requires two inputs, one to “SET” the output and one to
“RESET” the output. By connecting an inverter (NOT gate) to the SR flip-flop we can “SET” and “RESET”
the flip-flop using just one input as now the two input signals are complements of each other. This
complement avoids the ambiguity inherent in the SR latch when both inputs are LOW, since that state is
no longer possible.
Thus this single input is called the “DATA” input. If this data input is held HIGH the flip flop would be
“SET” and when it is LOW the flip flop would change and become “RESET”. However, this would be
rather pointless since the output of the flip flop would always change on every pulse applied to this data
input.
To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate the data input
from the flip flop’s latching circuitry after the desired data has been stored. The effect is that D input
condition is only copied to the output Q when the clock input is active. This then forms the basis of
another sequential device called a D Flip Flop.
The “D flip flop” will store and output whatever logic level is applied to its data terminal so long as the
clock input is HIGH. Once the clock input goes LOW the “set” and “reset” inputs of the flip-flop are both
held at logic level “1” so it will not change state and store whatever data was present on its output
before the clock transition occurred. In other words the output is “latched” at either logic “0” or logic
“1”.
Truth Table for the D-type Flip Flop

Note that: ↓ and ↑ indicates direction of clock pulse as it is assumed D-type flip flops are edge
triggered.

Circuit
JK-Flip Flop
The basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic circuits but it
suffers from two basic switching problems.
• 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
• 2. if Set or Reset change state while the enable (EN) input is high the correct latching action may
not occur
Then to overcome these two fundamental design problems with the SR flip-flop design, the JK flip
Flop was developed.
This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a
universal flip-flop circuit. The two inputs labelled “J” and “K” are not shortened abbreviated letters of
other words, such as “S” for Set and “R” for Reset, but are themselves autonomous letters chosen by its
inventor Jack Kilby to distinguish the flip-flop design from other types.
The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop with the
same “Set” and “Reset” inputs. The difference this time is that the “JK flip flop” has no invalid or
forbidden input states of the SR Latch even when S and R are both at logic “1”.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents
the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level
“1”. Due to this additional clocked input, a JK flip-flop has four possible input combinations, “logic 1”,
“logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is similar to that of an SR Bistable
Latch as seen in the previous tutorial except for the addition of a clock input.
The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called
the J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input NAND gates
with the third input of each gate connected to the outputs at Q and Q. This cross coupling of the SR flip-
flop allows the previously invalid condition of S = “1” and R = “1” state to be used to produce a “toggle
action” as the two inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the lower NAND gate. If
the circuit is “RESET” the K input is inhibited by the “0” status of Q through the upper NAND gate.
As Q and Q are always different we can use them to control the input. When both inputs J and K are
equal to logic “1”, the JK flip flop toggles as shown in the following truth table.
The Truth Table for the JK Function

Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its two input
terminals, either SET or RESET to be active at any one time under normal switching thereby eliminating
the invalid condition seen previously in the SR flip flop circuit.
However, if both the J and K inputs are HIGH at logic “1” (J = K = 1), when the clock input goes HIGH, the
circuit will “toggle” as its outputs switch and change state complementing each other. This results in the
JK flip-flop acting more like a T-type toggle flip-flop when both terminals are “HIGH”. However, as the
outputs are fed back to the inputs, this can cause the output at Q to oscillate between SET and RESET
continuously after being complemented once.
While this JK flip-flop circuit is an improvement on the clocked SR flip-flop it also suffers from timing
problems called “race” if the output Q changes state before the timing pulse of the clock input has time
to go “OFF”. To avoid this the timing pulse period ( T ) must be kept as short as possible (high
frequency). As this is sometimes not possible with basic JK flip-flops built using basic NAND or NOR
gates, far more advanced master-slave (edge-triggered) flip-flops were developed which are more
stable.

Circuit
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
Analysis
Draw timing diagrams for flip flops.

Lab Assignment
None

Conclusion
Flip flops has been verified.
LAB 13: Design and Implementation of shift register.
Objective:-
To design and verify serial in parallel out shift register.

Parts required:-
Sl.No. COMPONENT SPECIFICATION QTY.

1. Universal Shift Register IC 74194 1

Theory
Shift Register

This sequential device loads the data present on its inputs and then moves or “shifts” it to its output
once every clock cycle, hence the name Shift Register.
A shift register basically consists of several single bit “D-Type Data Latches”, one for each data bit, either
a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so that the output from
one data latch becomes the input of the next latch and so on.
Data bits may be fed in or out of a shift register serially, that is one after the other from either the left or
the right direction, or all together at the same time in a parallel configuration.
The number of individual data latches required to make up a single Shift Register device is usually
determined by the number of bits to be stored with the most common being 8-bits (one byte) wide
constructed from eight individual data latches.
Shift Registers are used for data storage or for the movement of data and are therefore commonly used
inside calculators or computers to store data such as two binary numbers before they are added
together, or to convert the data from either a serial to parallel or parallel to serial format. The individual
data latches that make up a single shift register are all driven by a common clock ( Clk ) signal making
them synchronous devices.
Shift register IC’s are generally provided with a clear or reset connection so that they can be “SET” or
“RESET” as required. Generally, shift registers operate in one of four different modes with the basic
movement of data through a shift register being:
▪ Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the
stored data being available at the output in parallel form.
▪ Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register, one bit at
a time in either a left or right direction under clock control.
▪ Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously and is
shifted out of the register serially one bit at a time under clock control.
▪ Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the register, and
transferred together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can be presented graphically as:
Also, the directional movement of the data through a shift register can be either to the left, (left shifting)
to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting within the same
register thereby making it bidirectional. In this tutorial it is assumed that all the data shifts to the right,
(right shifting).
Serial-in to Parallel-out (SIPO) Shift Register
4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been RESET ( CLEAR
input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output
of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs still
remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned LOW again to
logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output of FFB and QB HIGH to
logic “1” as its input D has the logic “1” level on it from QA. The logic “1” has now moved or been
“shifted” one place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so on until
the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level “0”
because the input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is
shown in the following table until the complete data value of 0-0-0-1 is stored in the register. This data
value can now be read directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output. The truth
table and following waveforms show the propagation of the logic “1” through the register from left to
right as follows.
Basic Data Movement Through A Shift Register

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the register
and will remain there provided clocking of the register has stopped. In practice the input data to the
register may consist of various combinations of logic “1” and “0”. Commonly available SIPO IC’s include
the standard 8-bit 74LS164 or the 74LS594.

Universal Shift Register

Today, there are many high speed bi-directional “universal” type Shift Registers available such as the
TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-function devices that can be
used in either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial, or as a
parallel-to-parallel multifunction data register, hence their name “Universal”.
These universal shift registers can perform any combination of parallel and serial input to output
operations but require additional inputs to specify desired function and to pre-load and reset the device.
A commonly used universal shift register is the TTL 74LS194 as shown below.
4-bit Universal Shift Register 74LS194
Universal shift registers are very useful digital devices. They can be configured to respond to operations
that require some form of temporary memory storage or for the delay of information such as the SISO
or PIPO configuration modes or transfer data from one point to another in either a serial or parallel
format. Universal shift registers are frequently used in arithmetic operations to shift data to the left or
right for multiplication or division.

Circuit
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
Analysis
Draw a timing diagram for shift register.

Lab Assignment
None

Conclusion
Shift Register has been verified
LAB 14: Implementation of decade counter.

Objective:-
To design and verify 4 bit decade counter

Parts required:-
Sl.No. COMPONENT SPECIFICATION QTY.

1. Decade Counter IC 7490 1

THEORY:
To make a digital counter which counts from 1 to 10, we need to have the counter count only the binary
numbers 0000 to 1001. That is from 0 to 9 in decimal and fortunately for us, counting circuits are readily
available as integrated circuits with one such circuit being the Asynchronous 74LS90 Decade Counter.
Digital counters count upwards from zero to some pre-determined count value on the application of a
clock signal. Once the count value is reached, resetting them returns the counter back to zero to start
again.
A decade counter counts in a sequence of ten and then returns back to zero after the count of nine.
Obviously to count up to a binary value of nine, the counter must have at least four flip-flops within its
chain to represent each decimal digit as shown.
BCD Counter State Diagram

Then a decade counter has four flip-flops and 16 potential states, of which only 10 are used and if we
connected a series of counters together we could count to 100 or 1,000 or to whatever final count
number we choose.
The total number of counts that a counter can count too is called its MODULUS. A counter that returns
to zero after n counts is called a modulo-n counter, for example a modulo-8 (MOD-8), or modulo-16
(MOD-16) counter, etc, and for an “n-bit counter”, the full range of the count is from 0 to 2n-1.
But as we saw in the Asynchronous Counters tutorial, that a counter which resets after ten counts with a
divide-by-10 count sequence from binary 0000 (decimal “0”) through to 1001 (decimal “9”) is called a
“binary-coded-decimal counter” or BCD Counter for short and a MOD-10 counter can be constructed
using a minimum of four toggle flip-flops.
It is called a BCD counter because its ten state sequence is that of a BCD code and does not have a
regular pattern, unlike a straight binary counter. Then a single stage BCD counter such as the 74LS90
counts from decimal 0 to decimal 9 and is therefore capable of counting up to a maximum of nine
pulses. Note also that a digital counter may count up or count down or count up and down
(bidirectional) depending on an input control signal.
Binary-coded-decimal code is an 8421 code consisting of four binary digits. The 8421 designation refers
to the binary weight of the four digits or bits used. For example, 23 = 8, 22 = 4, 21 = 2 and 20 = 1. The main
advantage of BCD code is that it allows for the easy conversion between decimal and binary forms of
numbers.
The 74LS90 BCD Counter

The 74LS90 integrated circuit is basically a MOD-10 decade counter that produces a BCD output code.
The 74LS90 consists of four master-slave JK flip-flops internally connected to provide a MOD-2 (count-
to-2) counter and a MOD-5 (count-to-5) counter. The 74LS90 has one independent toggle JK flip-flop
driven by the CLK A input and three toggle JK flip-flops that form an asynchronous counter driven by
the CLK B input as shown.
74LS90 BCD Counter LOGIC DIAGRAM FOR MOD

The counters four outputs are designated by the letter symbol Q with a numeric subscript equal to the
binary weight of the corresponding bit in the BCD counter circuits code. So for
example, QA, QB, QC and QD. The 74LS90 counting sequence is triggered on the negative going edge of
the clock signal, that is when the clock signal CLK goes from logic 1 (HIGH) to logic 0 (LOW).
The additional input pins R1 and R2 are counter “reset” pins while inputs S1 and S2 are “set” pins. When
connected to logic 1, the Reset inputs R1 and R2 reset the counter back to zero, 0 (0000), and when the
Set inputs S1 and S2 are connected to logic 1, they Set the counter to maximum, or 9 (1001) regardless of
the actual count number or position.
74LS90 Divide-by-10 Counter
Then we can see that BCD counters are binary counters that count from 0000 to 1001 and then resets as
it has the ability to clear all of its flip-flops after the ninth count. If we connect a pushbutton switch
(SW1) to clock input CLKA, each time the pushbutton switch is released the counter will count by one. If
we connected light emitting diodes (LED’s) to the output terminals, QA, QB, QC and QD as shown, we can
view the binary coded decimal count as it takes place.

74LS90 BCD Decade Counter

Successive applications of the push-button switch, SW1 will increase the count up to nine, 1001. At the
tenth application the outputs ABCD will reset back to zero to start a new count sequence. With such a
MOD-10 round number of pulses we can use the decade counter to drive a digital display.

Circuit
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
Analysis
Draw a timing diagram for decade and mod4 counter.

Lab Assignment
None

Conclusion
Decade counter has been verified