Embedded Systems Bus Protocols

• Serial communication sends data bit by bit over a single channel, while
parallel communication sends multiple bits at the same time over multiple
channels.
1.Serial Communication: This refers to the method of transferring data one bit at a
time sequentially over a communication channel or computer bus. In serial
communication, data is transmitted using a single communication line, which reduces
the number of wires required for communication compared to parallel
communication. Serial communication can occur over various physical mediums such
as wires, optical fibers, or even wirelessly.

2.Serial Communication Protocol: A protocol defines the rules and conventions for
communication between devices. In the context of serial communication, a protocol
specifies how data is framed, encoded, transmitted, received, and interpreted. It
includes details such as start and stop bits, baud rate (data transmission speed), error
detection and correction mechanisms, data packet structure, and flow control.
Popular serial communication protocols include UART (Universal Asynchronous
Receiver/Transmitter), SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit),
RS-232, and RS-485.
 Bus Protocols

four-cycle handshake

enq ack
• The microprocessor obviously is not used as a single unit.

• It needs to be linked with memory, extra peripherals, or I/O devices.

• This linking can also be called as Interfacing.

• An interface acts as a communication channel between the processor

and the externally interfaced device.

• I/O interfacing is the link between the processor or CPU and the
various I/O peripherals such as the keyboard, printer, mouse, etc. Such
type of interfacing is referred to as I/O Interfacing.

• The interfacing of the I/O devices can be done in two ways:

• Memory-Mapped I/O Interfacing
• Standard I/O Mapped I/O Interfacing (also known as
isolated I/O interfacing).
What is I/O mapped I/O?
Memory-Mapped I/O Interfacing
The I/O devices and memory, both are
treated as memory.
The I/O devices are provided with 16-
bit address values (in 8085)
The interfaced devices are accessed
by the memory read or memory write
cycles.
The peripherals or the I/O ports are
treated as memory locations. Thus, all
the instructions related to the memory
can be utilized for the data exchange
between the processor and the I/O
device.
In the memory-mapped ports, the
information data can be moved to the
I/O devices from any register or vice
versa.
The full memory address space cannot
be used solely for addressing memory
for interfacing.
Data transfer is possible between any
register and I/O device.
Here, a large number of I/O ports
(216 ports) are possible to be used for
interfacing.
While executing the memory, write or
read cycles, the IO/M` is set to low
(IO/M` = 0 ).
There is more decoder hardware
involved.
Separate control signals are not
required since we have a unified
memory space.
We can perform arithmetic and logical
operations on the data.
I/O Mapped I/O Interfacing
The I/O devices are treated as I/O
devices and the memory is treated as
memory.
The I/O devices are provided with 8-bit
address values. (In 8085)
The interfaced devices are accessed by
the I/O read or I/O write cycles.
Only the IN and the OUT instructions
can be put to use for transferring
information between the I/O device and
the processor.
In the I/O mapped ports, the information
bytes can be moved around between
the ports and the accumulator register
only.
The full memory address space can be
used solely for addressing memory for
interfacing.
Data transfer is possible between the
accumulator and I/O device only.
Only 256 I/O ports i.e., 28 ports, are
made available for interfacing.
While executing the I/O write or read
cycles, the IO/M` is set to high (IO/M` =
1 ).
There is less decoder hardware
involved.
Special control signals are used here
since we have separate memory
spaces.
We cannot perform arithmetic and
logical operations on the data.
Timer/counter are part of micro-controller internal hardware.
Timer counter are same as per hardware point of view.
Timer is used to generate delay and counter is for counting external events.
There is small line between timer and counter which differentiate them.
Timer/Counter module has internal counter register, which plays an important
role.

When we want to count events, we connect external event (e.g. event : rising edge
or falling edge) source to input pin of timer/counter module.
When external event occurs the value of counter increments.
Value of counter represents no. of external events.
E.g. A IR sensor is connected to wheel of vehicle, to calculate speed to vehicle. For
1 rotation of wheel sensor gives 100 pulses. So in this case counter will come in
picture and let us assume counter is configured to calculate events for rising edge.
counter will calculate no. of input pulses.

When we want to generate time delays, we connect external oscillator to input

pin of timer/counter module. At each tick (rising edge or falling edge) of clock
(external oscillator), the value of counter increments and content of counter register
represents time elapsed. As we know the frequency of oscillator we can calculate
time elapsed from.

e.g. A external clock (5 KHz) is connected to micro-controller. In 1 sec it will gives

5000 pulses. Consider timer module is configured to count rising events. We want a
delay of 5 seconds. So when counter reaches to 25000 count, a time of 5 seconds is
elapsed i.e. a delay of 5 second is achieved.
In micro-controller you will see 8 bit timer, 16 bit timer or 32 bit timer module. Now
what is significance of them. In case of 8 bit timer, timer will count clock pulses
maximum 255 and in case of 16 bit counter, timer will count maximum 65535 clock
pulses. If clock of 1 KHz is connected to micro-controller, using 8 bit timer
maximum delay can be achieved is 255 ms and using and using 16 bit timer 65.355
seconds.

How this calculation is done?

Clock frequency is 1KHz and 1/1KHz=0.001 seconds=1ms
i.e. Period of 1 clock pulse is 1ms.
Therefore 255 pulses = 255ms
and 65535 pulses =65.355 seconds
Prescaler of clock : Prescaler is used to achieve a big delay, clock is multiplied using
prescaler value. How? Let us consider above scenario with 8 bit timer and 1KHz
frequency. Maximum delay that can be achieved is 255 ms.

Now consider prescaler with value of 1/2.

New clock = 1 KHz/2 = 500 Hz.
So period of 1 tick equals to 2 ms (1/500Hz) and max delay achieved is 510 ms
(2ms*255 pulses).
Now to achieve big delay increase prescaler value from available values.
Difference Between Timer and Counter:

Timer:
1. A timer uses the frequency of the internal clock, and generates delay.
2. The register incremented for every machine cycle
3. Maximum count rate is 1/12 of the oscillator frequency.

Counter:
1. A counter uses an external signal to count pulses.
2. The register is incremented considering 1 to 0 transition at its
corresponding to an external input pin (T0, T1).
3. Maximum count rate is 1/24 of the oscillator frequency.
A watchdog timer (WDT) is a timer that monitors microcontroller (MCU)
programs to see if they are out of control or have stopped operating. It acts as a
“watchdog” watching over MCU operation. (or)

A watchdog timer (WDT) is a piece of hardware that can be used to automatically

detect software anomalies and reset the processor if any occur.

Generally speaking, a watchdog timer is based on a counter that counts down from
some initial value to zero. The embedded software selects the counter’s initial value
and periodically restarts it. If the counter ever reaches zero before the software
restarts it, the software is presumed to be malfunctioning and the processor’s reset
signal is asserted. The processor (and the embedded software it’s running) will be
restarted as if a human operator had cycled the power.

As shown, the watchdog timer is a chip external to the processor. However, it could
also be included within the same chip as the CPU. This is done in many
microcontrollers. In either case, the output from the watchdog timer is tied directly
to the processor’s reset signal.
 Interrupt
Interrupt Service Routine (ISR) or Interrupt Handler

Hardware Interrupt
Software Interrupt
Polling
Steps to Execute an Interrupt
When an interrupt gets active, the microcontroller goes through the following
steps −
• The microcontroller closes the currently executing instruction and saves the
address of the next instruction (PC) on the stack.
• It also saves the current status of all the interrupts internally (i.e., not on the
stack).
• It jumps to the memory location of the interrupt vector table that holds the
address of the interrupts service routine.
• The microcontroller gets the address of the ISR from the interrupt vector
table and jumps to it. It starts to execute the interrupt service subroutine,
which is RETI (return from interrupt).
• Upon executing the RETI instruction, the microcontroller returns to the
location where it was interrupted. First, it gets the program counter (PC)
address from the stack by popping the top bytes of the stack into the PC.
Then, it start to execute from that address.
Edge Triggering vs. Level Triggering
Interrupt modules are of two types − level-triggered or edge-triggered.
Level Triggered
A level-triggered interrupt module always
generates an interrupt whenever the level of the
interrupt source is asserted.
If the interrupt source is still asserted when the
firmware interrupt handler handles the interrupt,
the interrupt module will regenerate the interrupt,
causing the interrupt handler to be invoked again.
Level-triggered interrupts are cumbersome
for firmware.
Edge Triggered
An edge-triggered interrupt module generates an
interrupt only when it detects an asserting edge of
the interrupt source. The edge gets detected
when the interrupt source level actually changes.
It can also be detected by periodic sampling and
detecting an asserted level when the previous
sample was de-asserted.
Edge-triggered interrupt modules can be acted
immediately, no matter how the interrupt source
behaves.
Edge-triggered interrupts keep the
firmware's code complexity low, reduce the
number of conditions for firmware, and
provide more flexibility when interrupts are
handled.
Enabling and Disabling an Interrupt
Interrupt Enable Register
EA - ET2 ES ET1 EX1 ET0 EX0

•EA − Global enable/disable.

•- − Undefined.
•ET2 − Enable Timer 2 interrupt.
•ES − Enable Serial port interrupt.
•ET1 − Enable Timer 1 interrupt.
•EX1 − Enable External 1 interrupt.
•ET0 − Enable Timer 0 interrupt.
•EX0 − Enable External 0 interrupt.
To enable an interrupt, we take the following steps −
• Bit D7 of the IE register (EA) must be high to allow the rest of register
to take effect.
• If EA = 1, interrupts will be enabled and will be responded to, if their
corresponding bits in IE are high. If EA = 0, no interrupts will respond,
even if their associated pins in the IE register are high.
Interrupt inside Interrupt

Triggering an Interrupt by Software

Latency
The interrupt latency is the interval of time measured from the instant an
interrupt is asserted until the corresponding ISR begins to execute. The worst-
case latency for any given interrupt is a sum of many things, from longest to
shortest:

• The longest period global interrupt recognition is inhibited

• The time it would take to execute all higher priority interrupts if they
occurred simultaneously
• The time it takes the specific ISR to service all of its interrupt requests (if
multiple are possible)
• The time it takes to finish the program instructions in progress and save the
current program state and begin the ISR
Direct Memory Access (DMA) in Embedded Systems
A/D Converters
 Optimizing for low power in embedded MCU
designs
• Low-power embedded design is motivated by the need to run applications for as long
as possible while consuming minimum power. In a battery-powered system, this need
is magnified.
• Furthermore, low power implies lower cost of operation and smaller battery size to
make applications more mobile. When energy comes at a premium as it does with
today’s green initiatives, ensuring that an embedded design consumes as little energy
as possible is even important for wall-powered applications.
• Designing power-efficient applications also ensures less overhead to manage thermal
dissipation, and heat generation is controlled at the source by optimizing the power
consumed.
• Given these advantages, embedded systems engineers can no longer ignore the
problem of optimizing power. This article will focus on the major factors contributing
to power consumption in an embedded system by analyzing the various power modes
which most microcontrollers offer. Then we will analyze a real-life example of an
embedded application in terms of power consumption and how its efficiency can be
maximized.
MCU Power Consumption

Standby Power

Peripheral Power

Battery Life
 Mixed-signal integrated circuit
The particular challenges of mixed signal include:
• CMOS technology is usually optimal for digital performance and scaling
while bipolar transistors are usually optimal for analog performance, yet until
the last decade it has been difficult to either combine these cost-effectively or
to design both analog and digital in a single technology without serious
performance compromises. The advent of technologies like high
performance CMOS, BiCMOS, CMOS SOI and SiGe have removed many of
the compromises that previously had to be made.
• Testing functional operation of mixed-signal ICs remains complex, expensive
and often a "one-off" implementation task.
• Systematic design methodologies comparable to digital design methods are
far more primitive in the analog and mixed-signal arena. Analog circuit design
can not generally be automated to nearly the extent that digital circuit design
can. Combining the two technologies multiplies this complication.
• Fast-changing digital signals send noise to sensitive analog inputs. One path
for this noise is substrate coupling. A variety of techniques are used to attempt
to block or cancel this noise coupling, such as fully differential amplifiers,[5] P+
guard-rings,[6] differential topology, on-chip decoupling, and triple-well
isolation.[7]