Lab - Manual - DIGITAL LOGIC GATES

Faculty of Engineering and Architecture
Electrical and Electronics Eng. Dept. & Computer Eng. Dept.
EXPERIMENT 1
DIGITAL LOGIC GATES
EQUIPMENT:
1- Y-0016 main unit.
2- Multimeter.
3- Integrated Circuits (ICs) and other components:
IC number Definition Quantity

74LS00 Quadruple 2-input NAND gates 1
74LS02 Quadruple 2-input NOR gates 1
74LS04 Hex inverters (six independent gates) 1
74LS08 Quadruple 2-input AND gates 1
74LS32 Quadruple 2-input OR gates 1
74LS86 Quadruple 2-input EX-OR gates 1
74HC266 Quadruple 2-input EX-NOR gates 1
4011 Quadruple 2-input NAND gates 1
4030 Quadruple 2-input EX-OR gates 1
4063 Hex inverters (six independent gates) 1
4077 Quadruple 2-input EX-NOR gates 1
4081 Quadruple 2-input AND gates 1
10 KΩ resistor 1
4. Connection wires.
DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_1

Prof. Dr. Murat UZAM 2015
PRELIMINARY WORK:
1. Read all explanations about this experiment given in the lab manual.
2. Have a look at your course notes and related books about the topics covered in this experiment.
3. By means of a digital simulation software test and verify the operation of the logic gates shown in the
following table.
1 Fig. 1.4.(a) Examination of a 2-input AND gate (2_in_and_gate).
2 Fig. 1.5.(a) Examination of a 3-input AND gate (3_in_and_gate).
3 Fig. 1.8.(a) Examination of a 2-input NAND gate (2_in_nand_gate).
4 Fig. 1.9.(a) The use of a NAND gate as an INVERTER (nand_inverter).
5 Fig. 1.10.(a) Obtaining a 3-input NAND gate using 2-input NAND gates (3_in_nand_gate).
6 Fig. 1.15.(a) Examination of INVERTER (inverter).
7 Fig. 1.16.(a) Converting an AND gate into an OR gate by using inverters (and_to_or_gate).
8 Fig. 1.17.(a) Converting an OR gate into an AND gate by using inverters (or_to_and_gate).
9 Fig. 1.21.(a) Examination of a 2-input OR gate (2_in_or_gate).
10 Fig. 1.22.(a) Examination of a 3-input OR gate (3_in_or_gate).
11 Fig. 1.26.(a) Examination of a 2-input NOR gate (2_in_nor_gate).
12 Fig. 1.27.(a) The use of a NOR gate as an INVERTER (nor_inverter).
13 Fig. 1.28.(a) Obtaining a 3-input NOR gate using 2-input NOR gates (3_in_nor_gate).
14 Fig. 1.31.(a) Examination of a 2-input EX-OR gate (2_in_xor_gate).
15 Fig. 1.34.(a) Examination of a 2-input EX-NOR gate (2_in_xnor_gate).
4. In the above table there are 15 figures numbered as Fig. 1.XX.(a) referring to the schematic diagrams
of experiments to be done. As preliminary work you are obliged to draw by hand using pencils an
application circuit provided in Fig. 1.XX.(b) for each schematic diagram given in Fig. 1.XX.(a). It is
recommended that you use red colour for Vcc, black colour for GND and other colours for other
connections.
5. There are some questions to be answered in the report form for this experiment. Have a look at these
questions and try to answer them before coming for the experiment. The quiz you will take before the
experiment may contain some of these questions.
NOTE: You are obliged to have a copy of the page number 1_1 from “the experiment report form
1” when you start doing this experiment.

EXAMINATION OF AND GATE
OBJECTIVES:
1- Getting to know digital logic AND gate and verifying its logic operation,
2- Obtaining 3-input and 4-input AND gates by using 2-input AND gates.
PRELIMINARY INFORMATION:
1- In a logic operation, HIGH (H) level is represented by number “1” and LOW (L) level is represented
by number “0”.
2- For TTL ICs, H (1) represents voltage levels between 2,4V and 5V. Similarly, L (0) represents
voltage levels between 0 V and 0,4 V.
3- For CMOS ICs, voltage equivalent of H (1) is approximately the supply voltage and L (0) represents
voltage levels between 0V and 0,5 V.
4- AND gate is the multiplication gate. It has at least two inputs. At least one “0” input makes the output
“0”. The output is “1” only when all the inputs are “1” (Table 1.1).
5- The output of a 2-input AND gate is Y= A . B (Fig. 1.1).
6- As can be seen from Fig. 1.2, both TTL IC 7408 and CMOS IC 4081 contain 4 AND gates.
7- The output of a 3-input AND gate (Fig. 1.3) is Y= A.B.C (Table 1.2).
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1
Fig. 1.1. 2-input AND gate. Table 1.1. The truth table of 2-input AND gate.
TTL AND 7408 CMOS AND 4081

Fig. 1.2
A B C Y=A.B.C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Fig. 1.3. 3-input AND gate. Table 1.2. The truth table of 3-input AND gate.

EXPERIMENT NO: 1.1

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE AND GATE
Equipment:
1. Y-0016 main unit.
2. Multimeter.
3. Integrated circuits (ICs):
74LS08 Quadruple 2-input AND gates 1 IC
4081 Quadruple 2-input AND gates 1 IC
Fig. 1.4.(a) Examination of a 2-input AND gate (2_in_and_gate).
Note: Do not forget to connect the Vcc pin to +5 V and the GND pin to ground (GND) connection.
Fig. 1.4.(b) Examination of a 2-input AND gate – application circuit.

Procedure:
1- Construct the circuit [as given in Fig. 1.4.(a) and] as drawn by you in Fig. 1.4.(b) and apply the
power.
2- Apply logic 0 (L) to both inputs.
3- Using the LEDs investigate whether the output of 2-input AND gate is 1 (H) or 0 (L) and take note of
the output in Table 1.3.
4- Measure the same output with voltmeter and find the voltage value and take note of the output
voltage in Table 1.3.
5- Repeat steps 3 and 4 for all the input values given in Table 1.3 and take note of the outputs in Table
1.3.
Voltage value measured by voltmeter

A B Y=A.B
For 74LS08 For 4081
0 0
0 1
1 0
1 1
Table 1.3
NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING CMOS IC

(4081).

EXPERIMENT NO: 1.2

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE 3-INPUT AND GATE
Equipment:
2. Multimeter.
Fig. 1.5.(a) Examination of a 3-input AND gate (3_in_and_gate).
Fig. 1.5.(b) Examination of a 3-input AND gate – application circuit.

Procedure:
power.
2- Apply logic 0 (L) to all three inputs.
3- Using the LEDs investigate whether the output of 3-input AND gate is 1 (H) or 0 (L) and take note of
5- Repeat steps 3 and 4 for all the input values given in Table 1.4 and take note of the output in the
Table 1.4.
A B C Y=A.B.C Voltage value measured by voltmeter

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 1.4

EXAMINATION OF NAND GATE
OBJECTIVES:
1- Getting to know digital logic NAND gate and verifying its logic operation,
2- Deriving its truth table and learning some properties of it.
3- Getting familiar with TTL 74LS00 NAND gate.
4- Analyzing the properties of the circuits composed of 3 or more NAND Gates.
1- NAND Gate provides the output as exactly inverted form of an AND gate.
2- Symbolically this situation is shown with an AND gate having a small circle at the output (Fig. 1.6).
3- The operating principle of a NAND gate can be summarized as; If all inputs are 1(H), the output is 0
(L) and if there is even only one 0 (L) level at any of the inputs, the output is 1(H) (Table 1.5).
4- As can be seen from Fig. 1.7, both TTL IC 7400 and CMOS IC 4011 contain 4 NAND gates.
5- If all inputs of a NAND gate are connected, it can operate as an inverter.
A B A.B Y=(A.B)’
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
Fig. 1.6. 2-input NAND gate. Table 1.5. The truth table of 2-input NAND gate.
TTL NAND 7400 CMOS NAND 4011

Fig. 1.7.

EXPERIMENT NO: 1.3

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE NAND GATE
Equipment:
74LS00 Quadruple 2-input NAND gates 1 IC
4011 Quadruple 2-input NAND gates 1 IC
Fig. 1.8.(a) Examination of a 2-input NAND gate (2_in_nand_gate).
Fig. 1.8.(b) Examination of a 2-input NAND gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 2-input NAND gate is 1 (H) or 0 (L) and take note
of the output in Table 1.6.
4- Repeat step 3 for all remaining input values given in Table 1.6 and take note of the outputs in the
Table.
A B Y=(A.B)’
0 0
0 1
1 0
1 1
Table 1.6.

(4011).

EXPERIMENT NO: 1.4

EXPERIMENT NAME: USING A NAND GATE AS AN INVERTER
Equipment:
Fig. 1.9.(a) The use of a NAND gate as an INVERTER.
Fig. 1.9.(b) The use of a NAND gate as an INVERTER – application circuit.

Procedure:
power.
2- Set the input to logic 0.
3- Using the LEDs investigate whether the output of NAND gate Y is 1 (H) or 0 (L) and take note of the
output in Table 1.7.
5- Using the LEDs investigate whether the output of NAND gate Y is 1 (H) or 0 (L) and take note of the
A (INPUT) Y (OUTPUT)
1
0
Table 1.7.

(4011).

EXPERIMENT NO: 1.5

EXPERIMENT NAME: OBTAINING 3-INPUT NAND GATE USING 2-INPUT NAND GATES
OBJECTIVES:
1- Learning how to increase the number of inputs of a NAND Gate.
2- Deriving the truth table of a 3-input NAND Gate.
Equipment:
Fig. 1.10.(a) Obtaining a 3-input NAND gate using 2-input NAND gates (3_in_nand_gate).
Fig. 1.10.(b) Obtaining a 3-input NAND gate using 2-input NAND gates – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 3-input NAND gate is 1 (H) or 0 (L) and take note
Table.
A B C Y=(A.B.C)’
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 1.8.
NOTE : DO THE SAME EXPERIMENT AGAIN ON BREADBOARD BY USING CMOS IC

(4011).

EXAMINATION OF INVERTER
OBJECTIVES:
1- Getting to know digital logic INVERTER gate and verifying its logical operation,
2- Deriving its truth table.
3- Getting familiar with 74LS04 INVERTER IC.
4- Learning how to convert "an AND gate into an OR gate" and convert "an OR gate into an AND gate"
using INVERTERS.
1- An inverter reverses the logical level at the input (if input=0 then output=1; if input=1 then output=0)
(Table 1.9).
2- Symbolically this situation is denoted with a small circle at the inputs or outputs (Fig. 1.11).
3- Putting a small bar on the top of the letter representing the input or output means reversed logic.
4- This situation is simply named as "NOT".
5- As can be seen from Fig. 1.12, both TTL IC 7404 and CMOS IC 4063 contain 6 INVERTER gates.
INPUT OUTPUT
0 1
1 0
Fig. 1.11. INVERTER gate. Table 1.9. The truth table of the INVERTER gate.
TTL INVERTER 7404 CMOS INVERTER 4063

Fig. 1.12.
Converting an AND gate into an OR gate by using inverters:

According to the De Morgan's law, in order to change multiplication into addition
a-) Input variables are logically reversed.
b-) Multiplication sign is replaced with Addition sign.
c-) The whole process is reversed.
The connection diagram for converting an AND gate into an OR gate by using inverters is shown in Fig.
1.13. The corresponding truth table is provided in Table 1. 10.

Fig. 1.13. Converting an AND gate into an OR gate by using inverters.
INPUTS OUTPUT
INVERSE
A B X=A’.B’ Y=A+B
A’ B’
0 0 1 1 1 0
0 1 1 0 0 1
1 0 0 1 0 1
1 1 0 0 0 1
Table 1.10.
Converting an OR gate into an AND gate by using inverters:
According to the De Morgan's law, in order to change addition into multiplication

a-) Input variables are logically reversed.
b-) Addition sign is replaced with Multiplication sign.
c-) The whole process is reversed.
The connection diagram for converting an OR gate into an AND gate by using inverters is shown in Fig.
1.14. The corresponding truth table is provided in Table 1.11.
Fig. 1.14. Converting an OR gate into an AND gate by using inverters.
INPUTS OUTPUT
INVERSE
A B X=A’+B’ Y=A.B
A’ B’
0 0 1 1 1 0
0 1 1 0 1 0
1 0 0 1 1 0
1 1 0 0 0 1
Table 1.11.

EXPERIMENT NO: 1.6

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE INVERTER
Equipment:
2. Multimeter.
74LS04 Hex inverters (six independent gates) 1 IC
Fig. 1.15.(a) Examination of INVERTER (inverter).
Fig. 1.15.(b) Examination of INVERTER – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of INVERTER gate Y is 1 (H) or 0 (L) and take note
6- Using the LEDs investigate whether the output of INVERTER gate Y is 1 (H) or 0 (L) and take note
A (INPUT) Y (OUTPUT) Voltage value measured by voltmeter

0
1
Table 1.12.

EXPERIMENT NO: 1.7

EXPERIMENT NAME: CONVERTING AN AND GATE INTO AN OR GATE BY USING
INVERTERS
Equipment:
Fig. 1.16.(a) Converting an AND gate into an OR gate by using inverters (and_to_or_gate).
Note: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
Fig. 1.16.(b) Converting an AND gate into an OR gate by using inverters – application circuit.

Procedure:
power.
2- Record the logic level of the output Y for all possible combinations of the inputs A and B in Table
1.13.
INPUTS OUTPUT
INVERSE
Y=A+B
A B A’ B’
0 0 1 1
0 1 1 0
1 0 0 1
1 1 0 0
Table 1.13.

EXPERIMENT NO: 1.8

EXPERIMENT NAME: CONVERTING AN OR GATE INTO AN AND GATE BY USING
INVERTERS
Equipment:
74LS32 Quadruple 2-input OR gates 1 IC
Fig. 1.17.(a) Converting an OR gate into an AND gate by using inverters (or_to_and_gate).
Note: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
Fig. 1.17.(b) Converting an OR gate into an AND gate by using inverters – application circuit.

Procedure:
power.
2- Record the logic level of the output Y for all possible combinations of the inputs A and B in Table
1.14.
INPUTS OUTPUT
INVERSE
Y=AB
A B A’ B’
0 0 1 1
0 1 1 0
1 0 0 1
1 1 0 0
Table 1.14.

EXAMINATION OF OR GATE
OBJECTIVES:
1- Getting to know digital logic OR Gate and verifying its logic operation.
2- Obtaining 3-input or 4-input OR Gates using several 2-input OR Gates.
1- OR Gate is the addition gate. It has at least two inputs. For any of the inputs' 1 (H) condition the
output will be at level 1(H). Only for all inputs are 0 (L), the output will be 0 (L) (Table 1.15).
2- The output of a 2-input OR gate is Y= A+B (Fig. 1.18). The truth table of 2-input OR gate is given in
Table 1.15.
3- The output of a 3-input OR gate is Y= A+B+C (Fig. 1.19). The truth table of 3-input OR gate is given
in Table 1.16.
4- TTL IC 74LS32 contains quadruple 2-input TTL OR gates (Fig. 1.20).
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
Fig. 1.18. 2-input OR gate. Table 1.15. The truth table of 2-input OR gate.
A B C Y=A+B+C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Fig. 1.19. 3-input OR gate. Table 1.16. The truth table of 3-input OR gate.
Fig. 1.20. 2-input TTL OR gate 7432.

EXPERIMENT NO: 1.9

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE OR GATE
Equipment:
Fig. 1.21.(a) Examination of a 2-input OR gate (2_in_or_gate).
Fig. 1.21.(b) Examination of a 2-input OR gate – application circuit.
Procedure
power.
3- Using the LEDs investigate whether the output of 2-input OR gate is 1 (H) or 0 (L) and take note of
4- Repeat step 3 for all other input values given in Table 1.17 and take note of the output in the Table.
A B Y
0 0
0 1
1 0
1 1
Table 1.17.

EXPERIMENT NO: 1.10

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE 3-INPUT OR GATE
Equipment:
Fig. 1.22.(a) Examination of a 3-input OR gate (3_in_or_gate).
Fig. 1.22.(a) Examination of a 3-input OR gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 3-input OR gate is 1 (H) or 0 (L) and take note of
A B C Y (OUTPUT)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 1.18.

EXAMINATION OF NOR GATE
OBJECTIVES:
1- Getting to know digital logic NOR gate and verify its logic operation,
2- Obtaining the truth table and analyzing some properties of it.
3- Getting familiar with TTL 74LS02 NOR Integrated Circuit.
4- Obtaining a 3-input NOR gate by using three 2-input NOR gates.
1- NOR Gate provides the output as exactly inverted form of an OR Gate.
2- Symbolically this situation is shown with an OR gate having a small circle at the output (Fig. 1.23).
3- If any of the inputs is 1 (H) then the output is 0 (L) and when all inputs are 0 (L) then the output is 1
(H) (Table 1.19).
4- If the inputs of the NOR Gate are connected, it can operate as an inverter (Fig. 1.24, Table 1.20).
5- TTL IC 74LS02 contains quadruple 2-input TTL NOR gates (Fig. 1.25).
INPUTS OUTPUT
A B A+B Y=(A+B)’
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
Fig. 1.23. 2-input NOR gate. Table 1.19. The truth table of 2-input NOR gate.
INPUT OUTPUT
0 1
1 0
Fig. 1.24. Using a NOR gate as INVERTER. Table 1.20. The truth table of INVERTER gate.
Fig. 1.25. 2-input TTL NOR gate 7402.

EXPERIMENT NO: 1.11

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE NOR GATE
Equipment:
74LS02 Quadruple 2-input NOR gates 1 IC
Fig. 1.26.(a) Examination of a 2-input NOR gate (2_in_nor_gate).
Fig. 1.26.(b) Examination of a 2-input NOR gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 2-input NOR gate is 1 (H) or 0 (L) and take note of
INPUTS OUTPUT
A B Y = (A+B)’
0 0
0 1
1 0
1 1
Table 1.21.

EXPERIMENT NO : 1.12
EXPERIMENT NAME: USING A NOR GATE AS AN INVERTER
Equipment:
Fig. 1.27.(a) The use of a NOR gate as an INVERTER (nor_inverter).
Fig. 1.27.(b) The use of a NOR gate as an INVERTER – application circuit.
Procedure:
power.
3- Using the LEDs investigate whether the output of NOR gate Y is 1 (H) or 0 (L) and take note of the
5- Using the LEDs investigate whether the output of NOR gate Y is 1 (H) or 0 (L) and take note of the
A(INPUT) Y(OUTPUT)
0
1
Table 1.22.

EXPERIMENT NO : 1.13
EXPERIMENT NAME: OBTAINING A 3-INPUT NOR GATE USING 2-INPUT NOR GATES
Equipment:
Fig. 1.28.(a) Obtaining a 3-input NOR gate using 2-input NOR gates (3_in_nor_gate).
Fig. 1.28.(b) Obtaining a 3-input NOR gate using 2-input NOR gates – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 3-input NOR gate is 1 (H) or 0 (L) and take note of
Table.
INPUTS OUTPUT
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 1.23.

EXAMINATION OF EXCLUSIVE-OR GATE
OBJECTIVES:
1- Getting to know digital logic EX-OR Gate and verifying its logic operation.
2- Getting familiar with TTL 7486 and CMOS 4030 Integrated Circuits.
1- 2-Input EX-OR gate (Fig. 1.29) compares two bits. If the bits are different from each other then the
output becomes 1 (H). If the bits are the same then the output becomes 0 (L) (Table 1.24).
2- EX-OR gate can be formed not only by the help of other gates but also by standard integrated circuits.
3- These circuits are also called Inequality Comparers
4- The parity code, which is an equality code is checked by an EX-OR gate.
4- TTL IC 7486 and CMOS IC 4030 contain quadruple 2-input TTL EX-OR gates (Fig. 1.30).
A B Y=A ⊕ B
0 0 0
0 1 1
1 0 1
1 1 0
Fig. 1.29. 2-input EX-OR gate. Table 1.24. The truth table of 2-input EX-OR gate.
TTL EX-OR gate 7486 CMOS EX-OR gate 4030

Fig. 1.30.

EXPERIMENT NO: 1.14

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE EXCLUSIVE-OR GATE
Equipment:
74LS86 Quadruple 2-input EX-OR gates 1 IC
Fig. 1.31.(a) Examination of a 2-input EX-OR gate (2_in_xor_gate).
Fig. 1.31.(b) Examination of a 2-input EX-OR gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 2-input EX-OR gate is 1 (H) or 0 (L) and take note
4- Repeat step 3 for all other input values given in Table 1.25 and take note of the outputs in the Table.
INPUTS OUTPUT
A B Y=A ⊕ B
0 0
0 1
1 0
1 1
Table 1.25.

EXAMINATION OF EXCLUSIVE-NOR GATE
OBJECTIVES:
1- Getting to know digital logic EX-NOR gate and verifying its logic operation.
2- Observing the parity bit generator circuit and deriving its truth table.
3- Forming an EX-NOR Gate using 7486 or 4077 CMOS EX-OR Gate and 7404 Inverter.
1- 2-Input EX-NOR gate (Fig. 1.32) compares two bits. If the bits are the same then the output becomes
1(H). If the bits are different from each other, then the output becomes 0 (L). (Table 1.26).
2- EX-NOR is the inverted form of EX-OR.
3- EX-NOR gate can be formed not only by the help of other gates but also by standard integrated
circuits.
4- The parity code, i.e. equality code, is produced with EX-NOR Gate.
5- TTL IC 74HC266 and CMOS IC 4077 contain quadruple 2-input TTL EX-NOR gates (Fig. 1.33).
Since the outputs of 74HC266 IC are open-drain, in order to observe a logic signal from an output it is
necessary to connect a pull-up resistor from the output to the power supply.
A B A⊕B Y= (A ⊕ B)’ = AB

0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1
Fig. 1.32. 2-input EX-NOR gate. Table 1.26. The truth table of 2-input EX-NOR gate.
TTL EX-NOR gate 74HC266 CMOS EX-NOR gate 4077

Fig. 1.33

EXPERIMENT NO: 1.15

EXPERIMENT NAME: OBTAINING THE TRUTH TABLE OF THE EXCLUSIVE-NOR GATE
Equipment:
2. Integrated Circuits (ICs) and other components:
74HC266 Quadruple 2-input EX-NOR gates 1 IC
10 KΩ resistor 1
Fig. 1.34.(a) Examination of a 2-input EX-NOR gate (2_in_xnor_gate).
Fig. 1.34.(b) Examination of a 2-input EX-NOR gate – application circuit.

Procedure:
power.
3- Using the LEDs investigate whether the output of 2-input EX-NOR gate is 1 (H) or 0 (L) and take
note of the output in Table 1.27.
4- Repeat step 3 for all other input values given in Table 1.27 and take note of the outputs in the Table.
INPUTS OUTPUT
A B Y = (A ⊕ B)’ = AB
0 0
0 1
1 0
1 1
Table 1.27.


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Faculty of Engineering and Architecture

Electrical and Electronics Eng. Dept. & Computer Eng. Dept.

DIGITAL LOGIC GATES

1- Y-0016 main unit.

3- Integrated Circuits (ICs) and other components:

IC number Definition Quantity

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_1

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_2

EXAMINATION OF AND GATE

TTL AND 7408 CMOS AND 4081

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_3

EXPERIMENT NO: 1.1

Fig. 1.4.(a) Examination of a 2-input AND gate (2_in_and_gate).

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_4

2- Apply logic 0 (L) to both inputs.

Voltage value measured by voltmeter

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING CMOS IC

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_5

EXPERIMENT NO: 1.2

Fig. 1.5.(a) Examination of a 3-input AND gate (3_in_and_gate).

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_6

2- Apply logic 0 (L) to all three inputs.

A B C Y=A.B.C Voltage value measured by voltmeter

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_7

EXAMINATION OF NAND GATE

TTL NAND 7400 CMOS NAND 4011

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_8

EXPERIMENT NO: 1.3

Fig. 1.8.(a) Examination of a 2-input NAND gate (2_in_nand_gate).

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_9

2- Apply logic 0 (L) to both inputs.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING CMOS IC

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_10

EXPERIMENT NO: 1.4

Fig. 1.9.(a) The use of a NAND gate as an INVERTER.

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_11

2- Set the input to logic 0.

4- Set the input to logic 1.

NOTE: DO THE SAME EXPERIMENT AGAIN ON BREARDBOARD BY USING CMOS IC

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_12

EXPERIMENT NO: 1.5

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_13

2- Apply logic 0 (L) to all three inputs.

NOTE : DO THE SAME EXPERIMENT AGAIN ON BREADBOARD BY USING CMOS IC

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_14

TTL INVERTER 7404 CMOS INVERTER 4063

Converting an AND gate into an OR gate by using inverters:

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_15

Fig. 1.13. Converting an AND gate into an OR gate by using inverters.

Converting an OR gate into an AND gate by using inverters:

According to the De Morgan's law, in order to change addition into multiplication

Fig. 1.14. Converting an OR gate into an AND gate by using inverters.

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_16

EXPERIMENT NO: 1.6

Fig. 1.15.(a) Examination of INVERTER (inverter).

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_17

2- Set the input to logic 0.

5- Set the input to logic 1.

A (INPUT) Y (OUTPUT) Voltage value measured by voltmeter

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_18

EXPERIMENT NO: 1.7

DIGITAL DESIGN LABORATORY MANUAL – Experiment 1 1_19