RIYA JAIN

19103029
B1 Batch
COA Tut 5

Q1.
Total instruction length = 16 bit
0 6
i. Operands require 10 bits => Opcode range = 16-10 = 6 bit => 2 to2
0 8
ii. Operand 8 bits => Opcode range = 16-8 = 8 bit => 2 to2
0 10
iii. Operands 6 bits => Opcode range = 16-6 = 10 bit => 2 to2
0 16
iv. Operand 0 bits => Opcode range = 16-0 = 16 bit => 2 to2

Q2.
16
No of instructions encoding =2
No of bits in integer operand = 𝑙𝑜𝑔216 = 4
No of bits in floating point operand = 𝑙𝑜𝑔264 = 16
3*4 14
No of bits consumed by type 1 = 4 * 2 = 2
2*6 15
No of bits consumed by type 2 = 8 * 2 = 2
(4+6) 11
No of bits consumed by type 32 = 14 * 2 = 7 * 2
No of encoding left for type 4 =

16 14 15 11 16 11 3 4
8 * 2 − (2 + 2 + 7 * 2 ) = 2 − 2 (2 + 2 + 7)

11 5 11
= 2 (2 − 31) = 2 = 2048
Total no of different instructions for type 4 = 2048 / 64 = 32

Q3.
a. The next instruction that will be fetched is 97F2 that is an indirect ADD
instruction. The address of operand is at address 7F2.
b. Address of the operand is 0B29 at address 7F2.
Operand is at address 0B29 => operand is 24AF
ADD command: MDR <- M[MAR]
ACC <- ACC + MDR; operand is in MDR
C <- cout, C = 1 bit carry out
ACC = ACC + 24AF = 9ABC + 24AF = BF6B
c. PC = 2AB; 2AB + D
MAR = B29; Address of lost memory reference
MDR = 24AF; 2nd operand
 ACC = BF6B; Result of addition
IR = 97F2; lost instruction fetched = ADD
C = 0; carry out

Q4.
Opcode = 400
Address of instruction = 401
R1 = 200
Value at address field = 100
i. Direct: address will be 100
ii. Immediate: address will be 401
iii. Relative addressing: 402 + 100 = 502
iv. Register indirect addressing: 200
v. Indexed addressing with R1 or index register: 200 + 100 = 300

Q5. Z = (A - B) + C * D - (E + F)
a. Three address instruction
SUB R1, A, B R1 <- M[A] - M[B]
ADD R2, E, F R2 <- M[E] + M[F]
MUL R3, C, D R3 <- M[C] * M[D]
ADD R2, R1, R3 R2 <- R1 + R3
SUB Z, R1, R2 M[Z] <- R1 - R2
b. Two address instruction
MOV R1, A R1 <- M[A]
SUB R1, B R1 <- R1 - M[B]
MOV R2, E R2 <- M[E]
ADD R2, F R2 <- R2 + M[F]
MOV R3, C R3 <- M[C]
MUL R3, D R3 <- R3 + M[D]
ADD R1, R3 R4 <- R1 + R3
SUB R1, R2 R1 <- R1 - R2
MOV Z, R1 M[Z] <- R1
c. One address instruction
LOAD A AC <- M[A]
SUB B AC <- AC - B
STORE T M[T] <- AC
LOAD E AC <-M[E]
ADD F AC <- AC+ M[F]
STORE S M[S] <- AC
LOAD C AC <- M[C]
MUL D AC <- AC * D
ADD T AC <- AC + M[T]
 STORE T M[T] <- AC
LOAD T AC <- M[T]
SUB S AC <- AC - S
STORE Z M[Z] <- AC
d. Zero address instruction can be done in similar manner using stack

Q6.
i. C = A + B
Three address instruction -> ADD C, A, B M[C] = M[A] + M[B]

Two address instruction -> MOV R1, A R1 <- M[A]

ADD R1, B R1 <- R1 + M[B]
MOV C, R1 M[C] <-R1

One address instruction -> LOAD A AC <- M[A]

ADD B AC <- AC + M[B]
STORE C M[X] <- AC

Zero address instruction -> PUSH A TOS <- M[A]

PUSH B TOS <- B
ADD TOS <- A + B
POP C M[C] <- TOS

Ii. D = A-E => It can be done in similar manner as done above

Q7. $S0 = A, $S1 = B, $S2 = C, $S3 = D

3 address architecture
ADD $S0, $S1, $S2 #A = B + C
ADD $ S1, $S0, $S2 #B = A + C
SUB $S3, $S0, $S1 #D = A - B

2 address architecture
MOV $t0, $S2 #t0 = B ___
ADD $t0, $S2 #t0 = t0 + C | A=B+C
MOV $S0, $t0 #A = t0 ___|

MOV $t1, $S0 #t1 = A ___

ADD $t1, $S2 #t2 = t2 + c | B=A+C
MOV $s1, $t1 #B = t1 ___|

MOV $t2, $S0 #t2 = A ___

ADD $t2, $S1 #t2 = t2 - B | D=A-B
MOV $t3, $t2 #D = t2 ___|

1 address architecture
LOAD $S1 #AC = B ___
ADD $S2 #AC = AC + B | A=B+C
STORE $S0 #A = AC ___|

LOAD $S0 #AC = A ___

ADD $S2 #AC = AC +C | B=A+C
STORE $s1 #B = AC ___|

LOAD $S0 #AC = A ___

ADD $S1 #AC = AC - B | D=A-B
STORE $s3 #D = AC ___|

Q8. Data type that can be handled using machine level:

1. Integers
2. Powers
3. BITS fields
4. Strings
5. Floating point
6. MMXth technology Data Type

Q9. There are 7 ways:

1. Immediate Mode
2. Register Mode
3. Implied mode
4. Indexed addressing mode
5. Base indexed addressing mode
6. Absolute addressing mode
7. Auto increment / decrement mode