H61M-DS2

6 S Rev
e 2.0.0
Power Sequence & Power list

-()).2
 H61M-DS2 Power Sequence Rev 2.0
25 MHz

20. PCH_VRMPWRGD 4
4. 3VDUAL_PCH 3
3.
FET
PCH_DPWROK

H61
DPWROK CIRCUIT
2.
-RSMRST 4. 3. FET
Output Clock
16
16. 3VDUAL 5VDUAL
PCIEX1_1,2,
FET
6.5. 8. 21
PCIEX16
5VDUAL CIRCUIT

PWR
VCC18_EN , VCC1_05_EN,

-PFMRST
LAN , IT8213F

RBTSW
VTT PWRGD CIRCUIT
VTT_PWRGD CIRCUIT,
RTL
CPUPWROK
8111E

15. 7. POWER
ITE -PWRBTSW
CIIRCUIT

PWROK1 ITE PWROK1

ITE_PWROK1
IT8728F
14
14. BUTTON

12. IO_PWOK / PWOK 1.

ATX 5VSB
VCCSA
FET 11. -PSON 9. POWER MAIN POWER 10.
19 13.
19. CPU_VTT

CIRCUIT FET VIN 10. DDR_15V,DDRVTT,VCCPLL,VCC1_8_P

VR_RDY

PWRGD

CH,VCC1_05_PCH,VCC1_05_ME,VCC
3_DAC, VCCSA,VCC3_ME,CPU_VTT

22
22. 17.
17 CPU_VAXG
VTT_P
Y

CPUPWROK
-PFMRST1
-CPURST 23. LGA1155
9
9. 6 5.
6. 5
ISL95836HRTZ 18. -CPURST CIRCUIT

VCORE + CPU_VAXG

1
 +0'66\VWHP3RZHU9&&
+0 5HY

VCCPLL
CPU
AT
TX POW VCC1 8 PCH
VCC1_8_PCH
CIRCUIT
VCC3
PCH
WER CONNECT

VCC3
VCC3_ME
ME

ITE8728F

SPI BIOS

ALC887

DDR3
TOR

PCIE*16*1

ESDCM1293A
 +0'66\VWHP3RZHU96%
+0 5HY

5VDUAL
MOSFET
3VDUAL_PCH
ATX PO

MOSFET

3VDUAL
MOSFET PCH
OWER C

VCC3_DAC
MOSFET
FUSE 2N7002

DDR_15V
MOSFET PCIE*16**1
CONNE

2_5LEVEL
ECTOR

IT8728F

KA393D

ESD CM1293A
+0
+0 '66\VWHP3RZHU9&& 5HY

AT
PCH

TX POW
MOSFET Q53

WER CO
GD75232
ONNECT

RT9199PSP

ISL95836
TOR

ESD5
+0'66\VWHP3RZHU9
+0 5HY

ATX PO
OWER CONNEC GD75232

LM358DR

LM324DR

PCIE*16*1
CTOR

BAT54C
+0
+0 '66\VWHP3RZHU9%$79 5HY
VCORE
VIN

ATX
CPU_VAXG
Hi side
V12 MOSFET
LGA1155
CPU_VTT
Hi side
MOSFET
VBAT
IT8728F
PCH
BATT

BAT
TERY

RTCVDD
3.3V
-RTCRST

INTVRMEN
DSWVRMEN
 +0'66\VWHP3RZHU5HY
+0
5VDUAL DDR_15V CPU DDR3
CPU :
DDRVTT DDR3
2_5LEVEL VCORE
VCC1_05_EN
CPU VAXG
CPU_VAXG
VCC1_05_PCH PCH CPU_VTT
VTT_EN VCC1_05_ME PCH
VCCSA
VCCPLL
V12 / VIN CPU_VTT CPU DDR_15V
PCH
VSA_REF
VCCSA CPU
PCH :
VCC1_05_PCH
V12 / VIN VCORE VTT_PWRGD ISL95836 CPU_VTT
CPU_VAXG
VCC1 8 PCH
VCC1_8_PCH
V12 / VIN CPU
VCC3_DAC
VCC1_8_EN
VCC1_8_PCH PCH VCC3_ME
VCC3 VCC1 05 ME
VCC1_05_ME
VCCPLL CPU
3VDUAL VCC3_DAC
PCH

VCC3 VCC3 ME
VCC3_ME
PCH
 Power and Ground Signals
Name Power Description

DcpRTC CAP pull low Decoupling: This signal is for RTC decoupling only. This signal requires decoupling.

DcpSST CAP pull low Decoupling: Internally generated 1.5 V powered off of Suspend Well. This signal requires
decoupling. Decoupling is required even if this feature is not used.
DcpSus 2 CAP pull low 1.05 V Suspend well power.
TP Internal VR mode (INTVRMEN sampled high): Well generated internally. Pins should be left No
Connect External VR mode ((INTVRMEN sampled
p low):
) Well supplied
pp externally.
y Pins
should be powered by 1.05 Suspend power supply. Decoupling capacitors are
required.
NOTE: External VR mode applies to Mobile Only.
DcpSusByp TP Internally generated 1.05 V Deep S4/S5 well power. This rail should not be supplied externally.
NOTE: No decoupling capacitors should be used on this rail.
V5REF VCC/VCC3 Reference for 5 V tolerance on core well inputs. This power may be shut off in S3, S4, S5 or G3
states.
V5REF Sus
V5REF_Sus 5VDUAL/3VDUAL Reference for 5 V tolerance on suspend well inputs
inputs. This power is not expected to be shut off
unless the system is unplugged.

VccCore VCC1_05_PCH 1.05 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3 states.

V 3 3
Vcc3_3 VCC3 3 3 V supply
3.3 l ffor core wellll I/O b
buffers.
ff Thi
This power may b
be shut
h t off
ff iin S3
S3, S4
S4, S5 or G3 states.
t t

VccASW VCC1_05_ME 1.05 V supply for the Active Sleep Well. Provides power to the Intel® ME and integrated LAN.
This plane must be on in S0 and other times the Intel ME or integrated LAN is used.

8
 Power and Ground Signals
Name Power Description

VccDMI CPU_VTT Power supply for DMI.

1.1 V or 1.05 V based on the processor used. Please refer to the respective
processor documentation to find the appropriate voltage level.
VccDIFFCLKN VCC1_05_PCH 1.05 V supply for Differential Clock Buffers. This power is supplied by the corewell.

VccRTC RTCVDD 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not expected
to be shut off unless the RTC batteryy is removed or completely
p y drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC
low. Clearing CMOS can be done by using a jumper on RTCRST# or GPI.
VccIO VCC1_05_PCH 1.05 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3 states.
VccSus3 3
VccSus3_3 3VDUAL 3.3
3 3 V supply for suspend well I/O buffers
buffers. This power is not expected to be shut off unless the
system is unplugged.
VccSusHDA 3VDUAL Suspend supply for Intel® HD Audio. This pin can be either 1.5 or 3.3 V.
VccVRM VCC1_8_PCH 1.5 V/1.8 V supply for internal PLL and VRMs

VccDFTERM VCC1_8_PCH 1.8 V or 3.3 V supply for DF_TVS. This pin should be pulled up to 1.8 V or 3.3 V core.

VccADPLLA VCC1_05_PCH 1.05 V supply for Display PLL A Analog Power. This power is supplied by the core well.

VccADPLLB VCC1_05_PCH 1.05 V supply for Display PLL B Analog Power. This power is supplied by the core well.

VccADAC VCC3_DAC 3.3 V supply for Display DAC Analog Power. This power is supplied by the core well.

9
 Power and Ground Signals
Name Power Description

VccAClk NC 1.05 V Analog power supply for internal clock PLL. This power is supplied by the core well.
NOTE: This pin can be left as no connect
V APLLEXP
VccAPLLEXP NC 1.05
1 05 V A
Analog
l P Power ffor DMI
DMI. Thi
This power iis supplied
li d b
by th
the core well.
ll
NOTE: This pin can be left as no connect
VccAPLLDMI2 NC 1.05 V Analog Power for internal PLL. This power is supplied by core well.
NOTE: This pin can be left as no connect
VccAFDIPLL NC 1.05 V analog power supply for the FDI PLL. This power is supplied by core well.
NOTE: This pin can be left as no connect
VccAPLLSATA NC 1.05 V analog power supply for SATA PLL. This power is supplied by core well. This rail requires
an LC filter when power is supplied from an external VR.
NOTE: This pin can be left as no connect
V_PROC_IO CPU_VTT Powered by the same supply as the processor I/O voltage. This supply is used to drive the
processor interface signals. Please refer to the respective processor documentation to find the
appropriate voltage level.
VccDSW3_3 3VDUAL_PCH 3.3 V supply for Deep S4/S5 wells. If platform does not support Deep S4/S5 then tie to
VccSus3_3.
VccSPI VCC3_ME 3.3 V supply for SPI Controller Logic. This rail must be powered when VccASW is powered.
p
NOTE: This rail can be optionallyyp
powered on 3.3 V Suspendp p
power
(VccSus3_3) based on platform needs.
VccSSC VCC1_05_PCH 1.05 V supply for Integrated Clock Spread Modulators. This power is supplied by core well.

VccClkDMI VCC1_05_PCH 1.05 V supply for DMI differential clock buffer

10
G3 w/RTC Loss to S4/S5 (Without Deep Sx Support) Timing Diagram
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P.11
G3 w/RTC Loss to S4/S5 (With Deep Sx Support) Timing Diagram
G3 Deep Sx S5/S4
VccRTC t225

RTCRST# t200

t200a 3VDUAL_PCH
VccDSW3_3
t200b
DPWROK
t200c ERP / - DEPSLP
_
SLP_SUS# t202
5VDUAL , 3VDUAL

VccSUS
t201
t226
RSMRST#
SUSCLK valid
t202a
SLP_S5# only
l ffor S4 after
ft G3

Note: VccSus rail ramps up later in comparison to VccDSW3_3 due to assumption that SLP_SUS# is
used to control p
power to VccSus.

P.12
 S3/S4/S5 to Deep Sx to G3 w/ RTC Loss Timing Diagram
S3/S4/S5 D
Deep S
Sx G3
SUSWARN# This pin asserts low when the PCH is planning to enter the Deep S4/S5 power state and remove Suspend power
(using SLP_SUS#).
Undriven
SUSACK# If Deep S4/S5 is supported, the EC/motherboard controlling logic must change SUSACK# to match SUSWARN#
-DEPSLP
DEPSLP / ERP : U di
Undriven
SLP_SUS# When asserted low, this signal indicates PCH is in Deep S4/S5 state where internal Sus power is shut
off for enhanced power saving.
Undriven
SLP_S3# /
SLP_A# U di
Undriven

SLP_S4# Undriven
SLP_S4# drops here if not already asserted
SLP_S5# Undriven
SLP_S4# drops here if not already asserted
RSMRST#
DPWROK falling to VccDSW3_3 rail
VccSus falling t235/Min 40ns

DPWROK
DPWROK falling to VccDSW3_3 rail falling t234/Min 40 ns
VccDSW3_3

RTCRST#
RTCRST# deassertion to VccRTC rail falling
VccRTC t236/Min 0 ms

P.13
 H61 Power Sequence Timing
6WR67LPLQJ'LDJUDP
SLP_S5#
SLP S5# 5
5.
SLP_S4# t20Ɩ SLP_S5# high to SLP_S4# high
SLP_S3# 6. t204 SLP_S4# high to SLP_S3# high

SLP_A#
SLP_LAN#
VCC1_05_ME
VccASW t229

Vcc PROCPWRGD Serial VID

CPU SVID Load
V_vld
VCORE
VccCore_CPU
PCH_VRMPWRGD
SYS_PWROK
t205 Vcc active to PWROK high
PWROK1
PWROK t206 PWROK deglitch time
t207 VccASW active to APWROK high ME_PWROK
APWROK may come up earlier
APWROK than PWROK but no later
t230
DRAM_PWROK
25MHz
Crystal Osc St bl
Stable
PCH
Output Clocks Stable
PWROK high to PCH clock outputs stable
t208
PROCPWRGD CPUPWROK t209 PCH clock output stable to PROCPWRGD high
PROCPWRGD and SYS_PWROK high to SUS_STAT# deasserttion t210
SUS_STAT#

THRMTRIP# Ignored Honored

SUS_STST# deassertion to PLRST# deassertion t211

PLTRST# PFMRST#
DMI

P.14
 Power Sequencing and Timings (1)
3 3 V supply for the RTC well
3.3 well.
VccRTC
1. 5VSB 2. 5VDUAL / 2_5LEVEL This signal resets register bits in the RTC well.
RTCRST# 3.3 V supply for Deep Sx wells. If platform does not support Deep Sx then tie to VccSus3_3.
VccDSW 3. 3VDUAL_PCH
3 3 V supply
3.3 l ffor suspend
d wellll I/O b
buffers.
ff Thi
This power iis nott expected
t d tto b
be shut
h t off
ff unless
l th
the system
t iis unplugged.
l d
Vcc_SUS 3-1. 3VDUAL When asserted low, this signal indicates PCH is in Deep S4/S5 state where internal Sus power is shut off for enhanced
power saving.
SLP_SUS# -DEPSLP / ERP :
DPWROK
4. PCH_DPWROK Power OK Indication for the VccDSW3_3 voltage rail. This input is tied together with RSMRST# on platforms that do not support
Deep
p Sx.
This signal is used for resetting the resume power plane logic
RSMRST# 4-1. -RSMRST
If Deep S4/S5 is supported, the EC/motherboard controlling logic must change SUSACK# to match SUSWARN#
SUSWARN# This pin asserts low when the PCH is planning to enter the Deep S4/S5 power state and remove Suspend power (using SLP_SUS#).
SUSACK# This clock is an output of the RTC generator circuit to use by other chips for refresh clock
clock.
SUSCLK Valid
S4_S5# 5. S4 Suspend to Disk) or S5 (Soft Off) state.
SLP_S3# 6. Suspend To RAM
Used to control power to the active sleep well (ASW) of the PCH
PCH. (Could already be high before this sequence begins (to support M3)
M3),but
but will never go
SLP_A# high later than SLP_S3#)

VCCASW VCC1_05_ME 1.05 V supply for the Active Sleep Well. Provides power to the Intel ME and integrated LAN. This plane must be on in S0 and other
times the Intel ME or integrated LAN is used.
PSON# 7.
–PWRBTSW 8.
PWRBTSW 9.
-PSON

+12V,5V,3.3V 10.
10
Vcc_MAIN 11. DDR15V , VCC1_05_PCH , VCC1_8_PCH , VCCPLL
VCCIO 12. CPU_VTT
VCCSA 13.

P.15
 Power Sequencing and Timings (2)
SLP S3#
SLP_S3#
1.05 V supply for the Active Sleep Well. Provides power to the Intel® ME and integrated LAN. This plane must be on in S0 and other
VCCASW VCC1_05_ME times the Intel ME or integrated LAN is used.

VTT_PWRGD 14.
PWROK
15. PWOK 16. PWROK1
Active Sleep Well (ASW) Power OK: When asserted, indicates that
ME_PWROK power to the ASW sub-system is stable.. (APWROK may come up earlier than PWROK, but no later)
APWROK
DRAM_PWROK
PCH 25 MHz Stable
Output Clocks
17
17.
Stable
PROCPWRG 18. CPUPWROK
Serial VID
CPU SVID Load

VCORE 19.
19 V ld
V_vld

SYS_PWROK 20. VR_RDY , 21. PCH_VRMPWRGD SYS_PWROK is used to inform the PCH that power is stable to some other system component(s)
Indicate the system will be entering a low power state soon.
SUS_STAT#
PLTRESET# 22. -PFMRST
PFMRST1,2# 23.
-PCIE_RST #
CPURST#
24.

Notes : In the functional operating mode after RTCRST# deasserts for signals in the RTC well, after
RSMRST# deasserts for signals in the suspend well, after PWROK asserts for signals in the
core well, after DPWROK asserts for Signals in the Deep Sx well, after APWROK asserts for
Signals in the Active Sleep well .
P.16
 S5/Moff-S5/M3 Timing Diagram

S4_S5#

SLP S3#
SLP_S3#

SLP_A# Used to control power to the active sleep well (ASW) of the PCH.

SLP_LAN# Could already be high before this sequence begins (to

support WOL), but will never go high later than SLP_A#

VccASW VccASW active to APWROK high

APWROK high to SPI Soft Strap Reads

APWROK

SPI

P.17